TWI501554B - Pulse generation circuit - Google Patents

Description

Pulse wave generating circuit

The present invention relates to a pulse wave generating circuit, and more particularly to a pulse wave generating circuit in which a transfer curve of an output duty cycle and an input duty cycle is in a monotonously rising relationship.

The voltage conversion circuit is applied to, for example, a motor drive, a ballast, and a Cold Cathode Fluorescent Lamp (CCFL) drive circuit, which utilizes a source of DC or AC voltage source to generate a DC or A large voltage or large current output of the AC to drive the load. In the current voltage conversion circuit, the mainstream of the design is to implement a power component driver stage in a high voltage process-resistant integrated circuit (IC) to drive an external or power component on the same wafer. In general, in addition to the power components, the integrated circuit described above integrates other related control circuits to reduce the size of the application board and the number of external components, and further save costs. However, in order to properly drive the power components, there is usually an external boost capacitor in the application circuit that cooperates with the boost control circuit in the driver stage of the power component to obtain a high voltage to provide the power component driver stage.

FIG. 1 is a circuit diagram of a conventional voltage conversion controller 100. The power components 110, 120 form a circuit configuration of a half-bridge output stage, which alternately outputs high voltage and low voltage at the output terminal 115 in time, wherein the high voltage driver stage for outputting a high voltage is used. A high-side driver (HSD) is coupled to the output terminal 115 as a voltage reference level to efficiently turn on the power component 110, so that during an operation cycle, the high voltage driver The voltage reference level of the internal control circuit of the active stage 130 varies drastically with the output terminal 115. However, the input pulse control signal 160 of the high voltage drive stage 130 is generated with the ground terminal 140 as a voltage reference level. Therefore, in order to avoid malfunction, a pulse wave generating circuit 150 is designed to form the pulse edge signal 161 and the pulse signal 162 respectively after the positive edge and the negative edge of the input pulse wave control signal 160 are respectively formed. After the reference voltage level is converted from the ground terminal 140 to the output terminal 115 by using the level shifter 170, the flip-flop 180 is used to regenerate the power component control signal with the output terminal 115 as the reference voltage level. 190. Since the positive edge and the negative edge of the power component control signal 190 are triggered by the edge of the set pulse signal 162 and the reset pulse signal 161, the operation can reduce the malfunction caused by the change of the reference voltage level with time.

FIG. 2 is a circuit diagram of a conventional pulse wave generating circuit 150. The output signal of the pulse-wave negative-edge delay circuits 210 and 220 is opposite to the input signal, and the delay time t1 between the negative edge of the input signal and the positive edge of the output signal is greater than the input signal. The delay time t2 between the positive edge and the negative edge of the output signal. Fig. 3 is a timing chart of a conventional pulse wave generating circuit 150 in which the timing of the interval A indicates the normal operation of the pulse wave generating circuit 150. The positive edge of the input pulse control signal 160 (corresponding to the waveform 330) triggers the set pulse signal 162 (corresponding to the waveform 362) transition at time a1, and the aforementioned delay time t1 determines the endpoint 260 (corresponding to the waveform 360). The time at which the positive edge occurs determines the pulse width of the pulse signal 162. The negative edge of the input pulse control signal 160 triggers the reset pulse signal 161 (corresponding to the waveform 361) to change state at time a2, and the delay time t1 determines the time at which the positive edge of the endpoint 240 (corresponding to the waveform 340) occurs. Further, the pulse width of the pulse signal 161 is reset. Therefore, the positive edge and the negative edge of the power component control signal 190 (corresponding to the waveform 390) are respectively set by the pulse signal 162. And reset the positive edge trigger of the pulse signal 161.

Referring to FIG. 3, the timing of the interval B indicates that when the pulse width of the input pulse wave control signal 160 is less than the aforementioned delay time t2, that is, when the duty cycle of the input pulse wave control signal 160 is extremely small. . The delay time t2 is usually equivalent to the transmission delay time of several logic gate circuits, which is less than about 100 nanoseconds (ns). At this time, the positive edge of the input pulse wave control signal 160 can still trigger the set pulse wave signal 162 (corresponding to the waveform 362) transition state at time b1, but since the pulse wave width is less than the delay time t2, when the pulse wave control signal 160 is input, the pulse wave control signal 160 is input. When the negative edge occurs at time b2, the end point 240 still does not reflect the positive edge of the input pulse wave control signal 160, so the pulse wave of the reset pulse wave signal 161 does not occur. This result is reflected to the power component control signal 190, that is, a fault that only triggers the positive edge and does not trigger the negative edge, that is, the channel of the power component 110 will remain in the on state. If the input pulse control signal 160 controls the low-side driver (LSD) of the voltage conversion controller 100 and turns on the channel of the power component 120, the simultaneously turned-on power components 110 and 120 will be generated. Supplying the shoot-through current from the voltage source VDD to the ground terminal 140 not only causes malfunction of the voltage conversion circuit, but also burns the power components, and even causes fire and fire, which causes safety problems.

Please refer to FIG. 3, wherein the timing of the interval C indicates that the duty cycle of the input pulse wave control signal 160 is extremely large, and the time when the pulse wave control signal 160 is at a low voltage (ie, t3 in the figure) is less than the delay time. When t2. The negative edge of the input pulse wave control signal 160 triggers the reset pulse wave signal 161 transition state at time c1. However, since the input pulse wave control signal 160 is at a low voltage time t3 is less than the delay time t2, when the pulse wave control signal 160 is input, the pulse wave control signal 160 is input. When the positive edge occurs at time c2, the end point 260 still does not reflect the positive edge of the input pulse wave control signal 160. Therefore, the pulse wave of the pulse signal 162 is not set. This result is reflected to the power component control signal 190, that is, the fault is not triggered, but only the fault that triggers the negative edge, that is, the channel of the power component 110 will remain in a non-conducting state.

Figure 4 is a diagram showing the output duty cycle of the conventional pulse wave generating circuit 150 corresponding to the input The transition curve into the work cycle, wherein the output duty cycle refers to the duty cycle of the power component control signal 190, and the input duty cycle is the duty cycle of the pulse wave control signal 160. Based on the foregoing description, it can be found that when the input duty cycle is close to zero percent, since the channel of the power component 110 is always turned on, the output duty cycle is one hundred percent; and when the input duty cycle is close to the percent At one hundred o'clock, the channel of power component 110 is always non-conducting, so the output duty cycle is zero percent. That is, the output duty cycle does not increase as the input duty cycle increases from zero percent to one hundred percent. However, since the voltage conversion circuit is usually designed in the manner of a negative feedback loop, the components on the loop, usually within their possible application intervals, must have a monotonic increase in the output transfer curve corresponding to the input or The characteristic of monotonic decreasing is such that the negative feedback loop can function normally in its application interval. The transfer curve of the voltage conversion controller 100 will cause the voltage conversion circuit to malfunction when the input duty cycle is too high or too low, thus limiting the range in which the voltage conversion controller 100 is operable.

In view of the above problems, the present invention provides a pulse wave generating circuit that maximizes the interval in which the transfer duty cycle of the output duty cycle and the input duty cycle is monotonously rising.

The invention provides a pulse wave generating circuit for a voltage conversion circuit, the pulse wave generating circuit comprising a first pulse input end, a first monotonic output end, a pulse wave first edge delay circuit, a first inverter circuit, a second inverter circuit, a first switch, a second switch, a third switch, and a latch circuit.

The first pulse input end is for receiving the pulse input signal, and the pulse input signal is There is an input duty cycle and has a first edge and a second edge. The first monotonic output is configured to output a first pulse output signal, and the first pulse output signal has a first output duty cycle. The first edge delay circuit of the pulse wave has an input end and an output end, and an input end of the pulse first edge delay circuit is coupled to the first pulse input end, and an output end of the pulse first edge delay circuit outputs a pulse wave input delay signal The pulse input delay signal is in phase with the pulse input signal, and the delay time of the first edge between the pulse input signal and the pulse input delay signal is greater than the delay time of the second edge. The first inverting circuit has an input end and an output end. The input end of the first inverting circuit is coupled to the output end of the pulse wave positive edge delay circuit, and the signal of the output end of the first inverting circuit and the signal of the input end thereof are mutually For inversion. The second inverting circuit has an input end and an output end. The input end of the second inverting circuit is coupled to the first pulse input end, and the signal of the output end of the second inverting circuit and the signal of the input end thereof are opposite to each other. . The channel of the first switch is coupled between the first reference voltage and the first terminal, and the control end is coupled to the output of the first inverter circuit. The channel of the second switch is coupled between the first end and the second end, and the control end of the second switch is coupled to the output end of the second inverter circuit. The channel of the third switch is coupled between the second terminal and the second reference voltage, and the control terminal of the third switch is coupled to the output of the second inverter circuit. The latch circuit has an input end and an output end. The input end of the latch circuit is coupled to the second end end. The signal at the output end of the latch circuit is inverted from the signal of the input end and coupled to the first monotonic output. End, and when the second endpoint is floating, the signal at the output of the latch circuit remains unchanged. The transfer curve of the first output duty cycle and the input duty cycle is a monotonous rise relationship.

The invention further proposes a pulse wave generating circuit for a voltage converting circuit. Pulse wave The generating circuit includes a pulse input end, a first pulse negative edge delay circuit, a second pulse negative edge delay circuit, a first logic circuit, a second logic circuit, a reset signal, a set signal, a flip-flop, and a monotonic output end.

The pulse input end is used to receive the pulse input signal, and the pulse input signal has the input Into the work cycle. The first pulse wave negative edge delay circuit has a first input end and a first output end, and the first input end is coupled to the pulse wave input end, and the signal of the first output end and the signal of the first input end are mutually inverted. And the delay time between the negative edge of the signal of the first input end and the positive edge of the signal of the first output end is greater than the delay time between the positive edge of the signal of the first input end and the negative edge of the signal of the first output end . The second pulse wave negative edge delay circuit has a second input end and a second output end, the second input end is coupled to the first output end, and the signals of the second output end and the signal of the second input end are mutually inverted. And the delay time between the negative edge of the signal of the second input end and the positive edge of the signal of the second output end is greater than the delay time between the positive edge of the signal of the second input end and the negative edge of the signal of the second output end . The first logic circuit has two input ends and an output end. The two input ends of the first logic circuit are respectively coupled to the pulse wave input end and the first output end, and the output end of the first logic circuit is configured to generate a reset signal. When the two input ends of the first logic circuit are simultaneously inverted signals, the output end of the first logic circuit outputs a positive phase signal, and when the two input ends of the first logic circuit are different, the first logic circuit is an inverted signal The output terminal outputs an inverted signal. The second logic circuit has two input ends and an output end. The two input ends of the second logic circuit are respectively coupled to the first output end and the second output end, and the output end of the second logic circuit is used to generate the setting signal. When the two input ends of the second logic circuit are simultaneously inverted signals, the output end of the second logic circuit outputs a positive phase signal, and when the two input ends of the second logic circuit are different, the second logic circuit is Output output reverse signal number. The output of the flip-flop is coupled to the monotonic output to generate a pulse output signal. The pulse output signal has an output duty cycle, and the positive edge of the pulse output signal is determined by the set signal, and the pulse output signal is negative. The reason is determined by resetting the signal.

The effect of the invention is that the circuit is processed by a high duty cycle and the low working week The serial connection processing circuit can use the pulse wave generating circuit applied to the voltage conversion circuit to have a maximum monotonous rising characteristic interval for the output duty cycle of the input duty cycle, thereby increasing the use range of the voltage conversion circuit and Application flexibility.

Regarding the features, implementations and effects of the present invention, the preferred embodiment is in conjunction with the drawings. The details are as follows.

100‧‧‧Voltage conversion controller

110, 120‧‧‧ Power components

115‧‧‧ Output

130‧‧‧High voltage driver stage

135‧‧‧Low-voltage driver stage

140‧‧‧ Grounding terminal

150, 500, 800, 1200‧‧‧ pulse wave generating circuit

160‧‧‧Input pulse wave control signal

161‧‧‧Reset pulse signal

162‧‧‧Set pulse signal

170‧‧‧Voltage level shifter

180‧‧‧Fracture

190‧‧‧Power component control signals

210, 220, 700‧‧‧ pulse wave negative edge delay circuit

240, 250, 260‧ ‧ endpoints

510‧‧‧ pulse input

520‧‧‧First pulse wave negative edge delay circuit

521‧‧‧ first input

522‧‧‧ first output

530‧‧‧Second pulse negative edge delay circuit

531‧‧‧second input

532‧‧‧second output

540‧‧‧First logic circuit

550‧‧‧Second logic circuit

560‧‧‧Reset signal

570‧‧‧Set the signal

710‧‧‧ pulse wave negative margin delay input

720‧‧‧First negative edge delay inverting circuit

730‧‧‧ Negative edge delay switch

731‧‧‧ Negative Edge Delay Charge Endpoint

740‧‧‧ Negative edge delay charging current

750‧‧‧negative edge delay charging capacitor

760‧‧‧Second negative edge delay inverter circuit

770‧‧‧ Pulse wave negative edge delay output

810, 1211‧‧‧ first pulse input

820, 1212‧‧‧ first monotonic output

830‧‧‧ Pulse first edge delay circuit

840‧‧‧First Inverting Circuit

850‧‧‧second inverter circuit

855‧‧‧First reference voltage

860‧‧‧ first switch

865‧‧‧ first endpoint

870‧‧‧second switch

875‧‧‧second endpoint

880‧‧‧ third switch

885‧‧‧second reference voltage

890‧‧‧Latch circuit

1010‧‧‧Edge delay input

1020‧‧‧Edge delay inverting circuit

1030‧‧‧Edge delay switch

1031‧‧‧Edge Delay Charge Endpoint

1040‧‧‧Edge delay charging current

1050‧‧‧Edge delay charging capacitor

1060‧‧‧Edge buffer stage circuit

1070‧‧‧Edge delay output

1110‧‧‧ input

1120‧‧‧ Output

1130‧‧‧Latch first inverter circuit

1140‧‧‧Latcher second inverter circuit

1210‧‧‧High duty cycle processing circuit

1220‧‧‧Low duty cycle processing circuit

1221‧‧‧second pulse input

1222‧‧‧Second monotonic output

Figure 1 is a circuit diagram of a conventional voltage conversion controller.

Fig. 2 is a circuit diagram of a conventional pulse wave generating circuit.

Figure 3 is a timing diagram of a conventional pulse wave generating circuit.

Figure 4 is a transfer curve of the output duty cycle of the conventional pulse wave generating circuit corresponding to the input duty cycle.

FIG. 5 is a schematic diagram of a pulse wave generating circuit according to a first embodiment of the present invention.

Figure 6 is a timing diagram of the pulse wave generating circuit disclosed in the present invention.

FIG. 7 is a schematic diagram of a pulse wave negative edge delay circuit disclosed in the present invention.

Figure 8 is a schematic diagram of a pulse wave generating circuit of a second embodiment of the present invention.

Figure 9 is a timing diagram of the pulse wave generating circuit disclosed in the present invention.

10 is an embodiment of a pulse wave first edge delay circuit disclosed in the present invention Schematic diagram.

Figure 11 is a schematic diagram of an embodiment of a latch circuit disclosed in the present invention.

Figure 12 is a pulse wave generating circuit of a third embodiment of the present invention schematic diagram.

Fig. 13 is a transfer graph of the pulse wave generating circuit of the third embodiment.

In the context of the specification and subsequent patent applications, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, the first device can be directly electrically connected to the second device or indirectly electrically connected to the second device through other devices or connection means. In addition, the "positive signal" is a state of a digital logic signal, or can be understood as a general digital logic signal state "1", and the "inverted signal" is the state of another digital logic signal, or can be understood as The general digital logic signal status is "0".

FIG. 5 is a schematic diagram of a pulse wave generating circuit 500 according to the first embodiment of the present invention, which is used for a voltage converting circuit. The pulse wave generating circuit 500 includes a pulse wave input terminal 510, a first pulse wave negative edge delay circuit 520, a second pulse wave negative edge delay circuit 530, a first logic circuit 540, a second logic circuit 550, a reset signal 560, and a setting. Signal 570, a flip-flop (not shown), and a monotonic output (not shown).

As shown in FIG. 5, the pulse input terminal 510 is configured to receive a pulse input signal, and the pulse input signal has an input duty cycle. The first pulse-edge delay circuit 520 has a first input end 521 and a first output end 522, and the first input end 521 is coupled to the pulse input end 510. The signal of the first output terminal 522 is opposite to the signal of the first input terminal 521, and the delay time t1 between the negative edge of the signal of the first input terminal 521 and the positive edge of the signal of the first output terminal 522, The delay time t2 between the positive edge of the signal of the first input terminal 521 and the negative edge of the signal of the first output terminal 522.

As shown in FIG. 5, the second pulse-edge delay circuit 530 has a second input end 531 and a second output end 532. The second input end 531 is coupled to the first output end 522 and the second output end 532. The signals from the second input terminal 531 are opposite to each other, and the delay time t1 between the negative edge of the signal of the second input terminal 531 and the positive edge of the signal of the second output terminal 532 is greater than the second input terminal 531. The delay time t2 between the positive edge of the signal and the negative edge of the signal at the second output 532.

As shown in FIG. 5, the first logic circuit 540 has two input terminals and an output terminal. The two input terminals of the first logic circuit 540 are respectively coupled to the pulse input terminal 510 and the first output terminal 522. The first logic circuit The output of 540 is used to generate reset signal 560. When the two input ends of the first logic circuit 540 are both the inverted signal 0, the output of the first logic circuit 540 outputs a positive phase signal 1; and when the two input terminals of the first logic circuit 540 are different, the signal is inverted. The output of the first logic circuit 540 outputs an inverted signal 0. The second logic circuit 550 has two input ends and one output end. The two input ends of the second logic circuit 550 are respectively coupled to the first output end 522 and the second output end 532. The output end of the second logic circuit 550 is used. A set signal 570 is generated. When the two input ends of the second logic circuit 550 are simultaneously the inverted signal 0, the output of the second logic circuit 550 outputs the positive phase signal 1; and when the two input terminals of the second logic circuit 550 are different, the inverted signal is 0. The output of the second logic circuit 550 outputs an inverted signal 0. The first logic circuit 540 and the second logic circuit 550 are respectively a NOR logic circuit, but are not limited thereto.

Further, the flip-flop of the pulse wave generating circuit 500 has an output coupled to the monotonic output for generating a pulse output signal for driving the power component. The pulse output signal has an output duty cycle, and the positive edge of the pulse output signal is determined by the set signal 570, and the negative edge of the pulse output signal is determined by the reset signal 560.

FIG. 6 is a timing diagram of the pulse wave generating circuit 500 disclosed in the present invention. The timing of the interval D indicates the case where the pulse wave generating circuit 500 operates normally. The positive edge of the pulse input signal (corresponding to the waveform 610) occurs at time d1, and after the delay time t2, triggers the first output 522 (corresponding to the waveform 622) to transition, and then triggers the set signal 570 (corresponding to Waveform 670) Transition. The delay time t1 determines the time at which the positive edge of the second output 532 (corresponding to the waveform 632) occurs, thereby determining the pulse width of the set signal 570. The negative edge of the pulse input signal triggers the reset signal 560 (corresponding to the waveform 660) at the time d2, and the delay time t1 determines the time at which the positive edge of the first output 522 (corresponding to the waveform 622) occurs. The pulse width of the reset signal 560 is determined. Therefore, the positive edge and the negative edge of the pulse output signal (corresponding to the waveform 680) are respectively triggered by the positive edge of the set signal 570 and the reset signal 560.

Please refer to FIG. 6 , wherein the timing of the interval E indicates that when the pulse width of the pulse input signal is less than the aforementioned delay time t2, that is, when the duty cycle of the pulse input signal is extremely small. At this time, the positive edge of the pulse input signal occurs at time e1, but since the pulse width is less than the delay time t2, when the negative edge of the pulse input signal occurs at time e2, the first output 522 remains unreacted. Therefore, the pulse of the setting signal 570 and the reset signal 560 does not occur. Therefore, the channel of the power component will remain in the off state. Compared with the pulse wave generating circuit 150 of the prior art, the pulse wave generating circuit 500 disclosed in the present invention can maintain the transfer curve corresponding to the input working period as monotonous when the input duty cycle is close to zero percent. The characteristics of the rise, so as not to cause the malfunction of the negative feedback loop of the voltage conversion circuit.

FIG. 7 is a schematic diagram of the pulse wave negative edge delay circuit 700 of the first pulse wave negative edge delay circuit 520 and the second pulse wave negative edge delay circuit 530 in the pulse wave generating circuit 500 disclosed in the present invention. The pulse wave negative edge delay circuit 700 includes a pulse wave negative edge delay input terminal 710, a first negative edge delay inversion circuit 720, a negative edge delay switch 730, a negative edge delay charging current 740, a negative edge delay charging capacitor 750, and a second negative The edge delay inverting circuit 760 and the pulse negative edge delay output 770.

As shown in FIG. 7, the pulse wave negative edge delay input terminal 710 corresponds to the first input terminal 521 or the second input terminal 531 of the pulse wave generating circuit 500. The first negative edge delay inverting circuit 720 has an input end and an output end. The input end of the first negative edge delay inverting circuit 720 is coupled to the pulse wave negative edge delay input terminal 710, and the first negative edge delay inverting circuit 720. The signal at the output is inverted from the signal at the input. The negative-edge delay switch 730 is a metal-oxide-semiconductor field-effect transistor (MOSFET) or an NPN-type bipolar junction transistor (BJT), but This is limited. The channel of the negative-edge delay switch 730 is coupled between the negative-edge delay charging terminal 731 and the ground, and the control terminal of the negative-edge delay switch 730 is coupled to the output of the negative-edge delay inverting circuit 720.

As shown in FIG. 7, the negative edge delayed charging current 740 is coupled to the negative edge delayed charging terminal 731. The negative edge delay charging capacitor 750 is coupled between the ground terminal and the negative edge delay charging terminal 731. The second negative-edge delay inverting circuit 760 has an input end and an output end, and the input end of the second negative-edge delay inverting circuit 760 is coupled to the negative-edge delay charging terminal 731, and the output of the second negative-edge delay inverting circuit 760 The terminal is coupled to the pulse negative edge delay output 770, and the signal of the output of the second negative edge delay inverting circuit 760 is inverted from the signal of the input terminal.

Further, when the signal of the pulse wave negative edge delay input terminal 710 is changed from the inverted signal 0 to the positive phase signal 1, the channel of the negative edge delay switch 730 is turned off, and the negative edge delay charging current 740 is opposite to the negative edge delay charging capacitor 750. Charging is performed, so the voltage of the negative edge delayed charging terminal 731 gradually rises. After the delay time t1, the voltage of the negative edge delay charging terminal 731 is higher than the transition potential of the second negative edge delay inverting circuit 760, so the signal of the pulse negative edge delay output 770 is inverted to the inverted signal 0. Complete the operation. As described above, the delay time t1 is determined by parameters such as the negative edge delay charging current 740, the negative edge delay charging capacitor 750, and the transition potential of the second negative edge delay inverting circuit 760. In addition, as can be seen from the description of FIG. 6, the pulse width of the reset signal 560 and the set signal 570 is determined by the delay time t1, so that it can be designed accordingly.

In addition, when the signal of the pulse-edge negative-edge delay input terminal 710 is changed from the positive phase signal 1 to the inverted signal 0, the channel of the negative-edge delay switch 730 is turned on to form a path of the equivalent resistor Ron in parallel. The negative-edge delay charging capacitor 750 is discharged through the channel of the negative-edge delay switch 730, so that the voltage of the negative-edge delayed charging terminal 731 gradually decreases. After the delay time t2, the voltage of the negative edge delay charging terminal 731 is lower than the transition potential of the second negative edge delay inverting circuit 760, so that the signal of the pulse negative edge delay output terminal 770 is positive phase signal 1, Complete the operation. As can be seen from the above description, the delay time t2 is determined by parameters such as the channel equivalent resistance Ron of the negative edge delay switch 730, the negative edge delay charging capacitor 750, and the transition potential of the second negative edge delay inverting circuit 760. The delay time t2 in design can be as small as possible.

In another embodiment of the pulse-wave negative-edge delay circuit 700, the negative-edge delayed charging current 740 is a current source of adjustable current value for adjusting the delay time t1. In still another embodiment of the pulse-wave negative-edge delay circuit 700, the negative-edge delay charging capacitor 750 is a capacitive element of a variable capacitance value for adjusting the delay time t1. Delay time t1 can be adjusted to reset the signal The pulse width of the 560 and the set signal 570 can be adjusted according to actual needs, thereby increasing the flexibility of the present invention in application. It should be noted that the above-described pulse wave negative-edge delay circuit 700 embodiment is illustrative of the present invention and is not intended to limit the scope of the present invention. Those skilled in the art can use the present invention. The spirit of the disclosure is based on the practice of the invention.

FIG. 8 is a schematic diagram of a pulse wave generating circuit 800 according to a second embodiment of the present invention, which is used for a voltage converting circuit. The pulse wave generating circuit 800 includes a first pulse input terminal 810, a first monotonic output terminal 820, a pulse wave first edge delay circuit 830, a first inverting circuit 840, a second inverting circuit 850, a first switch 860, and a first A second switch 870, a third switch 880, and a latch circuit 890.

As shown in FIG. 8, the first pulse input terminal 810 is configured to receive a pulse input signal, the pulse input signal has an input duty cycle, and has a first edge and a second edge. The first monotonic output 820 is configured to output a first pulse output signal, and the first pulse output signal has a first output duty cycle. The pulse first edge delay circuit 830 has an input end and an output end. The input end of the pulse wave first edge delay circuit 830 is coupled to the first pulse input end 810, and the output end of the pulse wave first edge delay circuit 830 outputs a The pulse input delay signal, the pulse input delay signal is in phase with the pulse input signal, and the delay time t3 of the first edge between the pulse input signal and the pulse input delay signal is greater than the delay time t4 of the second edge. The first inverting circuit 840 has an input end and an output end. The input end of the first inverting circuit 840 is coupled to the output end of the pulse positive edge delay circuit 830, and the signal of the output end of the first inverting circuit 840 is input to the input end. The signals of the terminals are inverted. The second inverting circuit 850 has an input end and an output end. The input end of the second inverting circuit 850 is coupled to the first pulse input end 810, and the signal of the output end of the second inverting circuit 850 and the signal of the input end thereof Mutual inversion.

As shown in FIG. 8, the channel of the first switch 860 is coupled between the first reference voltage 855 and the first terminal 865, and the control terminal of the first switch 860 is coupled to the output of the first inverter circuit 840. . The second switch 870 is coupled between the first terminal 865 and the second terminal 875, and the control terminal of the second switch 870 is coupled to the output of the second inverter circuit 850. The channel of the third switch 880 is coupled between the second terminal 875 and the second reference voltage 885, and the control terminal of the third switch 880 is coupled to the output of the second inverter circuit 850. The latch circuit 890 has an input end and an output end. The input end of the latch circuit 890 is coupled to the second end point 875. The signal at the output end of the latch circuit 890 is inverted from the signal of the input end and coupled to the signal. The first monotonic output 820, and when the second endpoint 875 is floating, the signal at the output of the latch circuit 890 remains unchanged.

In an embodiment of the pulse wave generating circuit 800, the first edge refers to the positive edge of the pulse signal, the second edge refers to the negative edge of the pulse signal, and the first switch 860 is a P-type field effect transistor or For a PNP type bipolar junction transistor, the second switch 870 is a P-type field effect transistor or a PNP type bipolar junction transistor, and the third switch 880 is an N-type field effect transistor. Or an NPN type bipolar junction transistor. And the first reference voltage 855 is greater than the second reference voltage 885.

FIG. 9 is a timing diagram of an embodiment of a pulse wave generating circuit 800 disclosed in the present invention. Figure 9 illustrates the operation of pulse wave generation circuit 800 when the input duty cycle is high. The negative edge of the pulse input signal (corresponding to waveform 910) occurs at time f1, triggering the output of the second inverting circuit 850 (corresponding to waveform 950) and the first monotonic output 820 (corresponding to waveform 920). And after the elapse of time t4, the output of the pulse wave first edge delay circuit 830 (corresponding to the waveform 930) and the output of the first inverter circuit 840 (corresponding to the waveform 940) are transitioned. When the positive edge of the pulse input signal occurs at time f2, the output of the second inverter circuit 850 is triggered. In the transition state, the channel of the third switch 880 is turned off, and the channel of the second switch 870 is turned on. However, at this time, since the channel of the first switch 860 is not turned on, the second terminal is in a floating state, so that the output of the latch circuit 890, that is, the signal of the first monotonic output terminal 820 remains unchanged. After the time t3, the output of the pulse first edge delay circuit 830 and the output of the first inverter circuit 840 are turned, the channel of the first switch 860 is turned on, and the second terminal is thus coupled to the first reference voltage 855. Therefore, the first monotonic output 820 is in a state of transition. It can be seen from the above description that the duty cycle of the first monotonic output terminal 820 is fixed by a fixed value smaller than the duty cycle of the pulse input signal, and the certain value is determined by the delay time t3. Therefore, the duty cycle of the duty cycle of the output of the pulse wave generating circuit 800 and the duty cycle of its input is monotonically increasing.

In addition, when the output of the pulse wave generating circuit 800, that is, the first monotonic output terminal 820, is input to the conventional pulse wave generating circuit 150, the delay time t3 can be designed to limit the upper limit of the duty cycle of the pulse wave generating circuit 150 input. So that it never enters the interval C in Figure 3. That is, when the pulse wave generating circuit 800 cooperates with the conventional pulse wave generating circuit 150 to use the pulse wave generating circuit as the voltage converting controller, when the input duty cycle is large, the duty cycle of the output and the duty cycle of the input can be maintained. The transfer curve is monotonically increasing, thus extending the range in which the voltage conversion controller is operational.

FIG. 10 is a schematic diagram of an embodiment of a pulse wave first edge delay circuit 830 in the pulse wave generating circuit 800 disclosed in the present invention. The pulse first edge delay circuit 830 includes an edge delay input 1010, an edge delay inverting circuit 1020, an edge delay switch 1030, an edge delay charging current 1040, an edge delay charging capacitor 1050, an edge buffer stage circuit 1060, and an edge delay output. 1070.

As shown in Fig. 10, the edge delay input terminal 1010 is also the first edge of the pulse wave. The input of the delay circuit 830, and the edge delay output 1070 is also the output of the pulse first edge delay circuit 830. The edge delay inverting circuit 1020 has an input end and an output end. The input end of the edge delay inverting circuit 1020 is coupled to the edge delay input terminal 1010, and the signal of the output end of the edge delay inverting circuit 1020 and the signal of the input end thereof are mutually Inverted. The edge delay switch 1030 is an N-type field effect transistor or an NPN type bipolar junction transistor, but is not limited thereto. The edge of the edge delay switch 1030 is coupled between the edge delay charging terminal 1031 and the second reference voltage 885 of the pulse wave generating circuit 800, and the control terminal of the edge delay switch 1030 is coupled to the output terminal of the edge delay inverting circuit 1020. . The edge delay charging current 1040 is coupled to the edge delay charging terminal 1031. The edge delay charging capacitor 1050 is coupled between the second reference voltage 885 and the edge delay charging terminal 1031. The edge buffer stage circuit 1060 has an input end and an output end. The input end of the edge buffer stage circuit 1060 is coupled to the edge delay charging end point 1031, the output end of the edge buffer stage circuit 1060 is coupled to the edge delay output end 1070, and the edge buffer is coupled. The signal at the output of stage circuit 1060 is in phase with the signal at its input.

For the operation of the pulse wave first edge delay circuit 830, please refer to the description of the pulse wave negative edge delay circuit 700. The only difference is that the output of the pulse wave negative edge delay circuit 700 and the input are mutually inverted, and the pulse wave is first. The output of the edge delay circuit 830 is positively phased with each other. Those of ordinary skill in the art can refer to the description of pulse wave negative edge delay circuit 700 for direct and unambiguous understanding of the operation of pulse wave first edge delay circuit 830.

In another embodiment of the pulse first edge delay circuit 830, the edge delay charging current 1040 is a current source of adjustable current value for adjusting the delay time t3. In still another embodiment of the pulse first edge delay circuit 830, the edge delay charging capacitor 1050 is a capacitive element of adjustable capacitance value for adjusting the delay time t4. It is worth noting that the above The first embodiment of the pulse wave first edge delay circuit 830 is illustrative of the present invention and is not intended to limit the scope of the present invention. Those skilled in the art can implement the present invention in accordance with the spirit of the present invention. invention.

It is also worth noting that the foregoing pulse wave generating circuit 800 and the pulse wave first edge delay circuit 830, which are generally known in the art, can be complemented by a complementary circuit topology design method. The result of the phase. For example, the N-type field effect transistor is replaced by a P-type field effect transistor, and the NPN type bipolar junction transistor is replaced by a PNP type bipolar junction transistor, changing the current direction, and the first reference voltage 855 is The second reference voltage 885 is swapped and all associated signals are inverted. That is, in another embodiment of the pulse wave generating circuit 800, the first edge refers to the negative edge of the pulse signal, the second edge refers to the positive edge of the pulse signal, and the first open relationship is an N-type field effect. The transistor is either an NPN-type bipolar junction transistor, the second open relationship is an N-type field effect transistor or an NPN-type bipolar junction transistor, and the third open relationship is a P-type field effect transistor. Or a PNP type bipolar junction transistor. And the first reference voltage is less than the second reference voltage.

Further, in the pulse wave generating circuit of the embodiment, the duty cycle of the first monotonic output terminal is fixed by a fixed value from the duty cycle of the pulse wave input signal, and the certain value is determined by the delay time t3. With this pulse wave generating circuit and the conventional pulse wave generating circuit 150 using the pulse wave generating circuit as the voltage converting controller, the delay time t3 can be designed to limit the lower limit of the duty cycle of the pulse wave generating circuit 150 input, so that it never Will enter the interval A in Figure 3. That is, when the input duty cycle is small, the transfer curve of the output duty cycle and the input duty cycle can be maintained in a monotonous rise relationship, thus extending the range in which the voltage conversion controller is operable.

FIG. 11 is a schematic diagram of an embodiment of a latch circuit 890 in the pulse wave generating circuit 800 disclosed in the present invention. The latch circuit 890 includes an input terminal 1110, an output terminal 1120, a latch first inverter circuit 1130, and a latch second inverter circuit 1140. The input end of the latch first inverting circuit 1130 is coupled to the input end 1110, the output end of the latch first inverting circuit 1130 is coupled to the output end 1120, and the output of the latch first inverting circuit 1130 The signal of the terminal is opposite to the signal of its input. The input end of the latch second inverting circuit 1140 is coupled to the output end 1120, the output end of the latch second inverting circuit 1140 is coupled to the input end 1110, and the output of the latch second inverting circuit 1140 The signal of the terminal is opposite to the signal of its input. The output driving capability of the first inverter circuit 1110 of the latch is greater than the output driving capability of the second inverter circuit 1120 of the latch.

Further, when the signal of the input terminal 1110 is in a state of transition, since the output driving capability of the first inverter circuit 1110 of the latch is greater than the output driving capability of the second inverter circuit 1120 of the latch, the signal of the output 1120 is The latch first inverter circuit 1110 determines and is in anti-phase with the input terminal 1110. When the input terminal 1110 is floating, the latch second inverter circuit 1120 determines the signal of the input terminal 1110 by the signal of the previous output terminal 1120, and uses the latch first inverter circuit 1130 and the latch second. The positive feedback loop formed by the inverter circuit 1140 keeps the signal of the output terminal 1120 unchanged.

In another embodiment of the latch circuit 890, the latch circuit 890 includes a capacitor coupled to the input terminal and an inverter component, and the latch circuit 890 utilizes the inverter component The output terminal and the input terminal are mutually inverted, and when the input terminal is floating, the capacitance to the ground can keep the signal of the input terminal unchanged, so that the signal of the output terminal remains unchanged. This circuit topology is well known to those of ordinary skill in the art and will not be further described.

FIG. 12 is a schematic diagram of a pulse wave generating circuit 1200 according to a third embodiment of the present invention, which is used for a voltage converting circuit. The pulse wave generating circuit 1200 includes a high duty cycle processing circuit 1210 and a low duty cycle processing circuit 1220.

As shown in FIG. 12, the high duty cycle processing circuit 1210 has a first pulse input terminal 1211 and a first monotonic output terminal 1212. The high duty cycle processing circuit 1210 is the pulse wave generating circuit 800 shown in FIG. The first pulse input terminal 1211 corresponds to the first pulse input terminal 810 for receiving a pulse input signal. The pulse input signal has an input duty cycle. The first monotonic output 1212 corresponds to the first monotonic output 820. It can be seen from the related description of FIG. 8 that the duty cycle of the first monotonic output terminal 820 has an upper limit.

As shown in FIG. 12, the low duty cycle processing circuit 1220 has a second pulse input terminal 1221 and a second monotonic output terminal 1222. The low duty cycle processing circuit 1220 is the pulse wave generating circuit 500 shown in FIG. The second pulse input terminal 1221 corresponds to the pulse input terminal 510. The second monotonic output terminal 1222 corresponds to the monotonic output terminal for generating a pulse wave output signal for driving the power component of the voltage conversion circuit, and the pulse wave output signal has an output duty cycle. It can be seen from the related description of FIG. 5 that the low duty cycle processing circuit 1220 can solve the problem that the conventional pulse wave generating circuit does not monotonically increase the output duty cycle of the input duty cycle at a low duty cycle.

In summary, the pulse wave generating circuit 1200 uses the low duty cycle processing circuit 1220 to maintain the monotonically rising characteristic of the output duty cycle transition curve for the input duty cycle when the input duty cycle is low; and the input duty cycle is high. The high duty cycle processing circuit 1210 is used to limit the upper limit of the duty cycle of the first monotonic output terminal 820, thereby limiting the actual use interval of the low duty cycle processing circuit 1220 of the subsequent stage, so that the output duty cycle is higher. The duty cycle can still maintain the monotonous rise in characteristics described above.

Fig. 13 is a transfer graph of the output duty cycle of the pulse wave generating circuit 1200 of the third embodiment with respect to the input duty cycle. The transfer curve is the characteristic of the monotonous rise described above. In addition, in the embodiment of the present invention, since the design of the flip-flop is to receive the set signal and reset the signal at the same time, the output of the flip-flop is an inverted signal, so the upper limit of the output duty cycle is reset. When the pulse width is determined, and the high duty cycle in Fig. 13 is formed, the output duty cycle is constant. When the pulse wave generating circuit having the transfer curve shown in FIG. 13 is applied to the voltage converting circuit, the use range of the voltage converting circuit can be maximized, so that it is necessary to limit the use interval regardless of whether the transfer curve has a monotonous rising characteristic. .

It should be noted that the embodiments of the above three pulse wave generating circuits are illustrative of the present invention and are not intended to limit the scope of the present invention. Those skilled in the art may, depending on the actual needs of the application. The cost considerations at the time of design, the improved components introduced by the advanced technology, and the like, and the invention are embodied in accordance with the spirit of the present invention.

The effect of the invention is that the pulse wave generating circuit applied to the voltage converting circuit has the largest output curve for the input duty cycle of the input duty cycle by the high duty cycle processing circuit and the low duty cycle processing circuit. The interval of the monotonic rise characteristic increases the use interval of the voltage conversion circuit and the flexibility of the application.

Although the embodiments of the present invention are disclosed above, it is not intended to limit the present invention, and those skilled in the art, regardless of the spirit and scope of the present invention, the shapes, structures, and features described in the scope of the present application. And the number of modifications may be made, and the scope of patent protection of the present invention shall be determined by the scope of the patent application attached to the specification.

1200‧‧‧ pulse wave generating circuit

1210‧‧‧High duty cycle processing circuit

1211‧‧‧first pulse input

1212‧‧‧ first monotonic output

1220‧‧‧Low duty cycle processing circuit

1221‧‧‧second pulse input

1222‧‧‧Second monotonic output

Claims (14)

A pulse wave generating circuit is used for a voltage converting circuit, the pulse wave generating circuit includes: a first pulse wave input end for receiving a pulse wave input signal, the pulse wave input signal having an input duty cycle, and The pulse input signal has a first edge and a second edge; a first monotonic output is configured to output a first pulse output signal, the first pulse output signal having a first output duty cycle; The pulse first edge delay circuit has an input end and an output end, and the input end of the pulse first edge delay circuit is coupled to the first pulse input end, and the output end of the pulse first edge delay circuit Outputting a pulse input delay signal, the pulse input delay signal is in phase with the pulse input signal, and a delay time of the first edge between the pulse input signal and the pulse input delay signal is greater than the second a delay time of the edge; a first inverting circuit having an input end and an output end, the input end of the first inverting circuit being coupled to the output end of the pulse wave positive edge delay circuit, and the first inverting Electricity The signal of the output end is opposite to the signal of the input end; a second inverting circuit has an input end and an output end, and the input end of the second inverting circuit is coupled to the first pulse input end And the signal of the output end of the second inverting circuit is opposite to the signal of the input end; a first switch, the channel of the first switch is coupled between a first reference voltage and a first end point And the control end of the first switch is coupled to the output end of the first inverter circuit; a second switch, the channel of the second switch is coupled between the first end point and a second end point, The control end of the second switch is coupled to the output end of the second inverter circuit; a third switch, the channel of the third switch is coupled between the second terminal and a second reference voltage, and the control end of the third switch is coupled to the output end of the second inverter circuit; a latch circuit having an input end and an output end, the input end of the latch circuit being coupled to the second end, the signal of the output end of the latch circuit and the input of the latch circuit The signal of the end is inverted and coupled to the first monotonic output, and when the second end is floating, the signal of the output of the latch circuit remains unchanged; wherein the first output duty cycle is The transfer curve of the input duty cycle is a monotonous rise relationship. The pulse wave generating circuit of claim 1, wherein the first edge is a negative edge of the pulse input signal, and the second edge is a positive edge of the pulse input signal, the first open relationship is a The N-type field effect transistor is an NPN type bipolar junction transistor, and the second opening relationship is an N-type field effect transistor or an NPN type bipolar junction transistor, and the third open relationship is one. P-type field effect transistor, or a PNP type bipolar junction transistor. The pulse wave generating circuit of claim 1, wherein the first edge is a positive edge of the pulse input signal, and the second edge is a negative edge of the pulse input signal, the first open relationship is a The P-type field effect transistor is either a PNP type bipolar junction transistor, and the second open relationship is a P-type field effect transistor or a PNP type bipolar junction transistor, and the third open relationship is one. N-type field effect transistor, or an NPN type bipolar junction transistor. The pulse wave generating circuit of claim 3, further comprising: a first pulse wave edge delay circuit having a first input end and a first output end, wherein the first input end is coupled to the a first monotonic output, the signal of the first output and the signal of the first input are mutually inverted, and the negative edge of the signal of the first input and the first output The delay time between the positive edges of the signals is greater than the delay time between the positive edge of the signal of the first input terminal and the negative edge of the signal of the first output terminal; a second pulse wave edge delay circuit having a a second input end coupled to the second output end, the second input end is coupled to the first output end, the signal of the second output end is opposite to the signal of the second input end, and the second The delay time between the negative edge of the signal of the input terminal and the positive edge of the signal of the second output terminal is greater than the delay time between the positive edge of the signal of the second input terminal and the negative edge of the signal of the second output terminal a first logic circuit having two input terminals and an output terminal, wherein the two input ends of the first logic circuit are respectively coupled to the first monotonic output terminal and the first output terminal, and the output end of the first logic circuit For generating a reset signal, when the two input ends of the first logic circuit are simultaneously inverted signals, the output end of the first logic circuit outputs a positive phase signal, and when the two input ends of the first logic circuit are different When the time is an inverted signal, the first logic circuit And outputting an inverting signal; and a second logic circuit having two input ends and an output end, wherein the two input ends of the second logic circuit are respectively coupled to the first output end and the second output end, the first The output end of the second logic circuit is configured to generate a set signal. When the two input ends of the second logic circuit are simultaneously inverted signals, the output end of the second logic circuit outputs a positive phase signal; and a flip-flop, The output of the flip-flop is coupled to a second monotonic output for generating a second pulse output signal, the second pulse output signal having a second output duty cycle, the second pulse The positive edge of the output signal is determined by the setting signal, and the negative edge of the second pulse output signal is determined by the reset signal; wherein the transfer curve of the second output duty cycle and the input duty cycle is monotonous The relationship between the rise. The pulse wave generating circuit of claim 4, wherein the first pulse negative edge delay circuit and the second pulse negative edge delay circuit further comprise: a first negative edge delay inverting circuit having one An input end and an output end, the input end of the first negative-edge delay inverting circuit is coupled to the first input end or the second input end, and the signal of the output end of the first negative-edge delay inverting circuit is The signals at the input end are mutually inverted; a negative-edge delay switch is an N-type field effect transistor or an NPN-type bipolar junction transistor, and the channel of the negative-edge delay switch is coupled to a negative-edge delay. Between the charging terminal and the second reference voltage, and the control terminal of the negative-edge delay switch is coupled to the output of the negative-edge delay inverting circuit; a negative-edge delay charging current coupled to the negative-edge delay charging An end point; a negative edge delay charging capacitor coupled between the second reference voltage and the negative edge delay charging terminal; and a second negative edge delay inverting circuit having an input end and an output end, An input end of the second negative-edge delay inverting circuit is coupled to the negative edge a late charging end, an output end of the second negative-edge delay inverting circuit is coupled to the first output end or the second output end, and the signal of the output end of the second negative-edge delay inverting circuit and the input end thereof The signals are inverted from each other. The pulse wave generating circuit of claim 5, wherein the negative edge delay charging current is a current source of adjustable current value for adjusting a negative edge of the signal of the first input end and the first output The delay time between the positive edges of the signals of the terminals, or the delay time between the negative edges of the signals of the second input and the positive edges of the signals of the second output. The pulse wave generating circuit of claim 5, wherein the negative edge delay charging capacitor is one a capacitive component of the adjustable capacitance value for adjusting a delay time between a negative edge of the signal of the first input terminal and a positive edge of the signal of the first output terminal, or a negative edge of the signal of the second input terminal The delay time between the positive edges of the signals at the second output. The pulse wave generating circuit of claim 4, wherein the first logic circuit and the second logic circuit are respectively a reverse OR gate logic circuit. The pulse wave generating circuit of claim 3, wherein the pulse first edge delay circuit further comprises: an edge delay inverting circuit having an input end and an output end, the edge delay inverting circuit The input end is the input end of the first edge delay circuit of the pulse wave, and the signal of the output end of the edge delay inverting circuit is opposite to the signal of the input end thereof; an edge delay switch, the channel of the edge delay switch The edge of the edge delay switch is coupled to the output end of the edge delay inverting circuit; an edge delay charging current coupled to the edge is coupled between the edge of the edge delay switch and the second reference voltage a delay charging terminal; an edge delay charging capacitor coupled between the second reference voltage and the edge delay charging terminal; and an edge buffer stage circuit having an input end and an output end, the edge buffer stage circuit The input end is coupled to the edge delay charging end point, and the output end of the edge buffer stage circuit is an output end of the first edge delay circuit of the pulse wave, and the edge buffer stage circuit is output The signal input terminal and the signal terminal of the positive phase of each other. The pulse wave generating circuit of claim 3 or 4, wherein the latch circuit further comprises: a latch first inverting circuit having an input end and an output end, the latch first An input end of the inverter circuit is coupled to the second end point, and an output end of the first inverter circuit of the latch is coupled to the first monotonic output end, and an output end of the first inverter circuit of the latch The signal is in reverse phase with the signal of the input end thereof; and a second inverter circuit of the latch has an input end and an output end, and the input end of the second inverter circuit of the latch is coupled to the first end a monotonic output end, the output end of the second inverter circuit of the latch is coupled to the second end point, and the signal of the output end of the second inverter circuit of the latch is opposite to the signal of the input end thereof; The output driving capability of the first inverter circuit of the latch is greater than the output driving capability of the second inverter circuit of the latch. A pulse wave generating circuit is used for a voltage converting circuit. The pulse wave generating circuit includes: a pulse wave input end for receiving a pulse input signal, the pulse wave input signal having an input duty cycle; a first pulse The wave negative edge delay circuit has a first input end and a first output end, the first input end is coupled to the pulse wave input end, and the signal of the first output end and the signal of the first input end are mutually Inverting, and a delay time between a negative edge of the signal of the first input end and a positive edge of the signal of the first output end is greater than a signal of a positive edge of the first input end and a signal of the first output end a delay time between the negative edges; a second pulse negative edge delay circuit having a second input end and a second output end coupled to the first output end, the second output The signal of the terminal is opposite to the signal of the second input end, and the delay time between the negative edge of the signal of the second input end and the positive edge of the signal of the second output end is greater than the second input end. Between the positive edge of the signal and the negative edge of the signal at the second output delay; a first logic circuit having two input ends and an output end, wherein the two input ends of the first logic circuit are respectively coupled to the pulse wave input end and the first output end, and the output end of the first logic circuit is used To generate a reset signal, when the two input ends of the first logic circuit are simultaneously inverted signals, the output end of the first logic circuit outputs a positive phase signal, and when the two input ends of the first logic circuit are different, When the signal is inverted, the output of the first logic circuit outputs an inverted signal; a second logic circuit has two input ends and an output end, and the two input ends of the second logic circuit are respectively coupled to the first output And the second output end, the output end of the second logic circuit is configured to generate a set signal, and when the two input ends of the second logic circuit are simultaneously inverted signals, the output end of the second logic circuit outputs a positive phase signal, and when the two input ends of the second logic circuit are different, the output end of the second logic circuit outputs an inverted signal; and a flip-flop, the output end of which is coupled to the Monotonic output System for generating an output pulse signal, the pulse output signal having an output duty cycle and cause a positive output signal of the pulse signal determines the setting, the reason for the negative output pulse signal of the reset signal is determined. The pulse wave generating circuit of claim 11, wherein the first pulse negative edge delay circuit and the second pulse negative edge delay circuit further comprise: a first negative edge delay inverting circuit having one An input end and an output end, the input end of the first negative-edge delay inverting circuit is coupled to the first input end or the second input end, and the signal of the output end of the first negative-edge delay inverting circuit is The signals at the input end are mutually inverted; a negative-edge delay switch is an N-type field effect transistor or an NPN-type bipolar junction transistor, and the channel of the negative-edge delay switch is coupled to a negative-edge delay. Charging endpoint and a reference Between the voltages, and the control terminal of the negative-edge delay switch is coupled to the output of the negative-edge delay inverter circuit; a negative-edge delay charging current coupled to the negative-edge delay charging terminal; a negative-edge delay charging a capacitor coupled between the reference voltage and the negative edge delay charging terminal; and a second negative edge delay inverting circuit having an input end and an output end, the second negative edge delay inverting circuit input The end is coupled to the negative-edge delay charging terminal, the output end of the second negative-edge delay inverting circuit is coupled to the first output end or the second output end, and the second negative-edge delay inverting circuit is The signal at the output is inverted from the signal at the input. The pulse wave generating circuit of claim 12, wherein the negative edge delay charging current is a current source of adjustable current value for adjusting a negative edge of the signal of the first input end and the first output The delay time between the positive edges of the signals of the terminals, or the delay time between the negative edges of the signals of the second input and the positive edges of the signals of the second output. The pulse wave generating circuit of claim 12, wherein the negative edge delay charging capacitor is a capacitor element of a adjustable capacitance value for adjusting a negative edge of the signal of the first input terminal and the first output The delay time between the positive edges of the signals of the terminals, or the delay time between the negative edges of the signals of the second input and the positive edges of the signals of the second output.