TWI501242B - Erase method for flash - Google Patents

Description

Flash memory erase method

The present invention relates to a method of erasing a flash memory, and more particularly to a method of erasing a flash memory capable of quickly determining a blank segment.

When storing data, the flash memory writes specific data through a program and erase mechanism. In general, write and erase algorithms that are executed according to different command sheets can cause different problems, such as over erase. Taking a general erase program as an example, it mainly includes pre-program, erase and post-program steps to ensure that each memory cell is in a logical level after being erased. The status of "1". When the memory repeatedly performs the erase and program, as the number of writes increases, the execution time of the erase program will gradually increase, which is used to repair the programming steps in the entire erase program after over-erasing. The execution time is the longest. When an emergency occurs, such as when a shutdown condition suddenly occurs, it is possible that the post-programming step is interrupted, and the post-programming step of the flash memory is not completely performed. Therefore, it takes more time to verify the flash memory to find a blank sector to avoid any over-erased memory cells in the segment, causing read misjudgment.

The invention provides an erasing method suitable for a flash memory body. The first memory cell of the flash memory is preprogrammed, wherein the first memory cell is disposed in a memory array composed of a plurality of row lines and a plurality of column lines. Erasing the programmed first memory cell. The first memory cell that has been erased is programmed to repair the first memory cell that has been over-erased. After programming the erased first memory cell, programming a plurality of second memory cells, wherein the second memory cell is disposed in a first specific row line of one of the memory arrays, wherein the first specific row line is arranged to correspond to After the last line of one of the last valid row addresses. The memory array further includes a plurality of third memory cells disposed on a second particular row line of one of the memory arrays, wherein the second particular row line is arranged after the last row line and adjacent to the first particular row line.

100‧‧‧flash memory

110‧‧‧ Controller

120‧‧‧Sense Amplifier

130‧‧‧ address decoding circuit

200‧‧‧ memory array

210, 220, 230‧‧‧ memory cells

C0-Cm, CF1, CF2‧‧‧ lines

R0-Rn‧‧‧ line

S310-S340, S410-S484, S510-S584, S610-S684, S710-S750‧‧

1 is a view showing a flash memory according to an embodiment of the present invention; FIG. 2 is a view showing a memory array of FIG. 1; and FIG. 3 is a view showing an erase according to an embodiment of the present invention. The method is applicable to the flash memory of FIG. 1; FIG. 4A is a flowchart of the pre-programming procedure of the flash memory according to an embodiment of the invention; FIG. 4B is a diagram of another embodiment of the present invention. A flowchart of a pre-programming program for a flash memory; FIG. 5A is a flowchart of a flash memory erasing program according to an embodiment of the invention; FIG. 5B is a diagram of another embodiment of the present invention The flowchart of the flash memory erasing program; FIG. 6A is a flash memory according to an embodiment of the invention. FIG. 6B is a flowchart of a program after flash memory programming according to another embodiment of the present invention; FIG. 7 is a diagram of a flash memory according to an embodiment of the invention; A flowchart of a program; FIG. 8A is a flowchart of a marking procedure of a flash memory according to another embodiment of the present invention; and FIG. 8B is a flash memory according to another embodiment of the present invention. A flowchart of the marking program.

The above and other objects, features and advantages of the present invention will become more <RTIgt; The flash memory 100 described in the embodiment. The flash memory 100 includes a controller 110, a sense amplifier 120, an address decoding circuit 130, and a memory array 200. Figure 2 is a schematic diagram showing the memory array 200 of Figure 1. The memory array 200 includes a plurality of memory cells 210, 220, and 230, wherein the memory cells 210, 220, and 230 are disposed by a plurality of column rows R0-Rn and a plurality of columns C0-Cm, CF1, and CF2. On the array of compositions. In this embodiment, the column lines R0-Rn are word lines, and the row lines C0-Cm, CF1, and CF2 are bit lines. Further, in the memory array 200, each of the column lines R0-Rn represents a valid column address, and each of the row lines C0-Cm represents a valid row address. In other words, the controller (for example, the controller 110 of FIG. 1) stores the memory cell 210 through the column line R0-Rn and the row lines C0-Cm via the address decoding circuit 130. The data stored in the memory cell 210 is provided to other devices or the data stored in the memory cell 210 is updated. Compared with the conventional memory array, the row lines CF1 and CF2 of the memory array 200 are additional bit lines or extra lines, wherein the memory cell 220 coupled to the row line CF1 and the memory cell coupled to the row line CF2 The 230 series is used as a flag memory cell to indicate the state of the memory cell 210 on the corresponding column line. For example, the memory cells 220 and 230 disposed on the column line R0 are used to indicate the state of the plurality of memory cells 210 on the column line R0, and the memory cells 220 and 230 disposed on the column line Rn are used to indicate the column lines. The state of the plurality of memory cells 210 on Rn. Therefore, the controller can determine whether the segment erases the complete segment, whether the segment stores valid data, and the like according to the logical levels of the memory cells 220 and 230 in each sector. It should be noted that the locations of memory cells 220 and 230 are merely examples and are not intended to limit the invention. In one embodiment, memory cell 230 is disposed on row line F1 and memory cell 220 is disposed on row line F2.

Fig. 3 is a view showing an erasing method according to an embodiment of the present invention, which is suitable for the flash memory of Fig. 1. Referring to FIGS. 1 and 3 simultaneously, first, in step S310, the controller 110 performs a pre-programming process on the memory array 200 to program all of the memory cells in the memory array 200 to a logic level "0". Next, in step S320, the controller 110 performs an erase process on the memory array 200 to erase all memory cells in the memory array 200 to a logic level "1". Next, in step S330, the controller 110 executes a post-programming process on the memory array 200 to perform repair on the over-erased memory cells. Next, in step S340, the controller 110 performs a marking process on a specific memory cell (for example, the memory cell 220 or 230 of FIG. 2) in the memory array 200 to record the result of the erase process. Preprogrammed, erased, postprogrammed, and tagged programs will be detailed Described in detail later.

4A is a flow chart of a pre-programming process for flash memory according to an embodiment of the invention. The purpose of executing the preprogrammed program is to have each of the memory cells in the memory array 200 have similar voltage levels prior to performing the erase process to avoid the need to perform multiple erase procedures to reduce the generation of the transition erase memory cells. Referring also to Figures 2 and 4A, in this embodiment, a sense amplifier of a flash memory (e.g., sense amplifier 120 of Figure 1) uses an additional read/write unit for additional memory. Cells 220 and 230 perform read and write operations. First, in step S410, the controller performs pre-program verification on the complex memory cells 210 in the byte or character group corresponding to the address Addr according to the address Addr (eg, Addr=0, ie, the start address). Verify). Next, in step S420, the controller determines whether the pre-program verification is successful, that is, whether each memory cell 210 corresponding to the address Addr is a logic level "0". If the result of the preprogrammed verification is a failure (eg, at least one of the memory cells 210 corresponding to the address Addr is a logic level "1"), the controller performs a preprogrammed write operation so as to correspond to the address Addr. The memory cell 210 is programmed to a logic level of "0" (step S440). Next, returning to step S410, the controller will perform pre-program verification on the memory cell 210 corresponding to the address Addr (step S410) until the controller determines that the pre-program verification is successful (step S420). Next, at step 450, the controller determines if the address Addr is greater than the last sector address Addr_last_Sector. If the address Addr has exceeded the last sector address Addr_last_Sector, the pre-programming process is completed. On the other hand, if the address Addr is not greater than the last sector address Addr_last_Sector, then step S430 is performed. In step S430, the controller increments the position value of the address Addr by one (for example, Addr=Addr+1, that is, points to the next address) to update the address Addr. Then the controller will judge Whether the updated address Addr is the last valid row address Cm (step S460). If the updated address Addr is not the last valid row address Cm, then return to step S410. Thus, the controller performs preprogrammed verification on the memory cell 210 corresponding to the updated address Addr and proceeds to the subsequent process. If the updated address Addr is the last valid row address Cm (ie, Addr=Cm), the controller adds the extra bit lines CF1 and CF2 (step S470) so that the address Addr and the corresponding address can be simultaneously The additional rows of CF1 and CF2 memory cells are verified. Then, in step S410, the controller remembers the memory cell 210 corresponding to the last valid row address Cm, the memory cell 220 corresponding to the extra row CF1 of the same column address, and the additional row CF2 corresponding to the same column address. Cell 230 performs pre-program verification. As previously described, if the result of the pre-program verification is a failure, a pre-program write operation is performed to associate the memory cell 210 corresponding to the address Addr, the memory cell 220 corresponding to the extra row CF1 of the address Addr, and the corresponding The memory cell 230 of the extra line CF2 of the address Addr is programmed to the logic level "0" (step S440), and the subsequent flow is performed.

4B is a flow chart of a pre-programming procedure for flash memory according to another embodiment of the present invention. Referring to FIG. 2 and FIG. 4B simultaneously, in this embodiment, the sense amplifier of the flash memory (for example, the sense amplifier 120 of FIG. 1) uses the original read/write unit to add additional Memory cells 220 and 230 perform read and write operations. First, in step S410, the controller performs pre-program verification on the complex memory cells 210 in the byte or character group corresponding to the address Addr according to the address Addr (eg, Addr=0, ie, the start address). Next, in step S420, the controller determines whether the pre-program verification is successful, for example, determines whether each of the memory cells 210 corresponding to the address Addr is a logic level "0". If the result of the pre-program verification is a failure (for example, at least one memory cell 210 corresponding to the address Addr is logic The level "1"), the controller will perform a pre-program write operation to program all of the memory cells 210 corresponding to the address Addr to a logic level "0" (step S440). Next, the process returns to step S410. Thus, the controller will re-execute the pre-program verification of the memory cell 210 corresponding to the address Addr until the controller determines that the pre-program verification is successful (step S420). Next, the controller determines whether the address Addr is the last valid row address Cm (step S460). If the address Addr is not the last valid row address Cm, then step S450 is performed. Next, at step 450, the controller determines if the address Addr has exceeded the last sector address Addr_last_Sector. If the address Addr has exceeded the last sector address Addr_last_Sector, the pre-programming process is completed. Conversely, if the address Addr does not exceed the last sector address Addr_last_Sector, the controller increments the position value of the address Addr by one (for example, Addr=Addr+1, that is, points to the next address) to update the address Addr. Thus, the controller performs pre-program verification on the memory cell 210 corresponding to the updated address Addr (step S410), and performs a subsequent process. In step S460, if the address Addr is the last valid row address Cm (ie, Addr=Rn+Cm), the controller will add an additional row CF1 corresponding to the same column address for the additional bit lines CF1 and CF2. The memory cell 220 performs pre-program verification with the memory cell 230 corresponding to the extra row CF2 of the same column address (step S480). Next, in step S482, the controller determines whether the pre-program verification is successful, for example, determines whether the memory cells 220 and 230 are logic level "0". If the result of the preprogrammed verification is a failure (eg, memory cell 220 or memory cell 230 is a logic level "1"), the controller performs a preprogrammed write operation to place the same column address corresponding to the extra address Addr. The memory cell 220 of the extra line CF1 and the memory cell 230 of the extra line CF2 are programmed to logic level "0" (step S484), and return to step S480. The controller will then perform preprogrammed verification on memory cells 220 and 230 again. (Step S480). Next, returning to step S482, until the controller determines that the pre-program verification is successful, then step S450 is performed, and the subsequent flow is performed.

FIG. 5A is a flow chart of a flash memory erase program according to an embodiment of the invention. Referring also to Figures 2 and 5A, in this embodiment, the sense amplifier of the flash memory (e.g., sense amplifier 120 of Figure 1) uses an additional read/write unit for additional memory. Cells 220 and 230 perform read and write operations. First, in step S510, the controller erases the memory cells 210, 220, and 230 in a sector. Next, in step S520, the controller performs erasure verification on the plurality of memory cells 210 in the byte or the character group corresponding to the address Addr according to the address Addr (for example, Addr=0, that is, the start address). . Next, in step S530, the controller determines whether the erase verification is successful, for example, determines whether each of the memory cells 210 corresponding to the address Addr is a logic level "1". If the result of the erase verification is a failure (for example, at least one memory cell 210 corresponding to the address Addr is a logic level "0"), then returning to step S510 to re-erase the memory cells 210, 220 in the segment. With 230. On the other hand, if the result of the erase verification is successful, the controller determines whether the address Addr is greater than the last sector address Addr_last_Sector (step S540). If the address Addr has exceeded the last sector address Addr_last_Sector, the erase procedure is completed. On the other hand, if the address Addr is less than or equal to the last sector address Addr_last_Sector, the controller increments the position value of the address Addr by one (for example, Addr=Addr+1, that is, points to the next address) (step S550) to update. Address Addr. Next, in step S560, the controller determines whether the updated address Addr is the last valid row address Cm. If the updated address Addr is not the last valid row address Cm, then return to step S520. Then, the controller performs erasure verification on the memory cell 210 corresponding to the updated address Addr, and performs subsequent flow. Cheng. If the updated address Addr is the last valid row address Cm (ie, Addr=Cm), the controller adds the additional bit lines CF1 and CF2 (step S570), so that the address Addr and the corresponding address can be simultaneously The extra cells CF1 and CF2 on the same column address are verified. Thus, the controller performs a wipe on the memory cell 210 corresponding to the last valid row address Cm, the memory cell 220 corresponding to the extra row CF1 of the same column address, and the memory cell 230 corresponding to the extra row CF2 of the same column address. In addition to the verification (step S520) and the result of the authentication is confirmed (step S530). As previously described, if the result of the erase verification is a failure, for example, the memory cell 210 corresponding to the last valid row address Cm on the address Addr, the memory cell 220 corresponding to the extra row CF1 of the same column address, and the extra row If any of the memory cells 230 of CF2 is logic level "0", the process returns to step S510 to erase the memory cells 210, 220, and 230 in the segment.

FIG. 5B is a flow chart of a flash memory erasing program according to another embodiment of the present invention. Referring to FIG. 2 and FIG. 5B simultaneously, in this embodiment, the sense amplifier of the flash memory (for example, the sense amplifier 120 of FIG. 1) uses the original read/write unit to add additional Memory cells 220 and 230 perform read and write operations. First, in step S510, the controller erases the memory cells 210, 220, and 230 in a sector. Next, in step S520, the controller performs erasure verification on the plurality of memory cells 210 in the byte or the character group corresponding to the address Addr according to the address Addr (for example, Addr=0, that is, the start address). . Next, in step S530, the controller determines whether the erase verification is successful, for example, determines whether each of the memory cells 210 corresponding to the address Addr is a logic level "1". If the result of the erase verification is a failure (for example, at least one memory cell 210 corresponding to the address Addr is a logic level "0"), then returning to step S510 to re-erase the segment. Memory cells 210, 220 and 230. On the other hand, if the result of the erase verification is successful, the controller determines whether the address Addr is the last valid row address Cm (step S560). If the address Addr is not the last valid row address Cm, the controller determines whether the address Addr is greater than the last sector address Addr_last_Sector (step S540). If the address Addr has exceeded the last sector address Addr_last_Sector, the erase procedure is completed. On the other hand, if the address Addr is less than or equal to the last sector address Addr_last_Sector, the controller increments the position value of the address Addr by one (for example, Addr=Addr+1, that is, points to the next address) (step S550) to update. The address is Addr and returns to step S520. Then, the controller performs erasure verification on the memory cell 210 corresponding to the updated address Addr, and performs subsequent processes. In step S560, if the address Addr is the last valid row address Cm (ie, Addr=Cm), the controller will store the memory corresponding to the extra row CF1 on the same column address for the extra bit lines CF1 and CF2. The cell 220 and the memory cell 230 of the extra line CF2 perform erasure verification (step S580). Next, in step S582, the controller determines whether the erase verification is successful, for example, determines whether the memory cells 220 and 230 are logic level "1". If the result of the erase verification is a failure (for example, the memory cell 220 or the memory cell 230 is a logic level "0"), the controller will erase the memory cells 210, 220, and 230 in the segment again (step S584). ). Next, the controller re-executes the erase verification on the memory cells 220 and 230 (step S580). Next, the erase verification is repeatedly performed (step S582) and the erase is re-executed (step S584) until the controller determines that the erase verification is successful, and then proceeds to step S540, and the subsequent flow is performed.

6A is a flow chart of a program after flash memory programming according to an embodiment of the invention. The purpose of the post-execution programming program is to repair the over-erased memory cells. In general, after the erase process, the flash memory The threshold voltage of the memory cell may decrease. When the threshold voltage is too low (for example, less than 0), the memory cell will be over-erased, and the leakage current will cause the controller to fail to correctly identify the memory cell and other memory cells stored in the bank. data. Referring also to Figures 2 and 6A, in this embodiment, the sense amplifier of the flash memory (e.g., sense amplifier 120 of Figure 1) uses an additional read/write unit for additional memory. Cells 220 and 230 perform read and write operations. First, in step S610, according to the row address Addr_Col (for example, Addr_Col=0, that is, the start address), the controller performs excessive execution on the plurality of memory cells 210 corresponding to the row address Addr_Col in units of a row line (column). Wipe the verification. Next, in step S620, the controller determines whether the over-erase verification is successful. For example, if it is determined that all the memory cells 210 corresponding to the row address Addr_Col are not selected, it is verified whether there is leakage current on the line. If the result of the over-erase verification is a failure (for example, at least one of the memory cells 210 corresponding to the row address Addr_Col has a leakage current), then all the memory cells 210 corresponding to the row address Addr_Col are executed in units of row lines. A program write operation (or soft-program) is performed (step S640) to adjust the threshold voltage value of the memory cell 210. Next, returning to step S610, the controller performs over-erase verification on the complex memory cell 210 corresponding to the row address Addr_Col (step S620) until the over-erase verification is successful. When the over-erase verification is successful, the controller determines whether the row address Addr_Col has exceeded the last valid row address Cm (step S650). If the row address Addr_Col has exceeded the last valid row address Cm, the programming procedure is completed. Conversely, if the row address Addr_Col is less than or equal to the last valid row address Cm, the controller increments the position value of the row address Addr_Col by one (for example, Addr_Col=Addr_Col+1, which points to the next row address) to update. The row address Addr_Col (step S630). Then, control The controller determines whether the updated row address Addr_Col is the last valid row address Cm (step S660). If the updated row address Addr_Col is not the last valid row address Cm, then return to step S610. Then, the controller performs over-erase verification on the memory cell 210 corresponding to the updated row address Addr_Col, and performs a subsequent process. If the updated row address Addr_Col is the last valid row address Cm (ie, Addr_Col=Cm), the controller adds the extra bit lines CF1 and CF2 (step S670), so that the last valid row address can be simultaneously simultaneously. Addr_Col and additional lines CF1 and CF2 memory cells are verified. Then, in step S610, the controller performs over-erase verification on the memory cell 210 corresponding to the last valid row address Cm, the memory cell 220 of the extra row CF1, and the memory cell 230 of the extra row CF2. As previously described, if the result of the over-erase verification is a failure, the memory cell 210 corresponding to the row address Addr_Col is adjusted to correspond to the threshold voltage value of the memory cell 220 of the extra row CF1 and the memory cell 230 of the extra row CF2, And follow-up process.

6B is a flow chart of a program after flash memory programming according to another embodiment of the present invention. Referring to FIG. 2 and FIG. 6B simultaneously, in this embodiment, the sense amplifier of the flash memory (for example, the sense amplifier 120 of FIG. 1) uses the original read/write unit to add additional Memory cells 220 and 230 perform read and write operations. First, in step S610, according to the row address Addr_Col (for example, Addr_Col=0, that is, the start address), the controller performs excessive execution on the plurality of memory cells 210 corresponding to the row address Addr_Col in units of a row line (column). Wipe the verification. Next, in step S620, the controller determines whether the over-erase verification is successful, for example, determines whether all of the memory cells 210 corresponding to the row address Addr_Col have leakage current. If the result of the over-erase verification is a failure (for example, at least one of the memory cells 210 corresponding to the row address Addr_Col has a leakage current), then A post-program write operation (or soft-program) is performed on all of the memory cells 210 corresponding to the row address Addr_Col in units of row lines (step S640) to adjust the threshold voltage value of the memory cell 210. Next, returning to step S610, the controller performs over-erase verification on the complex memory cell 210 corresponding to the row address Addr_Col (step S620) until the over-erase verification is successful. When the over-erase verification is successful, the controller increments the position value of the row address Addr_Col by one (for example, Addr_Col=Addr_Col+1, that is, points to the next row address) to update the row address Addr_Col (step S630). Next, at step 650, the controller determines if the row address Addr_Col has exceeded the last valid row address Cm. If the row address Addr_Col is less than or equal to the last valid row address Cm, then return to step S610. Then, the controller performs over-erase verification on the memory cell 210 corresponding to the updated row Addr_Col (step S610), and performs a subsequent process. In step S650, if the row address Addr_Col has exceeded the last valid row address Cm (ie, Addr_Col=Cm), the controller pairs the memory cells 220 corresponding to the extra row CF1 for the additional bit lines CF1 and CF2 and The memory cell 230 corresponding to the extra line CF2 performs over-erase verification (step S680). Next, in step S682, the controller determines whether the over-erase verification is successful, that is, whether the memory cells 220 and 230 have leakage current. If the result of the over-erase verification is a failure (for example, the memory cell 220 or the memory cell 230 has a leakage current), all the memory cells 220 corresponding to the extra row CF1 and all the memories corresponding to the extra row CF2 are stored in units of row lines. The cell 230 performs a post-program write operation (S684) to adjust the threshold voltage value of the memory cell 220 corresponding to the extra row CF1 and the memory cell 230 corresponding to the extra row CF2, and returns to step S680. Then, the controller re-executes the over-erasing verification on the memory cells 220 and 230 (step S680) and performs subsequent procedures until the controller determines in step S682. If the erasure verification is successful, then step S650 is performed and the subsequent process is performed.

Figure 7 is a flow chart of a marking procedure of a flash memory according to an embodiment of the invention. Referring to Figures 2 and 7, in this embodiment, the memory cell 230 is used to indicate whether the memory cell on the corresponding row line has completely completed the erase process. It is to be noted that the result of using the memory cell 230 to record the erase program is merely an example and is not intended to limit the invention. In an embodiment, memory cell 220 can be used to record the results of the erase process. In another embodiment, a plurality of memory cells 230 or memory cells 220 may be used to record the results of the erase process. First, in step S710, according to the column address Addr_Row (for example, Addr_Row = R0, that is, the column start address), the controller programs the memory cell 230 corresponding to the column address Addr_Row to a logic level "0". Next, in step S720, the controller performs program verification on the memory cell 230. Next, in step S730, the controller determines whether the program verification is successful, for example, whether the memory cell 230 is a logic level "0". If the result of the program verification is a failure (for example, the memory cell 230 is a logic level "1"), then return to step S710 to reprogram the memory cell 230. On the other hand, if the result of the program verification is successful, the controller determines whether the column address Addr_Row has exceeded the last valid column address Rn (step S740). If the column address Addr_Row has exceeded the last valid column address Rn, the marking procedure is completed. On the other hand, if the column address Addr_Row is less than or equal to the last valid column address Rn, the controller increments the position value of the column address Addr_Row by one (for example, Addr_Row=Addr_Row+1, that is, points to the next column address) (step S750) ), and returns to step S710. Next, the controller will program the memory cell 230 corresponding to the updated column address Addr_Row to a logic level "0" and perform subsequent procedures.

8A is a flash memory according to another embodiment of the present invention. Flow chart of the body marking program. Referring to FIG. 2 and FIG. 8A simultaneously, in this embodiment, the memory cell 220 is used to indicate whether the memory cell on the corresponding column line has performed a programming procedure. In addition, a sense amplifier of a flash memory (such as sense amplifier 120 of FIG. 1) uses an additional read/write unit to perform read and write operations on additional memory cells 220. It is to be noted that the results of using the memory cell 220 to record programming procedures are merely examples and are not intended to limit the invention. In one embodiment, memory cell 230 can be used to record the results of the programming process, while memory cell 220 is used to record whether the segment completes the marking of the erase process. In another embodiment, a plurality of memory cells 230 or memory cells 220 can be used to record whether the programming process has been performed and the result of the erase process is completed. In this embodiment, the controller programs the memory cells 210 in the selected segment in units of bytes or groups of characters in accordance with programming instructions. First, in step S810, when the data to be programmed is the last byte data, the controller programs the last byte data to the corresponding memory cell 210 according to the address Addr, and places the bits in the same column. The memory cell 220 is programmed to a logic level of "0". Next, in step S820, the controller performs program verification on the memory cells 210 and 220 programmed by the corresponding address Addr. Next, in step S830, the controller determines whether the program verification is successful, for example, whether the memory cell 210 conforms to the programming data and whether the memory cell 220 is a logic level "0". If the result of the program verification is a failure (for example, the memory cell 220 is a logic level "1" or the logic cell 210 has an incorrect logic level), then the process returns to step S810 to reprogram the memory cells 210 and 220. Conversely, if the result of the program verification is successful, the marking process is completed.

8B is a flow chart of a marking procedure of a flash memory according to another embodiment of the present invention. Referring to Figures 2 and 8B at the same time, implementation here In the example, the memory cell 220 is used to indicate whether the memory cell on the corresponding column line has performed a programming procedure. In addition, a sense amplifier of a flash memory (such as sense amplifier 120 of FIG. 1) uses a conventional read/write unit to perform read and write operations on additional memory cells 220 and 230. It is to be noted that the results of using the memory cell 220 to record programming procedures are merely examples and are not intended to limit the invention. In one embodiment, memory cell 230 can be used to record whether a program has been executed and the result of the flag used by memory cell 220 to record whether the segment has completely completed the erase process. In another embodiment, a plurality of memory cells 230 or memory cells 220 can be used to record the results of the programming process. In this embodiment, the controller programs the memory cells 210 in the selected segment in units of bytes or groups of characters in accordance with programming instructions. In this embodiment, the controller programs the memory cells 210 in the selected segment in units of bytes or groups of characters in accordance with programming instructions. First, in step S840, when the data to be programmed is the last byte data, the controller programs the last byte data to the corresponding memory cell 210 according to the address Addr. Next, in step S850, the controller performs program verification on the programmed memory cell 210. Next, in step S860, the controller determines whether the program verification is successful. If the result of the program verification is a failure (for example, the logic level of the memory cell 210 is incorrect), then return to step S840 to reprogram the memory cell 210. On the other hand, if the result of the program verification of the memory cell 210 is successful, the memory cell 220 in the same column is programmed to the logic level "0" (step S870). Next, in step S880, the controller performs program verification on the programmed memory cell 220. Next, in step S890, the controller determines whether the program verification is successful, for example, whether the memory cell 220 is a logic level "0". If the result of the program verification of the memory cell 220 is a failure (for example, the memory cell 220 is a logic level "1"), then it is returned. Step S870, to reprogram the memory cell 220. Conversely, if the result of the program verification is successful, the marking process is completed.

In general, before programming the memory array, the controller must first confirm that the selected segment is a blank segment in order to program the data to the blank segment. In general, when an interrupt occurs during the erasure of a conventional flash memory, the erase program is not completely executed. Therefore, in conventional flash memory, the controller sometimes needs to perform erase verification on all the memory cells in the selected segment and perform over-erase verification to confirm that there is no excessive in the selected segment. The erased memory cell exists, and it takes more time to complete the erase verification of the entire segment of the memory cell and the over-erase verification. In addition, for the flash memory disposed in the portable electronic device, in order to speed up the execution of the erase verification and the over-erase verification, the read rate is often increased to increase the verification rate, but the power consumption is also increased. In the embodiment of the present invention, by reading the state of the memory cells (for example, the memory cells 220 and 230 of FIG. 2) disposed on the extra row lines (for example, the row lines CF1 and CF2 of FIG. 2), the controller may Confirm that the selected segment has completely executed the erase program and further determines whether the selected segment is a blank segment, without performing erase verification and over-erase verification on the selected segment. Therefore, it is possible to speed up the judgment of whether or not it is a blank section and reduce the power consumption. For example, in one embodiment, memory cell 220 and memory cell 230 are used to indicate whether the memory cell on the corresponding row line has completely completed the erase process. If all of the memory cells 230 in the selected segment are logic level "0" and all memory cells 220 are logic level "1", the controller may determine that the segment has been completely erased, as shown in Table 1 below. display. The controller then programs the data into the segment. After completing the data programming, the controller can use the previously described marking program to The memory cells 220 of this segment are programmed. In this embodiment, memory cell 220 is used to indicate whether the memory cells on the corresponding row lines have been programmed. For example, during the execution of a page of data programming, after the last byte is programmed, the controller can program the memory cell 220 on the same column line to a logic level of "0". Therefore, if some of the memory cells 220 in the selected segment are logic level "0" and all memory cells 230 are logic level "0", the controller can determine that the segment has been used, not a blank segment. . In addition, if a portion of the memory cells 230 in the selected segment are logic level "1", the controller can determine that the segment is not completely erased. In particular, all memory cells 220 are logic level "1" and all memory cells 230 are also logic level "1", which indicates that the sector has been erased and interrupted, and there may be excessive erasure. Memory cell. Therefore, the memory cells of the segment can be erased according to the method of FIG. 3 to avoid the existence of excessively erased memory cells and cause misjudgment of data integrity.

As described previously, by using the memory cells on the extra line to record the state of use of the memory cells on the corresponding column lines in the memory array, the controller can quickly determine if the selected segment is blank. Furthermore, by marking the memory cells of the entire row, the programming and erasing times of the flag memory cells can be effectively dispersed, and the number of cycles equal to the data memory cells can be achieved. In addition, the order and number of memory cells 220 and 230 can be determined according to practical applications.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and it is intended that the invention may be modified and modified without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

S310-S340‧‧‧Steps

Claims (12)

An erasing method, applicable to a flash memory, comprising: pre-programming a plurality of first memory cells of the flash memory, wherein the first memory cell is disposed by a plurality of row lines and a plurality of column lines a memory array; erasing the first memory cells that have been preprogrammed; and programming the first memory cells that have been erased to repair the first memory cells that have been over erased; and post programming After erasing the first memory cells, programming a plurality of second memory cells, wherein the second memory cells are disposed in a first specific row of the memory array, and the first specific row line is arranged Corresponding to one of the last valid row addresses after the last row line; wherein the memory array further comprises a plurality of third memory cells disposed in a second specific row line of the memory array, wherein the second specific row line is Arranged after the last row line and adjacent to the first specific row line. The erasing method of claim 1, wherein the step of pre-programming the first memory cells of the flash memory further comprises: corresponding to the first address according to a first address The first memory cells perform a pre-programmed verification to determine whether the first memory cells corresponding to the first address are low logic levels; and the first memories corresponding to the first address When at least one of the cells is a high logic level, programming the first memory cells corresponding to the first address; and when the first memory cells are programmed and the first address exceeds a last sector bit At the time of the address, the preprogramming process is completed. The erasing method of claim 2, wherein the step of pre-programming the first memory cells of the flash memory further comprises: when the first memory cells are programmed and the first address When the last sector address is not exceeded, the first address is updated to a second address; when the second address is the last valid row address, according to the second address, the pair corresponds to the first Performing the pre-programmed verification on the first memory cells of the two addresses and the second and third memory cells to determine whether the first, second, and third memory cells corresponding to the second address are a low logic level; when at least one of the first, second, and third memory cells corresponding to the second address is a high logic level, the first one corresponding to the second address Programming the second and third memory cells; and completing when the first, second, and third memory cells corresponding to the second address are programmed and the second address exceeds the last sector address Preprogrammed program. The wiping method of claim 1, wherein the step of erasing the pre-programmed first memory cells further comprises: erasing the first, second, and third portions in a segment. a memory cell; performing a erase verification on the erased first memory cells corresponding to the first address according to a first address to determine that the corresponding address corresponding to the first address has been erased Whether the first memory cell is a high logic level; when one of the first memory cells corresponding to the first address has been erased is a low logic level, the first of the segments is re-erased First, second and third memory cells; The erase process is completed when the first memory cells corresponding to the erased first address are high logic levels and the first address exceeds the last sector address. The erasing method of claim 4, wherein the step of erasing the pre-programmed first memory cells further comprises: when the first address corresponding to the first address is erased, the first When the memory cell is a high logic level and the first address does not exceed the last sector address, the first address is updated to a second address; when the second address is the last valid row address And performing, according to the second address, the erased verification on the erased first memory cells corresponding to the second address and the second and third memory cells to determine that the second is corresponding to the second address Whether the first, second, and third memory cells of the address have been erased are high logic levels; when the first, second, and third memories are erased corresponding to the second address Retrieving the first, second, and third memory cells in the segment when one of the cells is a low logic level; and when the first address corresponding to the second address has been erased The erase process is completed when the second and third memory cells are at a high logic level and the second address exceeds the last sector address. The erasing method of claim 1, wherein the step of erasing the first memory cells after the programming further comprises: according to a first address, corresponding to the first address Waiting for the first memory cell to perform an over-erase verification to determine whether the first memory cells corresponding to the erased first address are over-erased; Performing post programming on the first memory cells that have been over-erased when one of the first memory cells that have been erased is over-erased; and when the first memory cells are not over-erased, The first address is updated to a second address. The erasing method of claim 6, wherein the step of erasing the first memory cells after the programming further comprises: when the second address exceeds the last valid row address, according to the a second address, performing the over-erase verification on the first memory cells corresponding to the second address and the second and third memory cells to determine that the second address is erased Whether the first, second, and third memory cells are over-erased; and when the second and third memory cells are not over-erased, the post-programming process is completed. The erasing method of claim 1, wherein the step of programming the second memory cells further comprises: performing, according to a first address, the second memory cell corresponding to the first address Programming; performing a program verification on the programmed second memory cell corresponding to the first address to determine whether the second memory cell corresponding to the first address is a low logic level; and when corresponding to When the second memory cell programmed by the first address is a high logic level, the second memory cell corresponding to the first address is reprogrammed. The wiping method of claim 8, wherein the step of programming the second memory cells further comprises: When the programmed second memory cell corresponding to the first address is a low logic level and the first address exceeds a last valid column address, the flash memory has been erased; when programmed When the second memory cell is a low logic level and the first address does not exceed the last valid column address, the first address is updated to a second address; according to the second address, the corresponding address Programming the second memory cell at the second address; performing the program verification on the programmed second memory cell corresponding to the second address to determine the second corresponding to the second address Whether the memory cell is a low logic level; when the programmed second memory cell corresponding to the second address is a high logic level, reprogramming the second memory cell corresponding to the second address; And when the second memory cell programmed to correspond to the second address is a low logic level and the second address exceeds a last valid column address, the flash memory has completed erasing. The wiping method of claim 1, further comprising: after the flash memory is erased, programming the first memory cells corresponding to a write address according to the data to be programmed; The third memory cell corresponding to the write address is programmed to indicate that the first memory cells of the column line corresponding to the write address have been programmed. The erasing method of claim 1, further comprising: determining whether the segment is blank according to logic levels of the second and third memory cells in a segment of the flash memory Section Where the second memory cells are low logic levels and the third memory cells are high logic levels, the sector is a blank segment. The erasing method of claim 11, wherein when the second memory cell is a low logic level and at least one of the third memory cells is a low logic level, the segment is not a blank segment, and When at least one of the second memory cells is at a high logic level, the segment is not a blank segment.