TWI500128B - Package substrate with support and preparation method thereof - Google Patents
Package substrate with support and preparation method thereof Download PDFInfo
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- TWI500128B TWI500128B TW100144800A TW100144800A TWI500128B TW I500128 B TWI500128 B TW I500128B TW 100144800 A TW100144800 A TW 100144800A TW 100144800 A TW100144800 A TW 100144800A TW I500128 B TWI500128 B TW I500128B
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Description
本發明係有關一種封裝基板,尤指一種用於QFN封裝結構的封裝基板及其製法。The present invention relates to a package substrate, and more particularly to a package substrate for a QFN package structure and a method of fabricating the same.
傳統以導線架(lead frame)作為晶片承載件之半導體封件之型態及種類繁多,如習知四邊形平面封裝結構(Quad Flat package, QFP),而隨著電子產業的蓬勃發展,電子產品也逐漸邁向多功能、高性能的趨勢,且亦同時邁向微型化(miniaturization)的發展。因此,遂發展出了一種新的四邊扁平無導腳(Quad Flat Non-leaded, QFN)封裝結構,以縮小封裝結構之尺寸。Traditionally, there are many types and types of semiconductor packages using lead frames as wafer carriers, such as the conventional Quad Flat package (QFP), and with the booming electronics industry, electronic products are also Gradually towards a multi-functional, high-performance trend, and at the same time towards the development of miniaturization. As a result, 遂 has developed a new Quad Flat Non-leaded (QFN) package structure to reduce the size of the package structure.
請參閱第1A至1F圖,係為習知QFN封裝結構1之製法之剖面示意圖。Please refer to FIGS. 1A to 1F for a schematic cross-sectional view of a conventional QFN package structure 1.
如第1A圖所示,於一載板10上形成銅層11。As shown in FIG. 1A, a copper layer 11 is formed on a carrier 10.
如第1B圖所示,於該銅層11上經圖案化微蝕以形成複數電性接觸墊12與置晶墊13。As shown in FIG. 1B, patterned micro-etching is performed on the copper layer 11 to form a plurality of electrical contact pads 12 and a pad 13.
如第1C圖所示,於該些電性接觸墊12與置晶墊13上形成表面處理層14。As shown in FIG. 1C, a surface treatment layer 14 is formed on the electrical contact pads 12 and the seed pads 13.
如第1D圖所示,移除該些電性接觸墊12與置晶墊13周圍多餘之銅層11,以形成封裝基板1a。As shown in FIG. 1D, the excess copper layer 11 around the electrical contact pads 12 and the pad 13 is removed to form the package substrate 1a.
如第1E圖所示,係於該置晶墊13上承載晶片17並藉由焊線170電性連接該些電性接觸墊12,再形成封裝膠體18於該載板10上,以包覆該些電性接觸墊12、置晶墊13、晶片17與焊線170。As shown in FIG. 1E, the wafer 17 is carried on the crystal pad 13 and electrically connected to the electrical contact pads 12 by a bonding wire 170, and the encapsulant 18 is formed on the carrier 10 to be coated. The electrical contact pads 12, the pad 13, the wafer 17, and the bonding wires 170.
如第1F圖所示,移除該載板10,以外露出該些電性接觸墊12之底部與置晶墊13之底部。As shown in FIG. 1F, the carrier 10 is removed, and the bottom of the electrical contact pads 12 and the bottom of the crystal pad 13 are exposed.
惟,習知QFN封裝結構1之製法,僅能於該載板10之其中一側上形成該些電性接觸墊12與置晶墊13,故一次製程僅能製造出一批封裝基板1a,供封裝製程使用,導致生產效率不佳,而難以降低製作成本。However, the conventional QFN package structure 1 can only form the electrical contact pads 12 and the pad 13 on one side of the carrier 10, so that only one package substrate 1a can be manufactured in one process. Used in the packaging process, resulting in poor production efficiency, and it is difficult to reduce production costs.
因此,如何克服上述習知技術之種種問題,實已成目前亟欲解決的課題。Therefore, how to overcome the various problems of the above-mentioned prior art has become a problem that is currently being solved.
鑑於上述習知技術之種種缺失,本發明係揭露一種具有支撐體的封裝基板之製法,係包括:將兩銅箔基板片以其銅層相互疊置;於該兩銅箔基板片上結合強化板體以形成支撐結構;於該強化板體上形成複數電性接觸墊;以及沿該兩銅箔基板片之側邊進行切割,令該兩銅箔基板片相互疊置之銅層分開,使該支撐結構分離成兩支撐體,俾得到兩具有該支撐體的封裝基板。In view of the above-mentioned various deficiencies of the prior art, the present invention discloses a method for manufacturing a package substrate having a support body, comprising: stacking two copper foil substrate sheets with their copper layers; and bonding the reinforcing plates to the two copper foil substrate sheets. Forming a support structure; forming a plurality of electrical contact pads on the tempered plate; and cutting along sides of the two copper foil substrate sheets to separate the copper layers of the two copper foil substrate sheets from each other The support structure is separated into two supports, and two package substrates having the support are obtained.
本發明復提供一種具有支撐體的封裝基板,係包括:銅箔基板片、結合於該銅箔基板片上以形成支撐體之強化板體、以及形成於該強化板體上之複數電性接觸墊。The invention further provides a package substrate having a support body, comprising: a copper foil substrate piece, a reinforced plate body bonded to the copper foil substrate piece to form a support body, and a plurality of electrical contact pads formed on the reinforced plate body .
前述之具有支撐體的封裝基板及其製法中,該第一金屬剝離層係以物理方式結合該第二金屬剝離層。In the above package substrate having a support and a method of manufacturing the same, the first metal release layer physically bonds the second metal release layer.
前述之具有支撐體的封裝基板及其製法,可包括於該電性接觸墊上形成表面處理層。The foregoing package substrate having a support and a method of manufacturing the same may include forming a surface treatment layer on the electrical contact pad.
另外,前述之具有支撐體的封裝基板及其製法,可包括當形成該些電性接觸墊時,一併於該第二金屬剝離層上形成置晶墊。或者,於該第二金屬剝離層與電性接觸墊上形成增層結構,令該增層結構之最外層形成置晶墊。In addition, the package substrate having the support body and the method for fabricating the same may include forming a crystal pad on the second metal release layer when the electrical contact pads are formed. Alternatively, a build-up structure is formed on the second metal release layer and the electrical contact pad, so that the outermost layer of the buildup structure forms a crystal pad.
由上可知,本發明之具有支撐體的封裝基板及其製法,係藉由在該兩銅箔基板片上結合強化板體以形成支撐結構,故可於該支撐結構兩側製作該置晶墊與電性接觸墊,以形成兩具有該支撐體的封裝基板,故一次製程可製造出兩批封裝基板,供封裝製程使用。因此,相較於習知技術之產能,本發明之製法可提升生產效率,以降低製作成本。It can be seen from the above that the package substrate having the support body of the present invention and the method for manufacturing the same are formed by combining the reinforcing plate body on the two copper foil substrate sheets to form a support structure, so that the crystal pad can be fabricated on both sides of the support structure. The electrical contact pads are used to form two package substrates having the support body, so that one batch of package substrates can be manufactured in one process for use in a packaging process. Therefore, the production method of the present invention can increase the production efficiency to reduce the production cost compared to the productivity of the prior art.
以下藉由特定的具體實施例說明本發明之實施方式,熟悉此技藝之人士可由本說明書所揭示之內容輕易地瞭解本發明之其他優點及功效。The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.
須知,本說明書所附圖式所繪示之結構、比例、大小等,均僅用以配合說明書所揭示之內容,以供熟悉此技藝之人士之瞭解與閱讀,並非用以限定本發明可實施之限定條件,故不具技術上之實質意義,任何結構之修飾、比例關係之改變或大小之調整,在不影響本發明所能產生之功效及所能達成之目的下,均應仍落在本發明所揭示之技術內容得能涵蓋之範圍內。同時,本說明書中所引用之如“上”、“下”、“側邊”及“一”等之用語,亦僅為便於敘述之明瞭,而非用以限定本發明可實施之範圍,其相對關係之改變或調整,在無實質變更技術內容下,當亦視為本發明可實施之範疇。It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "lower", "side" and "one" are used in the description, and are not intended to limit the scope of the invention. Changes or adjustments to the relative relationship are considered to be within the scope of the invention without departing from the scope of the invention.
請參閱第2A至2D圖,係為本發明之具有支撐體2c的封裝基板2之製法之剖視示意圖。2A to 2D are schematic cross-sectional views showing a method of manufacturing the package substrate 2 having the support 2c of the present invention.
如第2A圖所示,首先,提供兩銅箔基板片(Copper clad laminate, CCL)20與兩強化板體21,各該銅箔基板片20係具有絕緣層200及設於該絕緣層200相對兩側之銅層201,202,該兩銅箔基板片20以其中一銅層201相互疊置,且各該強化板體21具有介電層210、設於該介電層210上之第一金屬剝離層211、及設於該第一金屬剝離層211上之第二金屬剝離層212。接著,於該兩銅箔基板片20上分別壓合該強化板體21之介電層210,令該兩介電層210合為一體以包覆該兩銅箔基板片20,而固定該兩銅箔基板片20,俾形成支撐結構2b。As shown in FIG. 2A, first, a copper clad laminate (CCL) 20 and two reinforced panels 21 are provided. Each of the copper foil substrate sheets 20 has an insulating layer 200 and is disposed on the insulating layer 200. The copper layers 201, 202 on both sides, the two copper foil substrate sheets 20 are overlapped with each other by a copper layer 201, and each of the reinforcing plate bodies 21 has a dielectric layer 210 and a first metal stripping provided on the dielectric layer 210. The layer 211 and the second metal stripping layer 212 disposed on the first metal stripping layer 211. Then, the dielectric layers 210 of the reinforced plate body 21 are respectively pressed onto the two copper foil substrate sheets 20, and the two dielectric layers 210 are integrated to cover the two copper foil substrate sheets 20, and the two are fixed. The copper foil substrate sheet 20 is formed into a support structure 2b.
於本實施例中,該絕緣層200之材質可例如為雙順丁烯二酸醯亞胺/三氮阱(Bismaleimide triazine,簡稱BT)。然而,有關銅箔基板片20之種類繁多,且為業界所熟知,故不再贅述。In this embodiment, the material of the insulating layer 200 can be, for example, Bisaleimide triazine (BT). However, there are many types of copper foil substrate sheets 20 which are well known in the art and will not be described again.
再者,該介電層210之材質可例如為預浸材(prepreg,簡稱PP),且該介電層210之厚度可例如為100μm,而該第一金屬剝離層211與第二金屬剝離層212係為銅材,並且兩者之厚度可為18μm及3μm。The material of the dielectric layer 210 can be, for example, a prepreg (PP for short), and the thickness of the dielectric layer 210 can be, for example, 100 μm, and the first metal stripping layer 211 and the second metal stripping layer. The 212 series is a copper material, and the thickness of both can be 18 μm and 3 μm.
又,該第一金屬剝離層211係以物理方式結合該第二金屬剝離層212,且該物理方式係為卡合、靜電、吸附、或黏著物等,亦即該第一金屬剝離層211與第二金屬剝離層212之間並無需藉蝕刻分離。Moreover, the first metal stripping layer 211 physically bonds the second metal stripping layer 212, and the physical manner is a bonding, static electricity, adsorption, or adhesion, etc., that is, the first metal stripping layer 211 and The second metal stripping layer 212 does not need to be separated by etching.
如第2B圖所示,經圖案化製程,於該第二金屬剝離層212上形成複數電性接觸墊22與置晶墊23。As shown in FIG. 2B, a plurality of electrical contact pads 22 and a pad 23 are formed on the second metal lift-off layer 212 by a patterning process.
然而,有關圖案化製程之方法繁多,如蝕刻、電鍍等,且為業界所熟知,故不再贅述。However, there are many methods for patterning processes, such as etching, electroplating, etc., which are well known in the industry and will not be described again.
如第2C圖所示,於該些電性接觸墊22上形成表面處理層24。於本實施例中,形成該表面處理層24之材質係為鎳/金(Ni/Au)、鎳鈀金(Ni/Pd/Au)或金等選擇,且其形成方式可為化鍍或電鍍等方式,若以化鍍方式形成,則該表面處理層24之材質係為化鎳/金(Ni/Au)、化鎳鈀金(Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG)或直接浸金(Direct Immersion Gold, DIG)。或者,併用化鍍與電鍍方式,即以該第二金屬剝離層212為導電途徑,形成例如電鍍鎳/化鍍鈀/電鍍金的該表面處理層24。As shown in FIG. 2C, a surface treatment layer 24 is formed on the electrical contact pads 22. In this embodiment, the material of the surface treatment layer 24 is selected from nickel/gold (Ni/Au), nickel palladium gold (Ni/Pd/Au) or gold, and the formation thereof may be plating or plating. In the other manner, if formed by a plating method, the surface treatment layer 24 is made of nickel/gold (Ni/Au), electroless nickel/electroplated gold (Electroless Nickel/Electroless Palladium/Immersion Gold, ENEPIG) or direct immersion gold. (Direct Immersion Gold, DIG). Alternatively, the surface treatment layer 24 such as electroplated nickel/palladium-plated/plated gold may be formed by a plating and plating method, that is, using the second metal stripping layer 212 as a conductive path.
如第2C’及2C”圖所示,亦可先不形成置晶墊23,而先於該第二金屬剝離層212與電性接觸墊22上形成增層結構25,再形成該表面處理層24。As shown in the 2C' and 2C", the pad 23 may not be formed first, and the build-up structure 25 is formed on the second metal stripping layer 212 and the electrical contact pad 22, and the surface layer is formed. twenty four.
其中,該增層結構25係包含至少一增層介電層250、設於各該增層介電層250上之線路層251、及設於各該增層介電層250中之導電盲孔252,該導電盲孔252係電性連接該線路層251與電性接觸墊22,且最外層之線路層251具有置晶墊253與複數電性連接墊254,以於該些電性連接墊254上形成表面處理層24。The build-up structure 25 includes at least one build-up dielectric layer 250, a circuit layer 251 disposed on each of the build-up dielectric layers 250, and conductive vias disposed in each of the build-up dielectric layers 250. 252, the conductive blind via 252 is electrically connected to the circuit layer 251 and the electrical contact pad 22, and the outermost circuit layer 251 has a pad 253 and a plurality of electrical connection pads 254 for the electrical connection pads. A surface treatment layer 24 is formed on 254.
再者,該增層結構25係可為一層(如第2C’圖所示)或多層(如第2C”圖所示之三層)。Furthermore, the buildup structure 25 can be one layer (as shown in Figure 2C') or multiple layers (as shown in Figure 2C).
又,本發明封裝基板係用於QFN封裝結構中,故不需於第2C圖之第二金屬剝離層212、或第2C’與2C”圖之增層結構25上形成絕緣保護層。Further, since the package substrate of the present invention is used in the QFN package structure, it is not necessary to form an insulating protective layer on the second metal lift-off layer 212 of Fig. 2 or the build-up structure 25 of the second C' and 2C" patterns.
如第2D及2D’圖所示,沿該兩銅箔基板片20之側邊進行切割,如第2C及2C’圖所示之切割線L,令該兩銅箔基板片20相互疊置之銅層201自動分開,使該支撐結構2b分離成兩支撐體2c,以分離出上、下側之具有該支撐體2c的封裝基板2,2’。As shown in FIGS. 2D and 2D', the side of the two copper foil substrate sheets 20 are cut, as shown by the cutting lines L shown in FIGS. 2C and 2C', so that the two copper foil substrate sheets 20 overlap each other. The copper layer 201 is automatically separated, and the support structure 2b is separated into two support bodies 2c to separate the package substrates 2, 2' having the support bodies 2c on the upper and lower sides.
本發明之具有支撐體2c的封裝基板2,2’之製法,主要藉由在該兩銅箔基板片20上結合強化板體21以形成支撐結構2b,故可於該支撐結構2b上、下兩側同時製作該置晶墊23與電性接觸墊22,再將該支撐結構2b分離成兩支撐體2c,以形成兩具有該支撐體2c的封裝基板2,2’。因此,一次製程可製造出兩批封裝基板2,2’,供後續封裝製程使用。The method for manufacturing the package substrate 2, 2' having the support 2c of the present invention is mainly to form the support structure 2b by bonding the reinforcing plate 21 to the two copper foil substrate sheets 20, so that the support structure 2b can be placed on the support structure 2b. The crystal pad 23 and the electrical contact pad 22 are simultaneously fabricated on both sides, and the support structure 2b is separated into two support bodies 2c to form two package substrates 2, 2' having the support body 2c. Therefore, one batch process can produce two batches of package substrates 2, 2' for use in subsequent packaging processes.
本發明復提供一種具有支撐體2c的封裝基板2,係包括:於相對兩側具有銅層201,202之銅箔基板片20、設於該銅箔基板片20之其中一銅層202上之強化板體21、以及形成於該強化板體21上之複數電性接觸墊22。The present invention provides a package substrate 2 having a support 2c, comprising: a copper foil substrate sheet 20 having copper layers 201, 202 on opposite sides, and a reinforcing plate disposed on one of the copper layers 202 of the copper foil substrate sheet 20. The body 21 and the plurality of electrical contact pads 22 formed on the reinforcing plate body 21.
所述之支撐體2c係包含該銅箔基板片20與該強化板體21。The support body 2c includes the copper foil substrate sheet 20 and the reinforcing plate body 21.
所述之銅箔基板片20復包含絕緣層200,且該銅層201,202係設於該絕緣層200相對兩側。然而,銅箔基板片之種類繁多,並無特別限制。The copper foil substrate sheet 20 further includes an insulating layer 200, and the copper layers 201, 202 are disposed on opposite sides of the insulating layer 200. However, there are many types of copper foil substrate sheets, and there is no particular limitation.
所述之強化板體21具有結合該銅層202之介電層210、設於該介電層210上之第一金屬剝離層211、及設於該第一金屬剝離層211上之第二金屬剝離層212;於本實施例中,該第一金屬剝離層211係以物理方式結合該第二金屬剝離層212。The reinforcing plate body 21 has a dielectric layer 210 bonded to the copper layer 202, a first metal stripping layer 211 disposed on the dielectric layer 210, and a second metal disposed on the first metal stripping layer 211. The peeling layer 212; in the embodiment, the first metal peeling layer 211 physically bonds the second metal peeling layer 212.
所述之電性接觸墊22係設於該第二金屬剝離層212上,且於該些電性接觸墊22上形成有表面處理層24。The electrical contact pads 22 are disposed on the second metal release layer 212, and the surface treatment layer 24 is formed on the electrical contact pads 22.
所述之封裝基板2復包括設於該第二金屬剝離層212上之置晶墊23。The package substrate 2 further includes a pad 23 disposed on the second metal release layer 212.
於另一實施例中,該封裝基板2’亦可包括形成於該第二金屬剝離層212與電性接觸墊22上之增層結構25。In another embodiment, the package substrate 2' may further include a build-up structure 25 formed on the second metal release layer 212 and the electrical contact pads 22.
所述之增層結構25係包含至少一增層介電層250、設於各該增層介電層250上之線路層251、及設於各該增層介電層250中之導電盲孔252,該導電盲孔252係電性連接該線路層251與電性接觸墊22,且最外層之線路層251具有置晶墊253與複數電性連接墊254,且於該些電性連接墊254上形成有表面處理層24。The build-up structure 25 includes at least one build-up dielectric layer 250, a circuit layer 251 disposed on each of the build-up dielectric layers 250, and conductive vias disposed in each of the build-up dielectric layers 250. 252, the conductive blind via 252 is electrically connected to the circuit layer 251 and the electrical contact pad 22, and the outermost circuit layer 251 has a pad 253 and a plurality of electrical connection pads 254, and the electrical connection pads A surface treatment layer 24 is formed on 254.
請參閱第3A至3D圖,係為應用本發明之具有支撐體2c的封裝基板2之後續封裝製程之剖視示意圖。於本實施例中,係以第2D圖之封裝基板2進行封裝,該封裝基板2係具有複數封裝單元2a,如第3C圖所示。Please refer to FIGS. 3A to 3D, which are schematic cross-sectional views showing a subsequent packaging process of the package substrate 2 having the support 2c of the present invention. In the present embodiment, the package substrate 2 of FIG. 2D is packaged, and the package substrate 2 has a plurality of package units 2a as shown in FIG. 3C.
如第3A圖所示,接續第2D圖之製程,進行封裝製程,係於該置晶墊23上設置晶片27,且令該些電性接觸墊22藉由焊線270電性連接該晶片27;接著,於該支撐體2c之強化板體21上形成封裝膠體28,以包覆該電性接觸墊22、置晶墊23、晶片27與焊線270。As shown in FIG. 3A, following the process of FIG. 2D, a packaging process is performed on which the wafers 27 are disposed, and the electrical contact pads 22 are electrically connected to the wafers 27 by bonding wires 270. Then, an encapsulant 28 is formed on the reinforcing plate 21 of the support 2c to cover the electrical contact pad 22, the pad 23, the wafer 27 and the bonding wire 270.
如第3B圖所示,分離該第一金屬剝離層211與第二金屬剝離層212,以移除該銅箔基板片20、該介電層210與第一金屬剝離層211,而外露出該第二金屬剝離層212。As shown in FIG. 3B, the first metal stripping layer 211 and the second metal stripping layer 212 are separated to remove the copper foil substrate sheet 20, the dielectric layer 210 and the first metal stripping layer 211, and the outer metal stripping layer 211 is exposed. The second metal stripping layer 212.
於本實施例中,因該第一金屬剝離層211係以物理方式結合該第二金屬剝離層212,故分離該第一金屬剝離層211與第二金屬剝離層212時,僅需以如剝離之物理方式進行分離。In this embodiment, since the first metal stripping layer 211 physically bonds the second metal stripping layer 212, when the first metal stripping layer 211 and the second metal stripping layer 212 are separated, only the stripping is required. Physical separation.
如第3C圖所示,藉由蝕刻方式移除該第二金屬剝離層212,且一併微蝕刻該些電性接觸墊22之部分底部與置晶墊23之部分底部,以外露出該些電性接觸墊22’底部與置晶墊23’底部。As shown in FIG. 3C, the second metal lift-off layer 212 is removed by etching, and a portion of the bottom portions of the electrical contact pads 22 and a portion of the bottom portion of the crystal pad 23 are microetched to expose the electricity. The bottom of the contact pad 22' is at the bottom of the pad 23'.
如第3D圖所示,沿各該封裝單元2a進行切割,如第3C圖所示之切割線S,以取得複數個封裝結構3,且於該電性接觸墊22’底部上結合焊球29。As shown in FIG. 3D, cutting is performed along each of the package units 2a, such as the cutting line S shown in FIG. 3C, to obtain a plurality of package structures 3, and solder balls 29 are bonded to the bottom of the electrical contact pads 22'. .
請參閱第4圖,係為應用本發明之具有支撐體2c的封裝基板2’之後續封裝製程之剖視示意圖。於本實施例中,係以第2D’圖之封裝基板2’進行封裝,且封裝製程之詳細步驟可參考第3A至3D圖。Referring to Fig. 4, there is shown a cross-sectional view showing a subsequent packaging process of the package substrate 2' having the support 2c of the present invention. In the present embodiment, the package substrate 2' of the 2D' is packaged, and the detailed steps of the package process can be referred to the 3A to 3D drawings.
如第4圖所示,係於該增層結構25之置晶墊253上設置晶片27,且令該些電性連接墊254藉由焊線270電性連接該晶片27;接著,形成封裝膠體28,以包覆該電性連接墊254、置晶墊253、晶片27與焊線270。As shown in FIG. 4, the wafer 27 is disposed on the pad 253 of the build-up structure 25, and the electrical connection pads 254 are electrically connected to the wafer 27 by bonding wires 270; and then, the package colloid is formed. 28, to cover the electrical connection pad 254, the crystal pad 253, the wafer 27 and the bonding wire 270.
最後,移除該銅箔基板片20與強化板體21,再進行切割與植設焊球29,以取得複數個封裝結構3’。Finally, the copper foil substrate sheet 20 and the reinforcing plate body 21 are removed, and the soldering and soldering balls 29 are cut to obtain a plurality of package structures 3'.
綜上所述,本發明之具有支撐體的封裝基板及其製法,主要藉由在該支撐結構上、下兩側製作該置晶墊與電性接觸墊,再將該支撐結構分離成兩支撐體,以形成兩具有該支撐體的封裝基板,故一次製程可製造出兩批封裝基板,以提升生產效率,而有效降低製作成本。In summary, the package substrate with the support body of the present invention and the method for manufacturing the same are mainly formed by forming the crystal pad and the electrical contact pad on the upper and lower sides of the support structure, and then separating the support structure into two supports. The body is formed to form two package substrates having the support body, so that two batches of package substrates can be manufactured in one process to improve production efficiency and effectively reduce manufacturing costs.
上述實施例係用以例示性說明本發明之原理及其功效,而非用於限制本發明。任何熟習此項技藝之人士均可在不違背本發明之精神及範疇下,對上述實施例進行修改。因此本發明之權利保護範圍,應如後述之申請專利範圍所列。The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.
1,3,3’...封裝結構1,3,3’. . . Package structure
1a,2,2’...封裝基板1a, 2, 2’. . . Package substrate
10...載板10. . . Carrier board
11,201,202...銅層11,201,202. . . Copper layer
12,22,22’...電性接觸墊12,22,22’. . . Electrical contact pad
13,23,23’,253...置晶墊13,23,23’,253. . . Crystal pad
14,24...表面處理層14,24. . . Surface treatment layer
17,27...晶片17,27. . . Wafer
170,270...焊線170,270. . . Welding wire
18,28...封裝膠體18,28. . . Encapsulant
2a...封裝單元2a. . . Package unit
2b...支撐結構2b. . . supporting structure
2c...支撐體2c. . . Support
20...銅箔基板片20. . . Copper foil substrate
200...絕緣層200. . . Insulation
21...強化板體twenty one. . . Reinforced plate
210...介電層210. . . Dielectric layer
211...第一金屬剝離層211. . . First metal peeling layer
212...第二金屬剝離層212. . . Second metal peeling layer
25...增層結構25. . . Layered structure
250...增層介電層250. . . Additive dielectric layer
251...線路層251. . . Circuit layer
252...導電盲孔252. . . Conductive blind hole
254...電性連接墊254. . . Electrical connection pad
29...焊球29. . . Solder ball
L,S...切割線L, S. . . Cutting line
第1A至1F圖係為習知QFN封裝結構之製法的剖視示意圖;1A to 1F are schematic cross-sectional views showing a method of manufacturing a conventional QFN package structure;
第2A至2D圖係為本發明之具有支撐體的封裝基板之製法的剖視示意圖;其中,第2C’至2D’圖係為第2C至2D圖之另一實施例,第2C”圖係為第2C’圖之另一實施例;2A to 2D are schematic cross-sectional views showing a method of manufacturing a package substrate having a support according to the present invention; wherein, the 2C' to 2D' diagram is another embodiment of the 2C to 2D diagram, and the 2C" diagram Another embodiment of the 2C' diagram;
第3A至3D圖係為應用本發明之具有支撐體的封裝基板之後續製法的剖視示意圖;以及3A to 3D are schematic cross-sectional views showing a subsequent method of applying the package substrate having the support of the present invention;
第4圖係為應用本發明之具有支撐體的封裝基板之後續製法之另一實施例的剖視示意圖。Fig. 4 is a schematic cross-sectional view showing another embodiment of a subsequent process for applying a package substrate having a support of the present invention.
2...封裝基板2. . . Package substrate
2c...支撐體2c. . . Support
20...銅箔基板片20. . . Copper foil substrate
200...絕緣層200. . . Insulation
201,202...銅層201,202. . . Copper layer
21...強化板體twenty one. . . Reinforced plate
210...介電層210. . . Dielectric layer
211...第一金屬剝離層211. . . First metal peeling layer
212...第二金屬剝離層212. . . Second metal peeling layer
22...電性接觸墊twenty two. . . Electrical contact pad
23...置晶墊twenty three. . . Crystal pad
24...表面處理層twenty four. . . Surface treatment layer
Claims (10)
銅箔基板片,係包含絕緣層及設於該絕緣層相對兩側之銅層;
強化板體,結合於該銅箔基板片之其中一銅層上以由該強化板體與該銅箔基板片形成該支撐體,該強化板體具有依序設於該其中一銅層上之介電層、第一金屬剝離層、及第二金屬剝離層;以及
電性接觸墊,係形成於該第二金屬剝離層上。A package substrate having a support body, comprising:
a copper foil substrate sheet comprising an insulating layer and a copper layer disposed on opposite sides of the insulating layer;
a reinforcing plate body is bonded to one of the copper layers of the copper foil substrate to form the support body from the reinforcing plate body and the copper foil substrate piece, wherein the reinforcing plate body is sequentially disposed on the one copper layer a dielectric layer, a first metal release layer, and a second metal release layer; and an electrical contact pad formed on the second metal release layer.
提供兩銅箔基板片,各該銅箔基板片係具有絕緣層及設於該絕緣層相對兩側之銅層,且該兩銅箔基板片以其銅層相互疊置;
於該兩銅箔基板片上結合強化板體以形成支撐結構,該強化板體具有包覆該兩銅箔基板片以固定該兩銅箔基板片之介電層、設於該介電層上之第一金屬剝離層、及設於該第一金屬剝離層上之第二金屬剝離層;
於該第二金屬剝離層上形成複數電性接觸墊;以及
沿該兩銅箔基板片之側邊進行切割,令該兩銅箔基板片相互疊置之銅層分開,使該支撐結構分離成兩支撐體,俾得到兩具有該支撐體的封裝基板。A method for manufacturing a package substrate having a support body includes:
Providing two copper foil substrate sheets, each of the copper foil substrate sheets having an insulating layer and a copper layer disposed on opposite sides of the insulating layer, and the two copper foil substrate sheets are stacked on each other with their copper layers;
The reinforcing plate body is bonded to the two copper foil substrate sheets to form a supporting structure, and the reinforcing plate body has a dielectric layer covering the two copper foil substrate sheets to fix the copper foil substrate sheets, and is disposed on the dielectric layer. a first metal release layer and a second metal release layer disposed on the first metal release layer;
Forming a plurality of electrical contact pads on the second metal stripping layer; and cutting along the sides of the two copper foil substrate sheets to separate the copper layers of the two copper foil substrate sheets from each other, so that the supporting structure is separated into Two support bodies are obtained, and two package substrates having the support body are obtained.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
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| TW100144800A TWI500128B (en) | 2011-12-06 | 2011-12-06 | Package substrate with support and preparation method thereof |
| CN201210127399.0A CN103137568B (en) | 2011-12-02 | 2012-04-26 | Package substrate with support and method for making same |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100144800A TWI500128B (en) | 2011-12-06 | 2011-12-06 | Package substrate with support and preparation method thereof |
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| TW201324712A TW201324712A (en) | 2013-06-16 |
| TWI500128B true TWI500128B (en) | 2015-09-11 |
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|---|---|---|---|---|
| TWI283056B (en) * | 2005-12-29 | 2007-06-21 | Siliconware Precision Industries Co Ltd | Circuit board and package structure thereof |
| TW201010541A (en) * | 2008-08-27 | 2010-03-01 | Advanced Semiconductor Eng | Method of fabricating multi-layered substrate and the substrate thereof |
| TW201015680A (en) * | 2008-10-13 | 2010-04-16 | Subtron Technology Co Ltd | Package carrier and fabricating method thereof |
| TW201041469A (en) * | 2009-05-12 | 2010-11-16 | Phoenix Prec Technology Corp | Coreless packaging substrate, carrier thereof, and method for manufacturing the same |
| TW201121381A (en) * | 2009-12-15 | 2011-06-16 | Samsung Electro Mech | Carrier for manufacturing substrate and method of manufacturing substrate using the same |
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- 2011-12-06 TW TW100144800A patent/TWI500128B/en active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI283056B (en) * | 2005-12-29 | 2007-06-21 | Siliconware Precision Industries Co Ltd | Circuit board and package structure thereof |
| TW201010541A (en) * | 2008-08-27 | 2010-03-01 | Advanced Semiconductor Eng | Method of fabricating multi-layered substrate and the substrate thereof |
| TW201015680A (en) * | 2008-10-13 | 2010-04-16 | Subtron Technology Co Ltd | Package carrier and fabricating method thereof |
| TW201041469A (en) * | 2009-05-12 | 2010-11-16 | Phoenix Prec Technology Corp | Coreless packaging substrate, carrier thereof, and method for manufacturing the same |
| TW201121381A (en) * | 2009-12-15 | 2011-06-16 | Samsung Electro Mech | Carrier for manufacturing substrate and method of manufacturing substrate using the same |
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| TW201324712A (en) | 2013-06-16 |
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