TWI500040B - Flash memory controller - Google Patents

Description

Flash memory controller

The present invention generally relates to memory devices.

Many electronic devices include embedded systems that have a central processor unit (CPU) to control the operation of such devices to provide greatly enhanced functionality and operational flexibility. In general, non-volatile memory is included as part of the embedded system to store operating system code and data for operating the embedded system. Recently, embedded systems have used flash memory as non-volatile memory. Flash memory is reprogrammable and offers the benefits of non-volatile storage.

The present invention provides a method, system and computer program product for performing polling processing between one or more flash memory devices. In some implementations, the polling process can include transmitting a read status command to a flash memory device to detect a read or busy state of the flash memory device. The flash memory device can include a status register for storing a status signal indicating a write (or erase) operation execution state. A solid state disk drive system can perform the polling process by reading a flash register of the flash memory device.

In some implementations, a method is described that includes asserting a control signal to one or more devices; determining an initial wait time after the control signal is asserted; issuing a first command based on the initial wait time; deciding with the first instruction Associated with a first interval time and a second instruction; and issuing the second instruction according to the first interval time.

In some implementations, a method is described that includes controlling a complex number a memory device, the device comprising a first set of memory devices and a second set of memory devices; determining a first period associated with the first set of memory devices; issuing a first according to the first period Commanding to the first set of memory devices; determining a second period associated with the second set of memory devices; and issuing a second command to the second set of memory devices in accordance with the second period.

In some implementations, an apparatus is illustrated that includes a first programmable edit timer for specifying an initial wait time associated with issuing one or more instructions to at least one device; and a second programmable edit timing For specifying an interval to control a period between each issued instruction.

In some implementations, an apparatus is illustrated that includes a bus bar for receiving instructions of one or more memory devices and for controlling the one or more memory devices in accordance with the issued instructions; A memory controller for performing data polling while processing the issued command with the one or more memory devices.

The details of one or more specific embodiments of the invention are set forth in the drawings and description. Other features, objects, and advantages of the invention will be apparent from the description and drawings.

Memory devices such as "EEPROM" (electrically erasable programmable read only memory) have become more widely used, such as: jump drives, memory cards, and other non-volatile devices. Sex memory devices are very common in cameras, video games, computers, and other electronic devices. The first figure shows a block diagram of a memory array 100.

As shown in the first figure, a memory array 100 can be grouped with bits. Weaving. For example, the memory array 100 can include an 8-bit depth 108. The memory array 100 can also be organized with a byte. For example, the memory array 100 can include a portion 104 containing 2k bytes and a portion 106 containing 64 bytes. The memory array 100 can further organize the page of ingredients. For example, the memory array 100 can include 512k pages 102. A single page 112 can be organized into two parts: a first portion 114 (e.g., portion 104 representing a 2k byte) and a second portion 116 (e.g., a portion 106 representing a 64 bit). The second portion 116 generally corresponds to an octet wide data input/output (I/O) path (eg, I/O [0] to I/O [7]). Even further, the memory array 100 can be arranged in a single block. For example, the memory array 100 can include a single block 110 that is equal to 64 pages. Among these, 8Mb memory devices can be formed using the aforementioned bits, bytes, pages, and blocks.

The memory array shown in the first figure can be configured as a flash memory. In some implementations, the flash memory can be a "NAND" type flash memory. NAND flash memory typically has faster erase and write times, higher density, lower cost per bit, and is more durable than NOR-type flash memory. The NAND flash memory can be coupled to a NAND flash I/O interface. However, the NAND flash I/O interface typically only allows sequential access to data. Of course, the memory array shown in the first figure can also be in the form of NOR flash EEPROM, AND flash EEPROM, DiNOR flash EEPROM, serial flash EEPROM, DRAM, SRAM, ROM, EPROM, FRAM, MRAM or PCRAM. .

A NAND flash I/O interface can include multiple pins, each corresponding to a particular function. An example interface is shown in Table 1.

As shown in Table 1 above, many of the pin functions correspond to the pins specified in the interface.

Sample timing diagram for data read operations

Figure 2A shows an example timing diagram associated with each pin within a NAND flash interface during a data read operation. Referring to Figure 2A, area 202 indicates the period in which one or more instructions have been transferred to a flash memory device, and area 204 indicates the period during which data has been transferred to/from the flash memory device. As shown, the write enable signal "WE_" can have a pulse (eg, 25ns period), allowing row address (eg, RA1, RA2, and RA3) and column address (eg, CA1 and CA2) information to be locked in the NAND flash memory. Inside the body device. The command "00h" appearing on the data I/O[7:0] pin indicates a read address input, and the command "3 Oh" indicates a read start.

Other instructions can also be used here. For example, other memory instructions may include, but are not limited to, read operations, write operations, erase operations, read status operations, read ID operations, write configuration scratch operations, write address operations, and Set the operation. For example, the command "05h" can indicate a random data read command, the command "10h" indicates a page program command, the command "20h" indicates a wafer erase command, the command "21h" indicates a segment erase command, and the command " 30h" indicates a read start command, the command "35h" indicates a page read copy command, the command "39h" indicates a write device address command, the command "60h" indicates a single block erase command, and the command "70h". Indicates a read status instruction, instruction "80h" indicates a sequence data input (writer to buffer) instruction, instruction "85h" indicates a random data input instruction, and instruction "8Fh" indicates a target address input copy instruction. The instruction "90h" indicates a reading device type command, the command "A0h" indicates a write configuration temporary storage command, the command "C0h" indicates a program editing/erasing abort command, and the command "D0h" indicates a program editing/wiping. Except for the instruction and "FFh" means the reset instruction, this is just some examples.

Table 2 below shows an example of the upstream and column address multiplexing for this data entry/exit pin (eg I/O[7:0]).

In some implementations, higher address bits can be used to address larger memory configurations (eg, A30 for 2Gb, A31 for 4Gb, A32 for 8Gb, A33 for 16Gb, A34 for 32Gb, A35 for 64Gb) and many more).

On the other hand, under the read enable signal "RE_" pulse, images such as D _out N, D _out N+1, D _out N+2, ... D can be read from the NAND flash memory device. _Out M's information. The ready/busy output signal "R/B_" within a particular logic state indicates whether the output is busy. For example, a ready/busy output signal "R/B_" in a low logic state can indicate a busy state on the output. In this example, the ready/busy output signal "R/B_" can be in a logic high state (ie, becomes a logic indicating a ready state) after some time period after the last rising edge of the write enable signal "WE_". High state).

As shown, the "tR" period of the data transmission time for transferring a data from one unit to an internal partial page buffer can range from the read start command "30h" to the ready/busy output signal "R/B". The rising edge and indicate the read time of the read data. In some implementations, the "tR" period may determine the performance of a solid state drive system (such as the solid state drive system 300 shown in FIG. 3) for READ operations. In some implementations, a long "tR" period indicates that there is a longer wait time for a solid state controller (e.g., solid state controller 308) before the controller can obtain the READ data.

The NAND flash I/O interface is idle and consumes unnecessary bandwidth before the data is ready. As such, we want to maintain the NAND flash I/O interface in a busy state to achieve bandwidth. For example: if The NAND flash I/O interface operates at tRC=25 ns, and the upper limit of the reachable bandwidth can be 40 MB/s (for example, according to the consumption of the 8-bit data bus, and the NAND flash memory) With unlimited bandwidth, such data can be transferred from the NAND flash memory to the solid state controller). However, prior to reading the data back to the solid state drive, this purpose may be difficult to achieve a known "tR" cycle to read a page from a memory cell in a NAND flash memory to an internal buffer.

Thus, in some implementations, multiple devices (eg, multiple wafer enable signals) are included in a single channel to share an identical NAND flash I/O interface, thus covering the "tR" time as much as possible while allowing the same channel. At least one device obtains the data.

In some implementations, the data transmission time is in the range of about 25 [mu]s on a single layer unit (SLC, "single level cell") device, or on a multi-level cell (MLC) device. A range of approximately 60 μs will be discussed in more detail below. During the "tR" period, the ready/busy output signal "R/B_" can be regarded as a logic "0", indicating that the flash memory is in a busy state, during which data cannot be written or erased.

Introduction to single-layer units and multi-level unit

Each unit in a memory device can be programmed to be a single bit per cell (ie, a single layer cell - SLC) or a multi-bit per cell (ie, a multi-level cell - MLC). The threshold voltage of each cell generally determines the type of data stored in the cell. For example, in an SLC memory device, a threshold voltage of 0.5V indicates a programmed cell (ie, a logic "0" state). -0.5V threshold voltage indicates an erased Unit (that is, a logical "1" state).

As the effectiveness and complexity of electronic systems increase, so does the need for additional memory within a system. However, in order to continue to reduce the cost of the system, these related components must generally be kept to a minimum. In a memory application, this can be achieved by using a memory density that adds an integrated circuit. In particular, memory density can be increased by using an MLC memory device. The MLC memory device can increase the amount of data stored in an integrated circuit without the need to add additional cells and/or increase the die size. The MLC memory device can store two or more data bits in each memory unit, although the MLC memory device needs to tightly control the threshold voltage so that each unit uses multiple critical levels. One problem with non-volatile memory cells is that they are closely spaced, especially for MLC, which is a floating gate to floating gate coupling that can cause interference between cells. This interference moves the threshold voltage of adjacent cells when a unit program is edited.

Partly because of the increased number of states requiring closer spacing of the threshold voltage, the MLC memory also has lower reliability than the SLC memory device. For example, a bad bit in a memory device for storing photos is more tolerable than a bad bit in a memory device for storing code. A bad bit in a photo may only produce one bad pixel in millions of pixels, but a bad bit in a code or other data means that an instruction is destroyed, which affects the operation of the entire program.

An MLC memory device has two or more threshold voltage distributions and has two or more data storage states corresponding to the voltage distribution. For example, an MLC memory device that can program 2-bit data has four data storage states (eg [11], [10], [01], and [00]). These states may correspond to a threshold voltage distribution of the MLC memory device, for example: assuming that the individual threshold voltage distribution of the memory cell is -2.7 V or less, 0.3V to 0.7V, 1.3V to 1.7V, and 2.3V to 2.7V, then states [11], [10], [01], and [00] correspond to -2.7V or less, 0.3V, respectively. Up to 0.5V, 1.3V to 1.7V and 2.3V to 2.7V.

A read operation of a flash memory device having a multi-level cell can be performed by detecting data of a multi-level cell. The difference between the cell currents flowing through the selected memory cell is determined according to, for example, the word line voltage according to a certain amount of bit line current and a staircase waveform.

The program editing operation of the flash memory device having the multi-level cell can be performed by supplying a predetermined program editing voltage to the gate of the selected memory cell, and then supplying a ground voltage to the bit line. Then, a power supply voltage can be supplied to the bit line to avoid program editing. If the program edit voltage and the ground voltage are respectively supplied to the word line and the bit line of the selected memory cell, a relatively high electric field is supplied between a floating gate and the memory cell channel. Due to this electric field, electrons of the channel pass through an oxide layer formed between the floating gate and the channel, such that tunneling occurs therein. In this manner, the memory cell threshold voltage programmed using the electronic accumulation in the floating gate can be increased.

Exemplary timing diagram for data paging operations

The second B diagram shows an example timing diagram associated with each pin within a NAND flash interface during a data program editing operation. Referring to FIG. 2B, the area 206 indicates the period in which one or more instructions have been transferred to a flash memory device, and the area 208 indicates the period in which the program editing material can be transferred to the flash memory device, and the area 210 indicates that a status check can be transmitted to the flash memory device for inspection. Check the period of the memory device state.

As shown, the command "80h" appearing on the data I/O[7:0] pins indicates the sequence data input (for example, D _in N...D _in M). The command "10h" indicates an automatic program editing, and is then read by the status indicated by the command "70h". I/O[0]="0" indicates a non-error condition, and I/O[0]=“1” indicates that an error has occurred in the automatic program editing.

In addition, as already discussed, the ready/busy output signal "R/B_" can be in a logic low state, indicating a busy state. In some implementations, the low logic state period of the ready/busy output signal "R/B_" is in the range of hundreds of μs. In addition, the rising edge of the read enable signal "RE_" can be written to the rising edge of the enable signal "WE_" after a certain period of time. In some implementations, this time period can be in the range of approximately 60 ns.

In addition, as shown in the second B-picture, the timing period "tPRG" across the rising edge of the /busy output signal "R/B_" from the trailing edge can indicate the program editing time for the program editing data. In some implementations, the program edit time "tPRG" is in the range of about 200 [mu]s to about 700 [mu]s for an SLC device and about 800 [mu]s to about 3 ms for an MLC device.

In some implementations, the program editing time "tPRG" is similar to the "t4" period, but is used when the program is used to edit data as opposed to when reading data. During the "tPRG" period, the ready/busy output signal "R/B_" can be regarded as a logic "0", indicating that the flash memory is in a busy state, during which data cannot be read or erased.

Example timing diagram for single block erase operation

The second C picture shows a NAND during a single erase operation Example timing diagram associated with each pin in the flash interface. Referring to the second C diagram, the area 212 indicates the period in which one or more instructions have been transmitted to a flash memory device, and the area 214 indicates that a status check has been transmitted to the flash memory device to check the memory device. The period of the state.

As shown, the command "60h" appearing on the data in/out I/O[7:0] pins indicates a single-block erase operation in which sequence line addresses have been supplied (eg RA 1, RA 2, and RA 3). ). The instruction "D0h" indicates a loop 2 block erase operation. This block erase operation can be checked with a status read (command "70h"), where I/O[0] = "0" indicates a non-error condition, and I/O[0] = "1" It is pointed out that an error has occurred within a single block erase.

In this example, the ready/busy output signal "R/B_" may be in a logic low state during the timing cycle, such as in the range of approximately milliseconds (eg, having a predetermined maximum). Similarly, the rising edge of the read enable signal "RE_" can then be written to the rising edge of the enable signal "WE_". According to another example, the rising edge of the write enable signal "WE_" corresponds to the "D0h" command, and the falling edge of the ready/busy output signal "R/B_" can be in the range of approximately 100 ns.

In addition, as shown in the second C-picture, the timing period "tBERS" across the rising edge of the ready/busy output signal "R/B_" from the trailing edge can indicate a single-section wipe for erasing a single block of data. Except time.

In some cases, in addition to transmitting one or more single-block erase commands (or if you do not use the read status command when reading a ready/busy output signal "R/B_"), a single block erase The operation does not require access to the NAND flash I/O interface. The performance of a solid state disk drive system is indirectly dependent on the single block erase operation. In a specific case, in a single section erase operation At the beginning, the drive can determine that some of the erased pages can be used for data program editing. As a result, the disk drive can maintain a program editing operation without performing a single block erase operation. However, as the data stored in the disk drive is modified following the operation of the disk drive, the number of pages available for data program editing is reduced, so the disk drive should perform one or more single block erase operations. Use the empty tab to edit the data program. Thus, a long "tBERS" period should produce a longer wait period for the solid state drive system to accept the PROGRAM command. In other words, the impact of a single erase operation on the overall drive performance is largely dependent on the garbage collection mechanism handled by the firmware (e.g., firmware 324).

In some implementations, the single erase time "tBERS" is in the range of about 1.5 ms to about 2 ms for an SLC device and about 1.5 ms to about 10 ms for an MLC device. During the "tBERS" period, the ready/busy output signal "R/B_" can be regarded as a logic "0" indicating that the flash memory is in a busy state, during which data cannot be read or written.

Solid state disk drive

The third figure shows an example solid state disk drive system 300. As shown in the third diagram, system 300 includes a host 302 and a solid state drive 304. The solid state drive 304 can include a host interface 310, a central processing unit (CPU) 323, a memory controller interface 328, a memory controller 330, and one or more flash memory devices 306a-306d.

The host 302 can communicate with the solid state drive 304 via the host interface 310. In some implementations, the host interface 310 includes a serial advanced technology add-on (SATA, "serial advanced techonology" Attach") interface or parallel advanced technology attachment (PATA) interface. A SATA interface or PATA interface is used to convert sequence or parallel data into parallel or sequence data. For example, if the host interface 310 contains a In the SATA interface, the SATA interface can receive the sequence data transferred from the host 302 through a bus 303 (for example, a SATA bus), and convert the received data into parallel data. In other implementations, the host interface 310 can include a Composite interface. In these implementations, the composite interface can be used, for example, in conjunction with a sequence of interfaces.

In some implementations, host interface 310 can include one or more registers in which operational instructions and addresses from host 302 can be temporarily stored. The host interface 310 can communicate a write or read operation to a solid state controller 308 to respond to information stored in the scratchpad.

In some implementations, solid state drive 304 can include one or more channels 326a-326d (eg, four or eight channels), and each channel can be configured to receive from host 302 or from flash memory 306a- One or more control signals of 306d (eg, a four-wafer enable signal).

Flash memory device

In some implementations, each flash memory device 306 can include non-volatile memory (eg, a single layer of flash memory or a multi-layered flash memory). In some implementations, the non-volatile flash memory can include a NAND type flash memory module. A NAND-type flash memory module includes an instruction/address/data multiplex interface that provides instructions, data, and address through corresponding input/output pins. The advantages of using NAND-type flash memory, contrary to a hard disk method, include: (i) faster boot and recovery time; (ii) longer battery life (eg For wireless applications) and (iii) high data reliability.

In some implementations, each flash memory device can be coupled to channel 326. Each channel can, for example, support one or more input and output lines, a wafer select signal line, a wafer enable signal line, and the like. This channel can also support other signal lines such as write enable, read enable, ready/busy output, and reset signal lines. In some implementations, the flash memory devices 306a-306d can share a common channel. In other implementations, each flash memory device can have its own channel connected to the solid state drive 304 to increase the degree of similarity. For example, flash memory device 306a can be coupled to solid state disk drive 304 using channel 326a; flash memory device 306b can be coupled to solid state disk drive 304 using channel 326b; flash memory device 306c can be coupled to channel 326c using channel 326c Solid state disk drive 304; and flash memory device 306d can be coupled to solid state disk drive 304 using channel 326d.

In some implementations, flash memory devices 306a-306d can be separated. In some implementations, flash memory devices 306a-306d can be coupled to solid state disk drive 304 using standard connectors. Examples of standard connectors include, but are not limited to, SATA, USB (Universal Serial Bus), SCSI (Small Computer System Interface), PCMCIA (Personal Computer Memory Card International Association), and IEEE-1394 (Firewire).

In some implementations, each flash memory device 306 can include one or more solid state storage elements arranged in a row. A solid state storage element can divide the page of ingredients. In some implementations, a solid state storage element has a capacity of 2000 bytes (ie, one page). In some implementations, a solid state storage component can include two registers, providing a total capacity of 4000 bytes (ie, 4 kB).

In some implementations, each flash memory device 306 can also be packaged. One or more columns are included, each column being selected using a wafer enable signal or a wafer select signal. The wafer enable or wafer select signal can select one or more solid state storage elements in response to a host command.

In some implementations, each solid state storage element can include one or more single layer unit (SLC, "single level cell" devices. In some implementations, each solid state storage element can include one or more multi-level cell (MLC) devices. The SLC or MLC devices can be selected using a wafer enable or wafer select signal that can be generated by the solid state controller 308 using a combination of control and address information received from the host 302.

In some implementations, where multiple columns are used, the solid state drive 304 can simultaneously access one or more columns within a same flash memory device. In some implementations, the solid state drive 304 can simultaneously access different columns within different flash memory devices. The ability to access more than one column allows the solid state drive 304 to fully utilize the available resources and channels 326a-326d to increase the overall performance of the solid state drive 304. Further, where the flash memory devices 306a-306d share an identical memory input/output line and control signals (e.g., wafer enable signals), the number of pins of the solid state controller 308 can be reduced to manufacture a solid state disk. The cost of machine 304 is minimized.

Solid state controller

The solid state controller 308 can receive one or more service requests or instructions (eg, read and program editing requirements). The solid state controller 308 can be configured to process any instruction, state, or control request to access the flash memory devices 306a-306d. For example, the solid state controller 308 can be configured to manage and control the storage device and retrieve data within the flash memory devices 306a-306d.

In some implementations, solid state controller 308 is part of a microprocessor system under the control of a microprocessor (not shown). The solid state controller 308 can control the flow of commands and data between the host 302 and the solid state drive 304. In some implementations, the solid state controller 308 can include read only memory (ROM, "random access memory") and other internal circuitry. In some implementations, the solid state controller 308 can be configured to support a number of functions associated with the flash memory devices 306a-306d, such as (without limitation) diagnosing the flash memory devices 306a-306d, transmitting instructions (eg, Initiating, reading, program editing, erasing, pre-charging and updating instructions) to flash memory devices 306a-306d and receiving status from flash memory devices 306a-306d, on a different wafer or an identical wafer Solid state controller 308 can be formed as flash memory devices 306a-306d (e.g., formed as solid state disk drive 304 on a same wafer). Flash memory devices 306a-306d can be coupled to memory interface 328. In some implementations, if the flash memory devices 306a-306d include NAND type memory devices, the memory interface 328 can be a NAND flash input/output interface.

As shown in the third diagram, solid state controller 308 can include an error check code module 312, interface logic 314, a sequencer 316, and a formatter 318. In some implementations, the solid state controller 308 can be coupled to a CPU 323 that includes an embedded firmware 324 that can be controlled by the solid state controller 308. The CPU 323 can include a microprocessor, a signal processor (e.g., a digital signal processor) or a microcontroller. In some implementations, CPU 323 with embedded firmware 324 can exist outside of solid state drive 304.

In some implementations, solid state drive 304 (and/or host 302) It can be fixed on a system on a wafer (SOC, "system on chip"). In these implementations, the SOC can be fabricated using, for example, digital processing. The SOC can include an embedded processing system (e.g., an embedded CPU) that is separate from the solid state drive 304. The SOC may also include SRAM, system logic, cache memory, and cache controller for processing code and data. The code and data associated with the embedded processing system can be stored in cache devices 306a-306d and communicated to the SOC via, for example, an SOC interface. The SOC interface can be used by a translator to translate information flowing between the interface of the SOC and the internal bus structure. Control signals may flow from the SOC to flash devices 306a-306d, while instructions and data may flow from flash device 308 during the read operation. Instructions and data may also flow to flash devices 306a-306d, such as when the main memory within flash devices 306a-306d is in WRITE operation.

In some implementations, flash devices 306a-306d can be controlled by memory controller 330. Host 302 can communicate with flash devices 306a-306d via a memory interface 328 coupled to memory controller 330. In some implementations, the memory interface 328 can be a NAND flash interface.

The memory controller 330 can be coupled to the flash memory devices 306a-306d via a corresponding pin or terminal. In these implementations, the memory controller 330 can be implemented as an application specific integrated circuit (ASIC) or a system on chip (SOC). In addition, the signal CNFG can be transmitted through the fast. The circuits on flash devices 306a-306d are connected in series.

Status polling

As discussed above, the ready/busy output signal "R/B_" within a particular logic state can indicate whether the output is busy. For example: a low logic The ready/busy output signal "R/B_" in the status indicates the busy status on the output. In this example, the ready/busy output signal "R/B_" can be in a logic high state for some time period after the last rising edge of the write enable signal "WE_" (ie, it becomes a logic high indicating the ready state). status).

In general, a flash memory device has only one internal write charge pump. Therefore, writing data to the flash memory device (i.e., program editing the device) puts the memory device into a busy state so that data cannot be read from the memory device during a write operation. If a read operation is performed during the busy state, the logic "00" is returned. In this case, the busy state of a write operation can last for a few microseconds.

Similarly, initializing the erase operation of the flash memory device places the memory device in the busy state. During a erase operation, the device typically enters the busy state for 0.50-1.0 seconds. During this time, the device could not be accessed.

Failure to access the flash memory device during write and erase operations can result in systems operating the flash memory device operating slower than normal systems. Before the processor (such as the CPU 323) or the memory controller attempting to read the contents of the fast memory device can obtain the desired data, it must wait for the writing or erasing operation to complete.

Further, during this waiting period (eg, during a write or erase operation), the processor or memory controller 330 can detect whether the flash memory device is detected using the ready/busy output signal "R/B_" In a ready condition (for example, detecting if the flash memory device is ready for reading). If the flash memory device is busy, a busy state is passed back to the processor or memory controller 330. If the flash memory device is idle, an idle state is returned.

Although the aforementioned process of detecting a ready/busy condition of the flash memory device allows the processor or memory controller 330 to read (or write or immediately) after other operations (such as write or erase operations) are completed. Erasing) The contents of the flash memory device, which typically requires an additional pin to support this process.

In some implementations, to avoid the need for an additional pin, the processor or memory controller 330 can utilize a polling method that utilizes a read status command (eg, a status read command "70h"). Transmitted to the flash memory device to detect a ready or busy state of the flash memory device (eg, a read status of an instruction has been executed, a busy/waiting or pass/fail status of the read command, etc.) . In some implementations, a state register 336a-336d can be coupled to the flash memory device for storing a status signal indicating a write (or erase) operation execution state. The processor or memory controller 330 can perform a polling method by reading the status registers 336a-336d of the flash memory device. In some implementations, the flash memory device can accept a read status command even if the flash memory device is in a busy state, as shown in Table 3 below:

In some implementations, the wafer enable signal (CE_) can be set to one. Set data polling when the logic low state simultaneous write enable signal (WE_) is set to a logic high state. In operation, the host (e.g., host 302) or the memory controller (e.g., memory controller 330) can input a write/erase busy signal to initialize a write/erase operation. The write/erase busy signal can set the state registers 336a-336d of the flash memory device to logic "1". During this time, the CPU (e.g., CPU 323) can read the contents of the flash memory device while performing the write (or erase) operation.

Although the flash memory device accepts a read status command from the processor or memory controller 330, the processor or memory controller 330 continues to poll to detect write or erase completion, erase The flash memory device is either written or erased or erased, which can overload the flash memory device and the processor or memory controller 330 with the results of the polling.

Thus, in some implementations, the memory controller 330 can include a programmable edit timer 332, and the programmable edit timer can be used to determine the initial wait time prior to polling (ie, prior to transmitting a read status command). . In particular, the initial latency may define a period of time (i.e., during a read, program edit, or erase operation) that the memory controller 330 may wait before issuing a status check to the flash memory device. In some implementations, the initial wait time may be determined based on one or more factors, such as the "tR", "tPROG", and "tBERS" parameters.

In some implementations, at the end of the initial wait time, the memory controller 330 begins issuing one or more instructions (eg, read status command "70h") to check the status of the flash memory (eg, ready/busy) , pass/fail, etc.).

In some implementations, the memory controller can also include a second programmable edit timer 334 that can be used to control the spacing between each instruction (e.g., read status instructions). In some implementations, the appropriate value of the interval may be determined by the system firmware (eg, firmware 324), and such determination is based on one or more parameters associated with power and performance (eg, increased efficiency due to frequent polling, But it consumes more power).

In some implementations, the second programmable edit timer 324 can control a precise period between each state check or each read state command. The memory controller 330 can instantly detect the busy/ready condition of the flash memory by controlling the initial wait time and the interval of each issued read state time before issuing the read status command.

In addition, when a read status command is asserted, the power consumption associated with the memory controller 330 and the flash memory devices 306a-306d in the execution command may increase. Further, if a particular channel is used to transmit one or more READ state commands, the channel is blocked, preventing the next instruction from being transferred to other devices (or delaying execution of the next instruction). Thus, by controlling the interval at which each read status command is issued, the number of read status instructions can be adjusted in this manner. Adjusting the read status command may save power associated with memory controller 330 and flash memory devices 306a-306d, thus enhancing memory controller 330 and flash memory devices 306a-306d (or solid state disk drive 308). Power performance.

While the above description pertains to a read command and a read status command, it should be noted that those skilled in the art will appreciate that the foregoing description is also applicable to program operations. In these implementations, a program status command can be transmitted and adjusted in accordance with the polling process described above.

The fourth graph shows an example initial wait time for a ready/busy output signal "R/B_" for a flash memory device. As shown in the fourth picture, The time period "t3" (for example, in a logic "0" state) from the trailing edge to the rising edge of the ready/busy output signal "R/B_" may indicate the read time of the read data (eg, second A) "tR" in the figure, program editing time of the program editing data (for example, "tPRG" in the second B picture) or single block erasing time in the erased block data (for example, "tBERS" in the second C picture) ).

During the time period "t3", one or more read status commands 402, 404, and 406 may be transmitted to read the status of the flash memory device. In some implementations, the first read status instruction 402 can be transmitted after an initial wait time "t1". In essence, this initial latency controls when state polling occurs. After transmitting the first read status instruction 402, a second read status instruction 404 can be transmitted. The second read status command 404 can be transmitted after a first interval time "t2" has elapsed. After transmitting the second read status command 404, a third read status command 406 can be transmitted after the second time interval "t4". In some implementations, the first interval "t2" and the second interval "t4" may be the same. In other implementations, the first interval time "t2" is different from the second interval time "t4".

In the implementation shown above, the initial wait time "t1" and the first interval time "t2" and the second interval time "t4" may be supplied by the clock generator of the memory controller 330. Further, the initial waiting time "t1", the first interval time "t2", and the second interval time "t4" may be supplied from the internal clock of the flash memory device.

An advantage here is that using a read status instruction to poll and control when a status read instruction is issued includes avoiding incoherent reading of the internal register of the flash memory device. This prevents the error indication processor or memory controller 330 from being able to avoid reading the status of the old data. Said to be decisive. The processor or memory controller 330 can poll for program or erase status and correctly receive current and updated data using the scratchpad data stored in the direct read status registers 336a-336d.

The fifth diagram shows an example process 500 for issuing one or more read status instructions. Process 500 can be performed, for example, by solid state disk drive 300, solid state drive 304, or memory controller 330. However, other devices, systems, or combinations of systems may be used to perform process 500.

Process 500 begins by asserting a control signal to one or more memory devices (502). In some implementations, asserting a control signal can include asserting a read enable, write enable, or wafer enable (or wafer select) signal to one or more flash memory devices. In some implementations, the flash memory devices can include NAND type memory devices.

An initial wait time (504) can then be determined. In some implementations, the initial wait time can include a time period (eg, in a read, program edit, or etc.) that a memory controller (eg, memory controller 330) waits before issuing an instruction to the flash memory device. During the erase operation).

A first command (506) can be issued based on the initial wait time. In some implementations, the memory controller can issue a first instruction after the initial wait time. In these implementations, the first instruction can be a status check instruction (eg, a read status instruction or a program edit status check instruction).

In some implementations, determining a control signal can include asserting a read command to one or more memory devices. In these implementations, issuing a first instruction can include issuing a read status instruction based on the initial wait time.

In other implementations, determining a control signal can include asserting a program edit (or write) command to one or more memory devices. In these implementations, issuing a first instruction can include issuing a program edit status instruction based on the initial wait time.

Next, a first interval time associated with the first instruction is determined (508). The first interval time can be associated with an interval between two read status instructions. For example, a first read status instruction can be transmitted after the initial wait time. After transmitting the first read status instruction, a second read status command can be transmitted to the flash memory device. The second read status instruction may be transmitted after the first interval time elapses. After transmitting the second read status instruction, a third read status instruction can be transmitted after the second time interval.

A second command (510) can be issued based on the first interval. In some implementations, a second interval time associated with the second instruction can be generally determined as described above. In these implementations, the second interval may be determined with respect to the second instruction and a third instruction. According to the second interval time, the third instruction can be issued.

In some implementations, operations 502-510 can be performed in the order listed, concurrently (eg, the same or different programs or threads executed on one or more processors, substantially or non-serious), or in reverse order. Execute to achieve the desired result. In other implementations, operations 502-510 can be performed in the order shown. Additionally, the order in which operations are performed may depend, at least in part, on the entity performing process 500. Operations 502-510 are further performed by the same or different entities or systems.

Read cycle time and write cycle time

Traditional solid-state storage devices use multi-dimensional memory array systems to Increase performance and maximize capacity. However, traditional solid state systems generally do not utilize different types of solid state storage devices in the same system. For example, a conventional solid-state system cannot effectively utilize single-layer units and multi-level unit devices in the same system at the same time. According to the example, if you do not use the ready/busy output signal "R/B_" and only provide a single timer to the SLC and MLC, it may be difficult to find the best single timer for the SLC and MLC. Settings (eg because SLC and MLC have different optimal "tR", "tPROG" and "tBERS" cycles). As such, when selecting a small timer for optimal SLC performance, the timer may not be suitable for achieving maximum MLC performance (eg, in terms of power consumption). Similarly, if a large timer is used to achieve maximum MLC performance (eg, reduced power consumption), the SLC state may not be detected immediately, which results in low performance.

Although slower devices such as MLC devices are generally less expensive and can be used to meet traditional capacity requirements and reduce the overall cost of storage devices implementing MLC devices, MLC devices may not be able to interact with devices like SLC because of parameter conflicts. Class fast devices are used together on the same device. For example, SLC devices and MLC devices typically require different manufacturing requirements and specifications for data access (eg, different time parameters).

For example, please refer back to Figure 2A. To perform a read operation, the read enable signal (RE_) can be recognized and triggered between a logic "1" and a logic "0" for a predetermined number of cycles (for example, when The flash memory device operates in the data transfer area 204). A single cycle can be defined by the cycle of the read cycle time "tRC". In particular, the read cycle time "tRC" can define the read time during reading of data from the flash memory device.

In some implementations, the read cycle time "tRC" is approximately 50 ns (eg, for MLC devices). In particular, in the example of display, the read cycle time "tRC" may include a first timing period T1 and a second timing period T2. The first timing period T1 and the second timing period T2 may define a fast flash fetch time associated with each read cycle time "tRC". In some implementations, the first timing period T1 can span a period of 4*T, where T is 160 MHz or approximately 6.25 ns. In other words, the first timing period T1 is approximately 25 ns in length. In these implementations, the second timing period T2 also spans a period of 4*T or a length of approximately 25 ns. Then, the first timing period T1 of about 25 ns in length and the second timing period T2 of about 25 ns should produce a total read cycle time "tRC" of about 50 ns.

In other implementations, the read cycle time "tRC" is approximately 25 ns (eg, for SLC devices). For example, the first timing period T1 may span a period of 2*T, where T is 160 MHz or approximately 6.25 ns. In other words, the first timing period T1 is approximately 12.5 ns in length. In some implementations, the second timing period T2 also spans a period of 2*T or a length of approximately 12.5 ns. Then, the first timing period T1 of about 12.5 ns in length and the second timing period T2 of about 25 ns should produce a total read cycle time "tRC" of about 25 ns.

The read cycle time "tRC" does not need to be limited by the timing cycle shown above, but other read cycle time periods can also be considered. For example, depending on the specific design and application, the read cycle time "tRC" can be in the range of 20 ns.

In some implementations, the read cycle time "tRC" (and the write cycle time "tWC" discussed below) can be shorter (eg, faster than) and the read enable signal (or about the write cycle time "tWC" The write cycle associated with the enable signal. In these implementations, the solid state drive system The system 300 can provide an SOC internal clock to generate a read cycle time "tRC" and a write cycle time "tWC" as a NAND flash I/O interface signal according to the read enable signal and the write enable signal. For example, if the low time and high time associated with a NAND flash read enable signal are 10 ns and 15 ns, respectively, then the internal clock can be 200 Mhz (5 ns). Then, the value of the first timing period T1 can be programmed to allow 2T cycles (eg, 5 ns x 2 = 10 ns), and the value of the second timing period T2 can be programmed to allow 3T cycles (5 ns x 3 = 15 n).

Please refer to the second B diagram. To perform a data program editing operation, the write enable signal (WE_) can be recognized and triggered between logic "1" and logic "0" for a predetermined number of cycles (for example, when When the flash memory device is operating in the data transfer area 206). A single cycle can be defined by the period of the write cycle time "tWC". In particular, the write cycle time "tWC" can define the write time during which the flash memory device writes the program edit data.

In some implementations, the write cycle time "tWC" is approximately 50 ns (eg, for MLC devices). In particular, in the example of display, the read cycle time "tRC" may include a first timing period T1 and a second timing period T2. The first timing period T1 and the second timing period T2 may define a fast flash fetch time associated with each write cycle time "tWC". In some implementations, the first timing period T1 can span a period of 4*T, where T is 160 MHz or approximately 6.25 ns. In other words, the first timing period T1 is approximately 25 ns in length. In some implementations, the second timing period T2 also spans a period of 4*T or a length of approximately 25 ns. Then, the first timing period T1 of about 25 ns in length and the second timing period T2 of about 25 ns should produce a total write cycle time "tWC" of about 50 ns.

In other implementations, the write cycle time "tWC" is approximately 25 Ns (for example for SLC devices). For example, the first timing period T1 may span a period of 2*T, where T is 160 MHz or approximately 6.25 ns. In other words, the first timing period T1 is approximately 12.5 ns in length. In some implementations, the second timing period T2 also spans a period of 2*T or a length of approximately 12.5 ns. Then, the first timing period T1 of about 12.5 ns in length and the second timing period T2 of about 25 ns should produce a total write cycle time "tWC" of about 25 ns.

Of course, the write cycle time "tWC" need not be limited to the timing cycle shown above, but other write cycle time periods may also be considered. For example, depending on the specific design and application, the write cycle time "tWC" can be in the range of 45 ns.

In general, the read cycle time "tRC" and the write cycle time "tWC" can be used as timing parameters to determine the overall performance of the data transfer rate. By appropriately adjusting the read cycle time "tRC" and the write cycle time "tWC", the interface time associated with the flash memory device can be controlled so that the SLC and MLC devices can be mixed. According to an example, when a READ command is issued, the solid state drive system 300 can wait for an internal buffer to be ready after the "t4" period shown in FIG. Thereafter, data is removed from the internal buffer through the NAND interface to the solid state controller 308. The shift frequency is then specified by the "tRC" period of the read operation (or the "tWC" period of the program edit operation). As discussed above, the maximum capacity is given by "1/tRC" (eg 40MHz for "tRC" cycle = 25ns). In other words, the "tRC" period (or "tWC" period) is minimized to allow for increased bandwidth. Therefore, with the definition of two different timing parameters (eg one setting for the SLC device and the other setting for the MLC device, two opposites using the same logic (timing parameters) to control the timing interface for the SLC and MLC devices), so significant Improve efficiency.

According to other examples, a solid state disk drive can use a first flash memory device having a 25 ns read cycle time "tRC" and a 25 ns write cycle time "tWC" with a 25 ns read cycle time "tRC" and 45 ns. A second flash memory device having a cycle time "tWC", a third flash memory device having a 20 ns read cycle time "tRC" and a 20 ns write cycle time "tWC" and having a 50 ns read cycle Time "tRC" and a fourth flash memory device with a 50 ns write cycle time "tWC". In some implementations, a single block erase operation does not use cycle time because the data is not shifted into or out during a single erase operation.

The sixth graph shows an example process 600 for status polling based on a write cycle time and a read cycle time. Process 600 can be performed, for example, by solid state disk drive system 300, solid state drive 304, or memory controller 330. However, process 600 can also be performed using other devices, systems, or combinations of systems.

Process 600 begins by controlling a plurality of memory devices, the device comprising a first set of memory devices and a second set of memory devices (602). In some implementations, the first set of memory devices can comprise a single layer unit device and the second set of memory devices can comprise a multi-level unit device. In other implementations, the first set of memory devices can include multi-level cell devices, and the second set of memory devices can include single-layer cell devices.

Next, a first cycle time (604) can be determined. In some implementations, determining a first cycle time can include determining a first cycle time associated with a first set of memory devices. In these implementations, determining a first cycle time associated with the first set of memory devices can include determining a first timing parameter (eg, a "tRC" period of the second A-picture display) and a second timing parameter (eg, The second "B" shows the "tWC" period), The first timing parameter and the second timing parameter are both associated with a data transmission rate of the first set of memory devices (eg, single layer unit devices). In some implementations, the first cycle time can be a read cycle time associated with a read operation during which data from at least one of the memory devices can be read. In other implementations, the first cycle time can be a program edit cycle time associated with a program editing operation during which the data program can be edited into at least one of the memory devices.

Thereafter, a write command (606) is issued based on the first cycle time. In some implementations, the first instruction is issued to the first set of memory devices based on the first cycle time. For example, a write enable signal (WE_) having a rising and falling edge corresponding to the first cycle time can be issued. The write enable signal (WE_) can be triggered between logic "0" and logic "1" while a write operation has been performed.

After issuing a write command, a second cycle time (608) is determined. In some implementations, determining a second cycle time can include determining a second cycle time associated with a second set of memory devices. The second set of memory devices can be different than the first set of memory devices. For example, the first set of memory devices can comprise a single layer unit device and the second set of memory devices can comprise a multi-level unit device. In some implementations, determining a second cycle time can include determining a second cycle time that is independent of the first cycle time. For example, the "tRC" or "tWC" period associated with a single layer unit device can be determined separately from the period associated with the multi-level unit device. In some implementations, a "tRC" or "WC" cycle can be used to maximize the data transfer rate of a corresponding memory device.

In some implementations, a control signal (eg, a read enable signal, a write enable signal, or a wafer enable signal) can be asserted to one of the first or second set of memory devices for a predetermined number of cycles. In these realities The predetermined number of cycles may include a first cycle associated with the first cycle time, the first cycle including a first time period (eg, the first time shown in the second A picture and the second B picture) The sequence period "T1") and a second timing period (for example, the second timing period "T2" shown in the second A picture and the second B picture). In these implementations, the first timing cycle and the second timing cycle of the first cycle may include the same or different periods.

In some implementations, the predetermined number of cycles can include a second cycle associated with the second cycle time, the second cycle including a first timing cycle (eg, the second A map and the second B graph display The first timing period "T1") and a second timing period (for example, the second timing period "T2" shown in the second A picture and the second B picture). In these implementations, the first timing period and the second timing period of the second cycle may include the same or different periods.

In some implementations, a wait period (e.g., "tR" as shown in the second A-picture) may be determined. The wait period can be a wait time during which no instructions (e.g., read status or write status commands) are issued to the first set of memory devices or the second set of memory devices. Thereafter, the first instruction or the second instruction can be issued to its corresponding group.

After the second cycle time has been determined, a second command (610) is issued based on the second cycle time. For example, a read enable signal (RE_) having a rising and falling edge corresponding to the second cycle time can be issued. The read enable signal (RE_) can be triggered between logic "0" and logic "1" while a read operation has been performed.

In some implementations, operations 602-610 can be performed in the order listed, concurrently (eg, the same or different programs or threads executed on one or more processors, substantially or non-serious), or in reverse order. Execute to achieve the desired result. In other implementations, operations 602-610 can Execute in the order shown. Additionally, the order in which operations are performed may depend, at least in part, on the entity performing process 600. Operations 602-610 are further performed by the same or different entities or systems.

Example implementation of a hard disk drive

Figures 7 through 12 show many exemplary implementations of the illustrated systems and techniques. Referring now to Figure 7, the system and technology described can be implemented in a hard disk drive (HDD) 700. The illustrated systems and techniques can be implemented within signal processing and/or control circuitry, which is generally indicated at 702 on the seventh diagram. In some implementations, signal processing and/or control circuitry 702 and/or other circuitry (not shown) within HDD 700 can process data, perform encoding and/or encryption, perform computations, and output to or receive from a magnetic The data of the storage medium 704 is formatted.

The HDD 700 can be coupled to a host device such as a computer (not shown), a mobile computing device such as a personal digital assistant, a mobile phone, a media or MP3 player, etc., and other devices that communicate through one or more wired or wireless communication links 706. communication. The HDD 700 can be connected to a memory 708, such as a random access memory (RAM), low processing burden non-volatile memory such as flash memory, read only memory (ROM), and/or other suitable electronics. Data storage device.

Referring now to Figure 8, the system and technology described can be implemented in a digital versatile compact disc drive (DVD) 800. The illustrated systems and techniques can be implemented in signal processing and/or control circuitry, generally indicated at 802 in the eighth diagram, and/or implemented in a plurality of data storage devices 804 of the DVD player 800. Signal processing and/or control circuitry 802 and/or other circuitry (not shown) within DVD player 800 may process data, perform encoding and/or encryption, perform calculations, and/or read from Or data formatted to the optical storage medium 806. In some implementations, signal processing and/or control circuitry 802 and/or other circuitry (not shown) within DVD player 800 can also perform other functions, such as encoding and/or decoding, and any other accompanying DVD drive. Signal processing function.

The DVD player 800 can communicate with an output device (not shown) via one or more wired or wireless communication links 810, such as a computer, television or other device. The DVD player 800 can communicate with a plurality of data storage devices 804 that store data in a non-volatile manner. The mass data storage device 804 can include a hard disk drive (HDD). The HDD has the configuration shown in the seventh figure. The HDD can be a mini HDD containing one or more discs of approximately 1.8 inches in diameter. The DVD player 800 can be coupled to a memory 808, such as RAM, ROM, low processing burden non-volatile memory, such as flash memory and/or other suitable electronic data storage devices.

Referring now to the ninth diagram, the illustrated system and technology can be implemented in a high-definition television (HDTV) 900. The illustrated systems and techniques may be implemented in signal processing and/or control circuitry, generally indicated at 902 on the ninth diagram, WLAN interface 906, and/or within a plurality of data storage devices 910 of HDTV 900. The HDTV 900 receives an HDTV input signal in a wired or wireless format and produces an HDTV output signal of the display 904. In some implementations, signal processing and/or control circuitry 902 and/or other circuitry (not shown) within HDTV 900 can process data, perform encoding and/or encryption, perform computations, data formatting, and/or perform as needed. Any kind of HDTV processing.

The HDTV 900 can communicate with a large number of data storage devices 910 that store data in a non-volatile manner, such as optical and/or magnetic storage devices. At least one HDD may have the configuration shown in the seventh diagram, and/or At least one DVD may have the configuration shown in the eighth diagram. The HDD can be a mini HDD containing one or more discs of approximately 1.8 inches in diameter. The HDTV 900 can be coupled to a memory 908, such as RAM, ROM, low processing burden non-volatile memory, such as flash memory and/or other suitable electronic data storage devices. The HDTV 900 also supports connection to a WLAN via the WLAN network interface 906.

Referring now to the tenth diagram, the illustrated system and techniques can be implemented within a mobile telephone 1000 that includes a mobile antenna 1002. The illustrated systems and techniques can be implemented in signal processing and/or control circuitry, which is generally identified in FIG. 10 by 1004, a WLAN interface 1010, and/or within a plurality of data storage devices 1006 of the mobile telephone 1000. In some implementations, the mobile phone 1000 includes a microphone 1012, a sound output 1014 such as a speaker and/or a sound output socket, a display 1016, and/or an input device 1018, such as a keyboard, pointing device, voice actuation, and / or other input device. Signal processing and/or control circuitry 1004 and/or other circuitry (not shown) within mobile phone 1000 can process data, perform encoding and/or encryption, perform calculations, format data, and/or perform other mobile phone functions.

The mobile phone 1000 can communicate with a plurality of data storage devices 1006 that store data in a non-volatile manner, such as an optical and/or magnetic storage device, such as a hard disk drive HDD and/or a DVD. At least one HDD may have the configuration shown in the seventh diagram, and/or at least one DVD may have the configuration shown in the eighth diagram. The HDD can be a mini HDD containing one or more discs of approximately 1.8 inches in diameter. Mobile phone 1000 can be coupled to memory 1008, such as RAM, ROM, low processing burden non-volatile memory, such as flash memory and/or other suitable electronic data storage devices. Mobile Phone 1000 also supports a WLAN network The interface 1010 is connected to a WLAN.

Referring now to Figure 11, the system and technology illustrated can be implemented within the set-top box 1100. The illustrated systems and techniques may be implemented in signal processing and/or control circuitry, generally indicated at 1102 in Figure 10, a WLAN interface 1108, and/or within a plurality of data storage devices 1104 of the set-top box 1100. The set-top box 1100 receives signals from a source 1112, such as a broadcast source, and outputs standard and/or high-fidelity sound/video signals suitable for a display 1110, such as a television and/or monitor and/or other video and / or sound output device. Signal processing and/or control circuitry 1102 and/or other circuitry (not shown) within set-top box 1100 can process data, perform encoding and/or encryption, perform calculations, format data, and/or execute any other set-top box Features.

The set-top box 1100 can communicate with a plurality of data storage devices 1104 that store data in a non-volatile manner. The mass data storage device 1104 can include optical and/or magnetic storage devices such as a hard disk drive HDD and/or a DVD. At least one HDD may have the configuration shown in the seventh diagram, and/or at least one DVD player may have the configuration shown in the eighth diagram. The HDD can be a mini HDD containing one or more discs of approximately 1.8 inches in diameter. The set-top box 1100 can be connected to a memory 1106, such as a RAM, ROM, low-processing burden non-volatile memory, such as a flash memory and/or other suitable electronic data storage device. The set-top box 1100 also supports connection to a WLAN through a WLAN network interface 1108.

Referring now to the twelfth diagram, the illustrated system and techniques can be implemented within the media player 1200. The illustrated systems and techniques can be implemented in signal processing and/or control circuitry, generally indicated at 1202 in FIG. 12, a WLAN interface 1208, and/or within a plurality of data storage devices 1204 of a media player 1200. In some implementations, the media Player 1200 includes a display 1212 and/or a user input 1214, such as a keyboard, touch pad, and the like. In some implementations, the media player 1200 can utilize a graphical user interface (GUI), which is typically utilized by the display 1212 and/or user input 1214 to function menus, drop-down menus, icons, and / or pointing interface. The media player 1200 further includes a sound output 1210, such as a speaker and/or a sound output socket. Signal processing and/or control circuitry 1202 and/or other circuitry (not shown) within media player 1200 can process data, perform encoding and/or encryption, perform calculations, format data, and/or execute any other media player. Features.

The media player 1200 can communicate with a plurality of data storage devices 1204 that store data, such as compressed sound and/or video content, in a non-volatile manner. In some implementations, the compressed sound files include files that conform to the MP3 format or other suitable compressed sound and/or video format. The mass data storage device can include optical and/or magnetic storage devices such as a hard disk drive HDD and/or a DVD. At least one HDD may have the configuration shown in the seventh diagram, and/or at least one DVD player may have the configuration shown in the eighth diagram. The HDD can be a mini HDD containing one or more discs of approximately 1.8 inches in diameter. Media player 1200 can be coupled to memory 1206, such as RAM, ROM, low processing burden non-volatile memory, such as flash memory and/or other suitable electronic data storage devices. The media player 1200 also supports connection to a WLAN via a WLAN network interface 1208. Other implementations are still considered plus the description above.

Some specific embodiments have been described in detail above, and many modifications are possible. The claimed claims include the functional operations described in this manual. Can be implemented in electronic circuits, computer hardware, firmware, software, or a combination of these, such as the structural devices disclosed in this specification and their structural equivalents, including potentially operable to cause one or more data processing devices A program that performs the operations described (such as a program encoded in a computer readable medium, which may be a memory device, a machine readable storage substrate or other entity, machine readable medium, or one or more of these). More combinations).

"Data Processing Equipment" encompasses all equipment, devices and machines that process data, including examples of programmable editing processors, computers or multi-processors or computers. In addition to the hardware, the device may include a code for establishing an execution environment for the computer program, that is, a program that constitutes a processor firmware, a communication protocol stack, a database management system, an operating system, or a combination of one or more of these. code.

A program (known as a computer program, software, software application, description file or code) can be written in any programming language, including a compiled or interpreted language or a statement or programming language, and can be deployed in any form. , including becoming a stand-alone program or becoming a module, component, sub-routine or other unit suitable for use in a computing environment. A program does not need to correspond to a file in a file system. A program can be stored in a part of a file (such as one or more description files stored in a markup language file) that holds other programs or materials, in a single file that is specific to the program, or in multiple collaborative files (for example, storage) One or more modules, subprograms or partial code files). A program can be deployed on a computer or on multiple computers that are geographically dispersed or interconnected in multiple locations.

The description contains many specifics, and should not be construed as limiting the scope of the invention. Specific features within the scope of individual embodiments within this specification Colors can also be implemented in a single embodiment combination. Conversely, many of the features that are described in the context of a single specific embodiment can also be practiced in the various combinations of the various embodiments. Moreover, while features have been described above in a particular combination and are claimed herein, one or more features from the claimed combination may be combined in some instances and the claimed combination may be directed to a sub-combination or sub-combination.

Similarly, although the operation is illustrated in a particular order, it should not be seen as requiring that the operations be performed in the particular order or sequence shown, or that all operations described are performed, and the desired result is achieved. . Multiple jobs and simultaneous processing have advantages in certain environments. Moreover, many of the system components in the above-described embodiments are not considered to be separate in all embodiments.

100‧‧‧ memory array

102‧‧‧page

104‧‧‧Parts

Section 106‧‧‧

108‧‧8 bit depth

110‧‧‧ single section

112‧‧‧ single page

114‧‧‧Part I

116‧‧‧Part II

202‧‧‧Area

204‧‧‧Area

206‧‧‧Area

208‧‧‧ area

210‧‧‧ Area

212‧‧‧Area

214‧‧‧Area

300‧‧‧Solid Disk System

302‧‧‧Host

303‧‧‧ busbar

304‧‧‧Solid Disk Drive

306a-306d‧‧‧flash memory device

308‧‧‧Solid Controller

310‧‧‧Host interface

312‧‧‧Error Check Code Module

314‧‧‧Interface logic

316‧‧‧Sequencer

318‧‧‧Formatter

323‧‧‧Central Processor Unit

324‧‧‧ embedded firmware

326a-326d‧‧‧ channel

328‧‧‧ memory interface

330‧‧‧ memory controller

332‧‧‧Programmable editing timer

334‧‧‧Second programmable editing timer

336a-336d‧‧‧ state register

402‧‧‧Read status command

404‧‧‧Read status command

406‧‧‧Read status command

500‧‧‧Process

600‧‧ ‧ treatment

700‧‧‧ Hard disk drive

702‧‧‧Signal processing and / or control circuit

704‧‧‧Magnetic storage media

706‧‧‧Wired or wireless communication link

708‧‧‧ memory

800‧‧‧Digital versatile CD player

802‧‧‧Signal processing and / or control circuits

804‧‧‧Many data storage devices

806‧‧‧Optical storage media

808‧‧‧ memory

810‧‧‧Wired or wireless communication link

900‧‧‧High-definition television

902‧‧‧Signal processing and / or control circuits

904‧‧‧ display

906‧‧‧WLAN interface

908‧‧‧ memory

910‧‧‧Many data storage devices

1000‧‧‧Mobile Phone

1002‧‧‧Mobile antenna

1004‧‧‧Signal processing and / or control circuits

1006‧‧‧Many data storage devices

1008‧‧‧ memory

1010‧‧‧WLAN interface

1012‧‧‧Microphone

1014‧‧‧Sound output

1016‧‧‧ display

1018‧‧‧ Input device

1100‧‧‧Set-top box

1102‧‧‧Signal processing and / or control circuits

1104‧‧‧Many data storage devices

1106‧‧‧ memory

1108‧‧‧WLAN interface

1110‧‧‧ display

1112‧‧‧Source

1200‧‧‧Media Player

1202‧‧‧Signal processing and / or control circuits

1204‧‧‧A large number of data storage devices

1206‧‧‧ memory

1208‧‧‧WLAN interface

1210‧‧‧Sound output

1212‧‧‧ display

1214‧‧‧User input

The first figure shows a block diagram of an example memory array.

Figure 2A shows a timing diagram associated with each pin within an exemplary NAND flash interface during a data read operation.

The second B diagram shows an example timing diagram associated with each pin within a NAND flash interface during a data program editing operation.

The second C diagram shows an example timing diagram associated with each pin within a NAND flash interface during a single erase operation.

The third figure shows an example solid state disk drive.

The fourth graph shows an example initial wait time for a ready/busy output signal "R/B_" for a flash memory device.

The fifth diagram shows an example process for issuing one or more read status instructions.

The sixth graph shows an example process for status polling based on a write cycle time and a read cycle time.

Figures 7 through 12 show many example electronic systems implementing a hard disk drive system.

300‧‧‧Solid Disk System

302‧‧‧Host

303‧‧‧ busbar

304‧‧‧Solid Disk Drive

306a-306d‧‧‧flash memory device

308‧‧‧Solid Controller

310‧‧‧Host interface

312‧‧‧Error Check Code Module

314‧‧‧Interface logic

316‧‧‧Sequencer

318‧‧‧Formatter

323‧‧‧Central Processor Unit

324‧‧‧ embedded firmware

326a-326d‧‧‧ channel

328‧‧‧ memory interface

330‧‧‧ memory controller

332‧‧‧Programmable editing timer

334‧‧‧Second programmable editing timer

336a-336d‧‧‧ state register

Claims (14)

A method of flash memory control, comprising: controlling a plurality of memory devices, the device comprising a first set of memory devices and a second set of memory devices; determining a one associated with the first set of memory devices a first period; issuing a first command to the first group of memory devices according to the first period; determining a second period associated with the second group of memory devices; and issuing a second according to the second period Commanding to the second set of memory devices. The method of claim 1, wherein determining a second period associated with the second set of memory devices comprises determining the second period unrelated to the first period. The method of claim 1, wherein determining a first period associated with the first set of memory devices comprises: determining a first timing parameter and a second timing parameter, the first timing parameter and The second timing parameter is associated with a data transmission rate of the first set of memory devices. The method of claim 1, wherein determining a second period associated with the second set of memory devices comprises: determining a first timing parameter and a second timing parameter, the first timing parameter and The second timing parameter is associated with a data transmission rate of the second set of memory devices. The method of claim 1, wherein controlling the plurality of memory devices comprises: Determining a control signal to the first set of memory devices for a predetermined number of cycles, comprising a first cycle associated with the first cycle, the first cycle comprising a first timing cycle and a second timing cycle. The method of claim 5, wherein the first timing cycle of the first cycle and the second timing cycle comprise the same period. The method of claim 5, wherein the first timing cycle of the first cycle and the second timing cycle comprise a different period. The method of claim 1, wherein controlling the plurality of memory devices comprises: determining a control signal to the second group of memory devices for a predetermined number of cycles, including a first phase associated with the second cycle The second cycle includes a first timing cycle and a second timing cycle. The method of claim 8, wherein the first timing period of the second loop and the second timing period comprise the same period. The method of claim 8, wherein the first timing period of the second loop and the second timing period comprise a different period. The method of claim 1, wherein determining a first period comprises determining a read period during reading of data from at least one of the memory devices, or editing the data program into at least one of the memory devices A program editing cycle during the period. The method of claim 1, wherein controlling the plurality of memory devices comprises determining a waiting period. The method of claim 12, wherein issuing a first instruction comprises issuing the first instruction after the waiting period. For example, the method of claim 12, wherein a second finger is issued The second instruction is issued after the waiting period is included.