TWI597807B - Chipless package structure - Google Patents

Description

Chipless package structure

The invention relates to the field of semiconductor chip packaging, in particular to a substrate-free chip package structure, which can be applied to a Fan-Out Wafer-Level Chip Scale Package (FOWLCSP) and a suitable application. Fan-Out Panel-Level Chip Scale Package (FOPLCSP).

In a conventional chip package structure, a substrate is used to carry a wafer, and an integrated circuit of the wafer is electrically conducted by using a wiring structure of the substrate and a plated through hole structure. However, in the advanced substrateless package structure, the substrate is omitted, and the fan-out line for external electrical connection of the wafer is provided by the re-arranged wiring layer that has conventionally formed the surface of the wafer. The reconfigured circuit layer is not only formed on the wafer, but also the line is elongated and fanned out to other packaging materials. The fan-out line is easily broken by the thermal stress caused by the mismatch of thermal expansion coefficients between different materials. In the conventional fan-out wafer level wafer size package structure, the line breakage problem of the reconfigured circuit layer is an urgent problem to be solved.

In order to solve the above problems, the main object of the present invention is to provide a substrate-free chip package structure for avoiding fan-out lines on the sealant. A breakage problem has occurred.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The present invention discloses a substrateless wafer package structure comprising a wafer, a gel, a reconfigurable circuit layer, and at least one line stiffening layer. The wafer has an active surface and a plurality of sides on the periphery of the active surface. The encapsulation system covers the sides of the wafer, the encapsulation system having a surface formed around the active surface and coplanar with the active surface. The reconfigurable circuit layer is formed on the active surface of the wafer and the surface of the encapsulant, and the reconfigurable circuit layer includes at least one line passing through an interface between the active surface and the encapsulant. The line stiffening layer is formed on a section of the at least one line, wherein the section is located at the interface between the active surface and the encapsulant.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the aforementioned wafer package construction, the surface of the encapsulant may be annular around the active surface of the wafer.

In the foregoing chip package construction, the thickness of the line stiffening layer may be not less than fifty percent of the line.

In the foregoing chip package structure, the line stiffening layer may be partially superposed on a plating circuit, and one of the bottom layers of the line stiffening layer is electrically conductively attached to the line, and both ends of the line stiffening layer are open circuit structures.

In the foregoing chip package structure, the conductivity of the line stiffening layer may be not less than the conductivity of the reconfigured wiring layer.

In the foregoing chip package structure, a plurality of first bonding terminals and at least one second bonding terminal may be further included, and the first bonding terminals may be located on the active surface of the chip and electrically connected to the reconfigurable circuit layer. The second bonding terminal can be located on the surface of the encapsulant and electrically connected to the line of the reconfigured wiring layer.

In the foregoing chip package structure, the length of the line stiffening layer may be smaller than a gap between the second bonding terminal and the nearest first bonding terminals, so that the line stiffening layer is not directly connected to the second bonding terminal and the foregoing The first joint terminals that are closest to each other.

In the foregoing chip package structure, the first bonding terminals and the second bonding terminals may include a plurality of solder balls.

In the foregoing wafer package construction, the sealant thickness of the sealant can be identical to the wafer thickness of the wafer to be exposed on the back side of the wafer to achieve an ultra-thin package of wafer thickness grade.

In the foregoing chip package structure, a protective layer is further disposed to cover the active surface and the surface of the sealant, and the protective layer has a thickness sufficient to seal the reconfigurable circuit layer and the line stiffening layer to avoid The line is exposed.

In the foregoing chip package structure, the circuit can directly contact the active surface and directly contact the surface of the encapsulant, thereby saving the number of layers of the inner dielectric layer.

By the above technical means, the present invention can increase the line strength of the reconfigurable line in the substrate-free chip package structure to prevent the line from being broken in the stress sensitive area.

S‧‧‧ gap

100‧‧‧ Chip package construction

110‧‧‧ wafer

111‧‧‧Active surface

112‧‧‧ side

113‧‧‧Back

114‧‧‧ solder pads

120‧‧‧ Sealant

121‧‧‧ surface

122‧‧‧ interface

130‧‧‧Reconfigure the circuit layer

131‧‧‧ lines

140‧‧‧Line stiffening layer

141‧‧‧ bottom

150‧‧‧First joint terminal

160‧‧‧Second joint terminal

170‧‧‧Protective layer

1 is a cross-sectional view showing a substrate-free package structure in accordance with an embodiment of the present invention.

2 is a partial enlarged view of the substrate-less chip package structure in accordance with an embodiment of the present invention.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

In accordance with an embodiment of the present invention, a substrateless package structure 100 is illustrated in a cross-sectional view of FIG. 1 and a partial enlarged view of FIG. A substrateless wafer package structure 100 includes a wafer 110, a glue body 120, a reconfiguration circuit layer 130, and at least one line stiffening layer 140.

Referring to FIGS. 1 and 2, the wafer 110 has an active surface 111 and a plurality of sides 112 on the periphery of the active surface 111. The active surface 111 is provided with a plurality of pads 114. The body material of the wafer 110 may be bismuth (Si) with a small coefficient of thermal expansion. An integrated circuit can be fabricated on the active surface 111 (not shown) Draw), and the pads 114 are external connection electrodes of the integrated circuit.

The encapsulant 120 covers the side surfaces 112 of the wafer 110. The encapsulant 120 has a surface 121 formed around the active surface 111 and coplanar with the active surface 111. The surface 121 of the encapsulant 120 can be annularly surrounding the active surface 111 of the wafer 110. The encapsulant 120 may specifically be an Epoxy Molding Compound (EMC) having a larger coefficient of thermal expansion than the wafer 110. Thermal stress may be generated between the active surface 111 and the sealant 120 during the heat treatment. In this embodiment, the encapsulation thickness of the encapsulant 120 can be consistent with the wafer thickness of the wafer 110 to be exposed on the back side 113 of the wafer 110 to achieve the thinnest package.

The reconfigurable circuit layer 130 is formed on the active surface 111 of the wafer 110 and the surface 121 of the encapsulant 120. The reconfigurable circuit layer 130 includes at least one line 131 passing through the active surface 111 and the The interface 122 between the sealants 120. Therefore, the line 131 is simultaneously formed on the active surface 111 and on the sealant 120 and continuously passes through the different materials of the wafer 110 and the sealant 120. The line 131 is preferably directly attached to the active surface 111 and directly contacts the surface 121 of the encapsulant 120, thereby saving the number of layers of the inner dielectric layer.

The line stiffening layer 140 is formed on a section of the at least one line 131, wherein the section is located on the interface 122 between the active surface 111 and the encapsulant 120. Preferably, the thickness of the line stiffening layer 140 is not less than fifty percent of the line 131. The material of the line stiffening layer 140 can be the same as the material of the main body of the line 131, such as copper. The formation of the stiffening layer 140 can be formed by two The secondary plating is formed in a specific partial region, that is, by additional partial plating. Preferably, the conductivity of the line stiffening layer 140 is not less than the conductivity of the reconfiguration circuit layer 130.

More specifically, the line stiffening layer 140 can be partially superposed on a plating circuit. One of the bottom surfaces 141 of the line stiffening layer 140 is electrically conductively attached to the line 131. The two ends of the line stiffening layer 140 are open. structure.

In addition, the chip package structure 100 can further include a plurality of first bonding terminals 150 and at least one second bonding terminal 160. The first bonding terminals 150 can be located on the active surface 111 of the wafer 110 and electrically connected to The reconfigured circuit layer 130, the second bonding terminal 160 can be located on the surface 121 of the encapsulant 120 and electrically connected to the line 131 of the reconfigured wiring layer 130. The first bonding terminals 150 and the second bonding terminals 160 may include a plurality of solder balls.

In a specific structure, the length of the line stiffening layer 140 may be smaller than the gap S between the second bonding terminal 160 and the first adjacent bonding terminals 150, so that the line stiffening layer 140 is not directly connected to the second The bonding terminal 160 is adjacent to the first bonding terminals 150 that are closest to the foregoing, thereby facilitating formation of the line stiffening layer 140 using an additional partial plating method.

In this embodiment, the chip package structure 100 can further include a protective layer 170 covering the central surface of the reconfigurable circuit layer 130, and the surface 112 of the encapsulant 120 is exposed. In the peripheral region of one of the reconfiguration circuit layers 130. Moreover, the protective layer 170 has a thickness sufficient to seal the re-wiring circuit layer 130 and the line stiffening layer 140 to prevent the line from being exposed. This protection The material of the layer 170 may be Polyimide (PI).

Therefore, according to the line stiffening layer 140 and the combination thereof, the wafer 110 and the sealant 120 have a thermal expansion coefficient mismatch (CTE mismatch), and the resulting stress does not cause the line. The break of 131. As shown in Fig. 2, under the action of thermal stress, even if the line 131 is locally cracked, the line stiffening layer 140 has an electrically conductive property, so that no electrical short circuit of the line 131 is caused.

The above disclosure is only the embodiment of the present invention, and the scope of the present invention is not limited thereto, and thus equivalent changes made in the claims of the present invention are still within the scope of the present invention.

S‧‧‧ gap

100‧‧‧ Chip package construction

110‧‧‧ wafer

111‧‧‧Active surface

112‧‧‧ side

113‧‧‧Back

114‧‧‧ solder pads

120‧‧‧ Sealant

121‧‧‧ surface

122‧‧‧ interface

130‧‧‧Reconfigure the circuit layer

131‧‧‧ lines

140‧‧‧Line stiffening layer

150‧‧‧First joint terminal

160‧‧‧Second joint terminal

170‧‧‧Protective layer

Claims (9)

A substrate-free chip package structure comprising: a wafer having an active surface and a plurality of sides on the periphery of the active surface; a gel covering the sides of the wafer, the encapsulation system having a surface Forming on the periphery of the active surface and coplanar with the active surface; a reconfigurable circuit layer formed on the active surface of the wafer and the surface of the encapsulant, the reconfigurable circuit layer comprising at least a line passing through an interface between the active surface and the encapsulant; at least one line stiffening layer is formed on one of the at least one line, wherein the section is located on the active surface and the encapsulant And the plurality of first bonding terminals and the at least one second bonding terminal, the first bonding terminals being located on the active surface of the chip and electrically connected to the reconfigurable circuit layer, the second a bonding terminal is disposed on the surface of the encapsulant and electrically connected to the circuit of the reconfigured wiring layer, wherein the length of the line stiffening layer is less than the first bonding of the second bonding terminal to the nearest one The spacer, so that the wiring layer is not directly connected to stiffening the plurality of first connecting terminals and the second connecting terminals of the nearest neighbor. The non-substrate wafer package structure of claim 1, wherein the surface of the encapsulant is annularly surrounding the active surface of the wafer. The substrate-free chip package structure according to claim 1, wherein The thickness of the stiffening layer of the line is not less than fifty percent of the line. The non-substrate wafer package structure of claim 1, wherein the line stiffening layer is partially superposed on a plating circuit, and one of the bottom layers of the stiffening layer is electrically attached to the line, the line Both ends of the stiffening layer are open circuit structures. The substrate-less chip package structure of claim 4, wherein the conductivity of the line stiffening layer is not less than the conductivity of the reconfiguration circuit layer. The substrate-less chip package structure of claim 1, wherein the first bonding terminals and the second bonding terminals comprise a plurality of solder balls. The substrate-free chip package structure of claim 1, wherein the sealant has a mold thickness that is identical to the wafer thickness of the wafer to be exposed on the back side of the wafer. The non-substrate wafer package structure of claim 1, further comprising a protective layer covering the active surface and the surface of the encapsulant and sealing the reconfigurable circuit layer and the line stiffening layer. The substrate-less chip package structure according to any one of claims 1 to 8, wherein the circuit is directly attached to the active surface and directly contacts the surface of the sealant.