TWI597863B - Light-emitting element and method of manufacturing same - Google Patents
Light-emitting element and method of manufacturing same Download PDFInfo
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- TWI597863B TWI597863B TW102138216A TW102138216A TWI597863B TW I597863 B TWI597863 B TW I597863B TW 102138216 A TW102138216 A TW 102138216A TW 102138216 A TW102138216 A TW 102138216A TW I597863 B TWI597863 B TW I597863B
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/81—Bodies
- H10H20/819—Bodies characterised by their shape, e.g. curved or truncated substrates
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
- H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/01—Manufacture or treatment
- H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
- H10H20/018—Bonding of wafers
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/882—Scattering means
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Description
本發明係關於一種發光元件及其製造方法；特別是關於一種具有孔洞之發光元件及其製造方法。 The present invention relates to a light-emitting element and a method of manufacturing the same; and more particularly to a light-emitting element having a hole and a method of manufacturing the same.
發光二極體(Light-Emitting Diode，LED)具有耗能低、低發熱、操作壽命長、防震、體積小、以及反應速度快等良好特性，因此適用於各種照明及顯示用途。由於發光二極體的發光效率為其內部量子效率(internal quantum efficiency)及光取出效率(extraction efficiency)的乘積，故在提昇發光二極體的亮度時，除了可從內部量子效率著手外，改善發光二極體的光取出效率亦是另一個提昇發光二極體亮度的方向。 Light-Emitting Diode (LED) has good characteristics such as low energy consumption, low heat generation, long operating life, shock resistance, small size, and fast response. It is suitable for various lighting and display applications. Since the luminous efficiency of the light-emitting diode is the product of the internal quantum efficiency and the extraction efficiency, when the brightness of the light-emitting diode is increased, the improvement can be improved from the internal quantum efficiency. The light extraction efficiency of the light-emitting diode is also another direction for increasing the brightness of the light-emitting diode.
本發明係揭露一種發光元件及其製造方法。本發明揭露一發光元件，包含：一發光疊層；以及一半導體層具有一第一表面鄰接上述發光疊層、一第二表面相對於上述第一表面，以及一孔洞，上述孔洞包含一底部接近上述第一表面及一開口位於上述第二表面，其中上述孔洞之底部具有一寬度大於上述開口之寬度。本發明揭露 一發光元件之製造方法，包含：提供一基板；形成一發光疊層於上述基板上；形成一半導體層於上述發光疊層上，上述半導體層具有一第一表面鄰接上述發光疊層以及一第二表面相對於上述第一表面；以及形成一孔洞於上述半導體層中，上述孔洞包含一底部接近上述第一表面及一開口位於上述第二表面，其中上述孔洞之底部具有一寬度大於上述開口之寬度。 The invention discloses a light-emitting element and a method of manufacturing the same. The invention discloses a light-emitting element comprising: a light-emitting layer; and a semiconductor layer having a first surface adjacent to the light-emitting layer, a second surface opposite to the first surface, and a hole, the hole comprising a bottom The first surface and an opening are located on the second surface, wherein the bottom of the hole has a width greater than a width of the opening. The invention discloses A method of manufacturing a light-emitting device, comprising: providing a substrate; forming a light-emitting layer on the substrate; forming a semiconductor layer on the light-emitting layer, the semiconductor layer having a first surface adjacent to the light-emitting layer and a first The second surface is opposite to the first surface; and a hole is formed in the semiconductor layer, the hole includes a bottom portion adjacent to the first surface and an opening at the second surface, wherein a bottom of the hole has a width greater than the opening width.
101‧‧‧基板 101‧‧‧Substrate
102‧‧‧發光疊層 102‧‧‧Lighting laminate
102a‧‧‧第一電性半導體層 102a‧‧‧First electrical semiconductor layer
102b‧‧‧發光層 102b‧‧‧Lighting layer
102c‧‧‧第二電性半導體層 102c‧‧‧Second electrical semiconductor layer
103‧‧‧半導體層 103‧‧‧Semiconductor layer
103a‧‧‧第一半導體層 103a‧‧‧First semiconductor layer
103b‧‧‧第二半導體層 103b‧‧‧Second semiconductor layer
103a1‧‧‧第一含鋁層 103a1‧‧‧First aluminum layer
103a2‧‧‧第二含鋁層 103a2‧‧‧Second aluminum-containing layer
103a3‧‧‧第三含鋁層 103a3‧‧‧The third aluminum-containing layer
103a1ce‧‧‧底部凹洞 103a1ce‧‧‧ bottom recess
103a2o‧‧‧穿透部 103a2o‧‧‧ penetration
103bo‧‧‧開口孔洞 103bo‧‧‧Open hole
103boe‧‧‧開口 103boe‧‧‧ openings
103v‧‧‧孔洞 103v‧‧‧ hole
103v’‧‧‧孔洞 103v’‧‧‧ hole
104‧‧‧透明導電層 104‧‧‧Transparent conductive layer
105‧‧‧金屬層 105‧‧‧metal layer
106‧‧‧接合結構 106‧‧‧ joint structure
106a1‧‧‧第一接合層 106a1‧‧‧First joint layer
106a2‧‧‧第二接合層 106a2‧‧‧Second joint layer
107‧‧‧永久基板 107‧‧‧Permanent substrate
108‧‧‧保護層 108‧‧‧Protective layer
109‧‧‧電極 109‧‧‧Electrode
d1‧‧‧開口孔洞103bo之孔洞直徑 D1‧‧‧ hole diameter of the opening hole 103bo
d2‧‧‧穿透部103a2o之孔洞直徑 D2‧‧‧ hole diameter of the penetration part 103a2o
d3‧‧‧凹洞103a1ce之孔洞直徑 D3‧‧‧ hole diameter of the hole 103a1ce
L‧‧‧光線 L‧‧‧Light
S1‧‧‧第一表面 S1‧‧‧ first surface
S2‧‧‧第二表面 S2‧‧‧ second surface
第1(a)圖至第1(g)圖所示為本發明第一實施例之發光元件及其製造方法。 Fig. 1(a) to Fig. 1(g) show a light-emitting element according to a first embodiment of the present invention and a method of manufacturing the same.
第2圖用以說明本發明第二實施例之發光元件及其製造方法。 Fig. 2 is a view for explaining a light-emitting element and a method of manufacturing the same according to a second embodiment of the present invention.
第3圖用以說明本發明第三實施例之發光元件及其製造方法。 Fig. 3 is a view for explaining a light-emitting element and a method of manufacturing the same according to a third embodiment of the present invention.
圖1為本發明第一實施例之發光元件及其製造方法，如圖1(a)所示，首先提供一基板101，並於其上形成一發光疊層102，發光疊層102包括一半導體疊層，由下而上依序包括一第一電性半導體層102a；一發光層102b位於第一電性半導體層102a之上；以及一第二電性半導體層102c位於發光層102b之上。第一電性半導體層102a和第二電性半導體層102c電性相異，例如第一電性半導體層102a是n型半導體層，而第二電性半導體層102c是p型半導體層。 第一電性半導體層102a、發光層102b、及第二電性半導體層102c為III-V族材料所形成，例如為磷化鋁鎵銦(AlGaInP)系列材料。 1 is a light emitting device according to a first embodiment of the present invention, and a method of fabricating the same. As shown in FIG. 1(a), a substrate 101 is first provided, and a light emitting layer 102 is formed thereon. The light emitting layer 102 includes a semiconductor. The laminate includes a first electrical semiconductor layer 102a from bottom to top, a light emitting layer 102b over the first electrical semiconductor layer 102a, and a second electrical semiconductor layer 102c over the light emitting layer 102b. The first electrical semiconductor layer 102a and the second electrical semiconductor layer 102c are electrically different, for example, the first electrical semiconductor layer 102a is an n-type semiconductor layer, and the second electrical semiconductor layer 102c is a p-type semiconductor layer. The first electrical semiconductor layer 102a, the light-emitting layer 102b, and the second electrical semiconductor layer 102c are formed of a III-V material, such as an aluminum gallium indium phosphide (AlGaInP) series material.
接著，如圖1(b)所示，形成一半導體層103於發光疊層102之上。半導體層103包含一含有鋁之半導體層，例如包含砷化鋁(AlAs)及/或砷化鋁鎵(AlGaAs)，其厚度約為1μm至10μm。半導體層103具有兩相對之表面，第一表面S1鄰接發光疊層102，而第二表面S2則相對於第一表面S1。在本實施例中，半導體層103包含一第一半導體層103a於發光疊層102上及一第二半導體層103b於第一半導體層103a上，且第一半導體層103a之鋁含量大於第二半導體層103b之鋁含量。例如第一半導體層103a包含砷化鋁(AlAs)及/或砷化鋁鎵(AlxGa1-xAs)，在一實施例中，0.5≦x<1，厚度約為3μm；而第二半導體層103b不含鋁，例如包含磷化鎵(GaP)，厚度約為50nm。此外，在本實施例中，第一半導體層103a為兩層結構，即第一半導體層103a包含第一含鋁層103a1及第二含鋁層103a2，兩層中鋁含量不同。在本實施例中，第一含鋁層103a1之鋁含量高於第二含鋁層103a2之鋁含量，例如第一含鋁層103a1為砷化鋁(AlAs)，第二含鋁層103a2為砷化鋁鎵(AlyGa1-yAs，其中0.5≦y<1)。第一含鋁層103a1及第二含鋁層103a2之厚度各約為1.5μm。 Next, as shown in FIG. 1(b), a semiconductor layer 103 is formed over the light-emitting layer stack 102. The semiconductor layer 103 comprises a semiconductor layer containing aluminum, for example, comprising aluminum arsenide (AlAs) and/or aluminum gallium arsenide (AlGaAs) having a thickness of about 1 μm to 10 μm. The semiconductor layer 103 has two opposite surfaces, the first surface S1 adjoins the light emitting stack 102, and the second surface S2 is opposite to the first surface S1. In this embodiment, the semiconductor layer 103 includes a first semiconductor layer 103a on the light emitting layer 102 and a second semiconductor layer 103b on the first semiconductor layer 103a, and the aluminum content of the first semiconductor layer 103a is greater than that of the second semiconductor. The aluminum content of layer 103b. For example, the first semiconductor layer 103a comprises aluminum arsenide (AlAs) and/or aluminum gallium arsenide (Al x Ga 1-x As), in one embodiment, 0.5 ≦ x < 1, and a thickness of about 3 μm; The semiconductor layer 103b contains no aluminum, for example, contains gallium phosphide (GaP) and has a thickness of about 50 nm. In addition, in the present embodiment, the first semiconductor layer 103a has a two-layer structure, that is, the first semiconductor layer 103a includes the first aluminum-containing layer 103a1 and the second aluminum-containing layer 103a2, and the aluminum content in the two layers is different. In this embodiment, the aluminum content of the first aluminum-containing layer 103a1 is higher than the aluminum content of the second aluminum-containing layer 103a2, for example, the first aluminum-containing layer 103a1 is aluminum arsenide (AlAs), and the second aluminum-containing layer 103a2 is arsenic. Aluminum gallium (Al y Ga 1-y As, where 0.5 ≦ y < 1). The thickness of each of the first aluminum-containing layer 103a1 and the second aluminum-containing layer 103a2 is about 1.5 μm each.
接著，進行一孔洞(void)形成步驟，如圖1(c)所示，以一黃光及蝕刻製程在第二半導體層103b中蝕刻出開口孔洞103bo，此開口孔洞103bo作為後續形成之整個孔洞之開口端並提供一開口103boe於第二表面S2上。接著，如圖1(d)所示，以一濕蝕刻製程蝕 刻第一半導體層103a。在本實施例中，採用一酸性溶液進行濕蝕刻製程，例如採用檸檬酸(Citric Acid)或氫氟酸(HF)。此酸性溶液蝕刻並穿透第二含鋁層103a2，形成穿透部103a2o，此穿透部103a2o為最後形成之整個孔洞103v之中間部份。酸性溶液繼續蝕刻第一含鋁層103a1，並在第一含鋁層103a1中蝕刻出底部凹洞103a1ce，此凹洞103a1ce為整個孔洞103v之底部。 Next, a void forming step is performed. As shown in FIG. 1(c), an opening hole 103bo is etched in the second semiconductor layer 103b by a yellow light and an etching process, and the opening hole 103bo is formed as a subsequent hole. The open end is provided with an opening 103boe on the second surface S2. Next, as shown in Figure 1 (d), a wet etching process The first semiconductor layer 103a is engraved. In this embodiment, a wet etching process is performed using an acidic solution, such as citric acid or hydrofluoric acid (HF). This acidic solution etches and penetrates the second aluminum-containing layer 103a2 to form a penetrating portion 103a2o which is the intermediate portion of the finally formed entire hole 103v. The acidic solution continues to etch the first aluminum-containing layer 103a1 and etches a bottom recess 103a1ce in the first aluminum-containing layer 103a1, the recess 103a1ce being the bottom of the entire hole 103v.
值得注意的是，如前所述，因為第一含鋁層103a1和第二含鋁層103a2之鋁含量不同，故酸性溶液對兩層的蝕刻速率不同，鋁含量較高則蝕刻速率較高，故鋁含量較低之第二含鋁層103a2之穿透部103a2o之孔洞直徑d2小於鋁含量較高之第一含鋁層103a1之凹洞103a1ce之孔洞直徑d3。此外，穿透部103a2o係酸性溶液經由其上方之第二半導體層103b之開口孔洞103bo滲入並蝕刻，故穿透部103a2o之孔洞直徑d2大致等於或略大於第二半導體層103b之開口孔洞103bo之孔洞直徑d1。在本實施例中，開口孔洞103bo之孔洞直徑d1及穿透部103a2o之孔洞直徑d2大小約為0.1μm≦d1(或d2)≦20μm，而底部凹洞103a1ce之孔洞直徑d3大小約為1.2×d1≦d3≦10×d1。因而，在孔洞(void)形成步驟完成後，孔洞103v形成於半導體層103中，孔洞103v包含一底部(例如底部凹洞103a1ce)接近第一表面S1及一開口(例如開口103boe)位於第二表面S2，且孔洞103v之底部具有一寬度(d3)大於開口之寬度(d1)。 It is to be noted that, as described above, since the aluminum content of the first aluminum-containing layer 103a1 and the second aluminum-containing layer 103a2 are different, the etching rate of the two layers is different for the acidic solution, and the etching rate is higher for the aluminum content. Therefore, the hole diameter d2 of the penetration portion 103a2o of the second aluminum-containing layer 103a2 having a lower aluminum content is smaller than the hole diameter d3 of the cavity 103a1ce of the first aluminum-containing layer 103a1 having a higher aluminum content. Further, the penetrating portion 103a2o is an acidic solution which is infiltrated and etched through the opening hole 103bo of the second semiconductor layer 103b above it, so that the hole diameter d2 of the penetrating portion 103a2o is substantially equal to or slightly larger than the opening hole 103bo of the second semiconductor layer 103b. The hole diameter is d1. In the present embodiment, the hole diameter d1 of the opening hole 103bo and the hole diameter d2 of the penetrating portion 103a2o are about 0.1 μm ≦d1 (or d2) ≦ 20 μm, and the hole diameter d3 of the bottom cavity 103a1ce is about 1.2×. D1≦d3≦10×d1. Therefore, after the void forming step is completed, the hole 103v is formed in the semiconductor layer 103, and the hole 103v includes a bottom portion (for example, the bottom recess 103a1ce) near the first surface S1 and an opening (for example, the opening 103boe) on the second surface. S2, and the bottom of the hole 103v has a width (d3) larger than the width (d1) of the opening.
由上述實施例之教示，熟習本領域技藝之人士當了解，藉由控制半導體層103在其形成方向上之鋁含量不同，可以調整孔洞之 剖面形狀，例如上例中藉由第一含鋁層103a1之鋁含量高於第二含鋁層103a2之鋁含量，而蝕刻出底部寬度大於開口寬度之孔洞。故在一變化的實施例中，可以不形成第二含鋁層103a2，而其餘則和上述實施例方法相同。而在另一變化的實施例中，亦可以不形成第二半導體層103b，而在第一半導體層103a(之第二含鋁層103a2)上覆蓋光阻及曝光顯影形成具圓形開孔之圖案於光阻上，並以酸性溶液蝕刻第二含鋁層103a2及第一含鋁層103a1以形成孔洞。這些形成的孔洞可以有效改善發光二極體的光取出效率，提昇發光二極體的亮度。 It will be apparent to those skilled in the art from the teachings of the above-described embodiments that the hole can be adjusted by controlling the difference in aluminum content of the semiconductor layer 103 in the direction in which it is formed. The cross-sectional shape, for example, in the above example, is such that the aluminum content of the first aluminum-containing layer 103a1 is higher than the aluminum content of the second aluminum-containing layer 103a2, and the hole having a bottom width larger than the opening width is etched. Therefore, in a variant embodiment, the second aluminum-containing layer 103a2 may not be formed, and the remainder is the same as the method of the above embodiment. In another modified embodiment, the second semiconductor layer 103b may not be formed, and the first semiconductor layer 103a (the second aluminum-containing layer 103a2) may be covered with photoresist and exposed to form a circular opening. The pattern is on the photoresist, and the second aluminum-containing layer 103a2 and the first aluminum-containing layer 103a1 are etched with an acidic solution to form holes. These formed holes can effectively improve the light extraction efficiency of the light-emitting diode and improve the brightness of the light-emitting diode.
接著，如圖1(e)所示，形成一透明導電層104位於第二表面S2上並封閉開口103boe。透明導電層104例如是透明導電氧化層，例如包含一材料選自氧化銦錫(Indium Tin Oxide,ITO)、氧化鋁鋅(Aluminum Zinc Oxide,AZO)、氧化鎘錫、氧化銻錫、氧化鋅(ZnO)、及氧化鋅錫所構成之材料群組。 Next, as shown in FIG. 1(e), a transparent conductive layer 104 is formed on the second surface S2 and the opening 103boe is closed. The transparent conductive layer 104 is, for example, a transparent conductive oxide layer, for example, comprising a material selected from the group consisting of Indium Tin Oxide (ITO), Aluminium Zinc Oxide (AZO), cadmium tin oxide, antimony tin oxide, and zinc oxide. A group of materials consisting of ZnO) and zinc tin oxide.
接著，將圖1(e)上下旋轉180度顯示，如圖1(f)所示，在透明導電層104上形成一金屬層105與透明導電層104相接，並形成一第一接合層106a1與金屬層105相接。金屬層105為具高反射率之金屬，例如金(Au)，銀(Ag)，或鋁(Al)，以作為反射鏡。然後，提供一永久基板107，永久基板107為一導電基板，例如矽(Si)基板或碳化矽(SiC)基板，接著形成一第二接合層106a2於永久基板107上。第一接合層106a1與第二接合層106a2例如是金(Au)，銦(In)或二者之合金，使第一接合層106a1與第二接合層106a2相接後，形成接合結構106。之後移除基板101，並形成電極109於第一電性半導體層 102a上並與其歐姆接觸，如圖1(g)所示。此外，可選擇性地對第一電性半導體層102a實施一粗化步驟，以使第一電性半導體層102a具有一粗化表面以增加出光。最後，形成保護層108於第一電性半導體層102a上以保護發光元件。由於半導體層103含有鋁，容易與空氣中之水氣反應，故為提高元件可靠度，可於發光元件形成保護層108時一併覆蓋半導體層103之側壁。具體實施方式如圖1(g)所示，即對發光元件施以一微影及蝕刻製程，以移除發光疊層102及半導體層103之部份側壁，以使保護層108形成時一併覆蓋半導體層103之側壁。而由於本實施例中第二半導體層103b不含鋁，故上述蝕刻製程可僅蝕刻至第一半導體層103a，曝露出不含鋁之第二半導體層103b。如圖1(g)中所示，發光疊層102所發出之光線L行進至孔洞103v時，將產生反射及散射之效果，可以有效改善發光二極體的光取出效率，提昇發光二極體的亮度及在正向出光面之均勻性。 Next, FIG. 1(e) is rotated up and down by 180 degrees. As shown in FIG. 1(f), a metal layer 105 is formed on the transparent conductive layer 104 to be in contact with the transparent conductive layer 104, and a first bonding layer 106a1 is formed. It is in contact with the metal layer 105. The metal layer 105 is a metal having high reflectance such as gold (Au), silver (Ag), or aluminum (Al) as a mirror. Then, a permanent substrate 107 is provided. The permanent substrate 107 is a conductive substrate, such as a germanium (Si) substrate or a tantalum carbide (SiC) substrate, and then a second bonding layer 106a2 is formed on the permanent substrate 107. The first bonding layer 106a1 and the second bonding layer 106a2 are, for example, gold (Au), indium (In), or an alloy of the two, and the first bonding layer 106a1 and the second bonding layer 106a2 are brought into contact with each other to form the bonding structure 106. Thereafter, the substrate 101 is removed, and the electrode 109 is formed on the first electrical semiconductor layer. 102a is in contact with its ohmic as shown in Fig. 1(g). Further, a roughening step may be selectively performed on the first electrical semiconductor layer 102a such that the first electrical semiconductor layer 102a has a roughened surface to increase light emission. Finally, a protective layer 108 is formed on the first electrical semiconductor layer 102a to protect the light emitting elements. Since the semiconductor layer 103 contains aluminum, it is easy to react with moisture in the air. Therefore, in order to improve the reliability of the element, the side wall of the semiconductor layer 103 can be collectively covered when the protective layer 108 is formed on the light-emitting element. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As shown in FIG. 1(g), a lithography and etching process is applied to a light-emitting device to remove a portion of sidewalls of the light-emitting layer 102 and the semiconductor layer 103 so that the protective layer 108 is formed together. The sidewall of the semiconductor layer 103 is covered. Since the second semiconductor layer 103b does not contain aluminum in the present embodiment, the etching process can be etched only to the first semiconductor layer 103a to expose the second semiconductor layer 103b containing no aluminum. As shown in FIG. 1(g), when the light L emitted from the light-emitting layer 102 travels to the hole 103v, the effect of reflection and scattering is generated, and the light extraction efficiency of the light-emitting diode can be effectively improved, and the light-emitting diode can be improved. Brightness and uniformity in the forward exit surface.
圖2說明本發明第二實施例之發光元件及其製造方法，本實施例為上述第一實施例之變化型，如圖1(d)中所提及，藉由控制半導體層103在其形成方向上之鋁含量不同，可以調整孔洞之剖面形狀，本實施例僅改變第一實施例之半導體層103。在本實施例中，將第一實施例之第一含鋁層103a1及第二含鋁層103a2順序對調，即先形成第二含鋁層103a2，再形成第一含鋁層103a1。與第一實施例相同，第一含鋁層103a1為砷化鋁(AlAs)，第二含鋁層103a2為砷化鋁鎵(AlyGa1-yAs，其中0.5≦y<1)。由於鋁含量較高之第一含鋁層103a1在第二半導體層103b下方，故以酸性溶液蝕刻時，蝕刻之時間可設 定較第一實施例短，僅蝕刻第一含鋁層103a1並形成底部凹洞103a1ce，此凹洞103a1ce為整個孔洞103v’之底部。孔洞103v’包含一底部(例如底部凹洞103a1ce)接近第一表面S1及一開口(例如開口103boe)位於第二表面S2，且孔洞103v’之底部具有一寬度(d3)大於開口之寬度(d1)。至於後續步驟，與第一實施例相同，故不再贅述。相較於第一實施例以鋁含量較高之第一含鋁層103a1與發光疊層102相接，此實施例由於以鋁含量較低之第二含鋁層103a2與發光疊層102相接，故相較於第一實施例，可以有較低之正向電壓(forward voltage,Vf)。 2 illustrates a light-emitting element and a method of fabricating the same according to a second embodiment of the present invention. This embodiment is a variation of the above-described first embodiment, as mentioned in FIG. 1(d), by controlling the formation of the semiconductor layer 103 therein. The cross-sectional shape of the hole can be adjusted by the difference in the aluminum content in the direction. This embodiment only changes the semiconductor layer 103 of the first embodiment. In the present embodiment, the first aluminum-containing layer 103a1 and the second aluminum-containing layer 103a2 of the first embodiment are sequentially reversed, that is, the second aluminum-containing layer 103a2 is formed first, and then the first aluminum-containing layer 103a1 is formed. As in the first embodiment, the first aluminum-containing layer 103a1 is aluminum arsenide (AlAs), and the second aluminum-containing layer 103a2 is aluminum gallium arsenide (Al y Ga 1-y As, wherein 0.5 ≦ y < 1). Since the first aluminum-containing layer 103a1 having a high aluminum content is under the second semiconductor layer 103b, the etching time can be set shorter than that of the first embodiment when etching with an acidic solution, and only the first aluminum-containing layer 103a1 is etched and the bottom portion is formed. The cavity 103a1ce is the bottom of the entire hole 103v'. The hole 103v' includes a bottom portion (for example, the bottom recess 103a1ce) near the first surface S1 and an opening (for example, the opening 103boe) on the second surface S2, and the bottom of the hole 103v' has a width (d3) larger than the width of the opening (d1) ). The subsequent steps are the same as those of the first embodiment, and therefore will not be described again. Compared with the first embodiment, the first aluminum-containing layer 103a1 having a higher aluminum content is in contact with the light-emitting layer 102. This embodiment is connected to the light-emitting layer 102 by the second aluminum-containing layer 103a2 having a lower aluminum content. Therefore, compared to the first embodiment, there may be a lower forward voltage (Vf).
圖3說明本發明第三實施例之發光元件及其製造方法，本實施例亦為上述第一實施例之變化型，本實施例亦僅改變第一實施例之半導體層103。在本實施例中，於第一實施例之半導體層103再增加一第三含鋁層103a3，即先形成第三含鋁層103a3後，再如同第一實施例依續形成第一半導體層103a的第一含鋁層103a1、第二含鋁層103a2，及第二半導體層103b。在本實施例中，第三含鋁層103a3與第二含鋁層103a2相同，為砷化鋁鎵(AlyGa1-yAs，其中0.5≦y<1)，厚度亦約為1.5μm。至於後續步驟，與第一實施例相同，故不再贅述。相較於第一實施例，本實施例以鋁含量較高之第三含鋁層103a3與發光疊層102相接，故相較於第一實施例，可以有較低之正向電壓(forward voltage,Vf)；此外，在孔洞之剖面形狀上，相較於第二實施例，本實施例之孔洞103v與第一實施例之孔洞103v相同，具有穿透部103a2o成為孔洞103v之中間部份，可增加光的反射之機率， 故本實施例同時具有上述兩實施例之優點。 3 is a view showing a light-emitting element and a method of manufacturing the same according to a third embodiment of the present invention. This embodiment is also a modification of the first embodiment described above, and this embodiment also changes only the semiconductor layer 103 of the first embodiment. In this embodiment, a third aluminum-containing layer 103a3 is further added to the semiconductor layer 103 of the first embodiment, that is, after the third aluminum-containing layer 103a3 is formed, the first semiconductor layer 103a is formed as in the first embodiment. The first aluminum-containing layer 103a1, the second aluminum-containing layer 103a2, and the second semiconductor layer 103b. In the present embodiment, the third aluminum-containing layer 103a3 is the same as the second aluminum-containing layer 103a2, and is aluminum gallium arsenide (Al y Ga 1-y As, wherein 0.5 ≦ y < 1), and has a thickness of about 1.5 μm. The subsequent steps are the same as those of the first embodiment, and therefore will not be described again. Compared with the first embodiment, the third aluminum-containing layer 103a3 having a higher aluminum content is in contact with the light-emitting layer 102, so that the forward voltage can be lower than that of the first embodiment. In addition, in the cross-sectional shape of the hole, the hole 103v of the present embodiment is the same as the hole 103v of the first embodiment in comparison with the second embodiment, and has the penetrating portion 103a2o as the middle portion of the hole 103v. This can increase the probability of reflection of light, so this embodiment has the advantages of both of the above embodiments.
上述實施例僅為例示性說明本發明之原理及其功效，而非用於限制本發明。任何本發明所屬技術領域中具有通常知識者均可在不違背本發明之技術原理及精神的情況下，對上述實施例進行修改及變化。因此本發明之權利保護範圍如後述之申請專利範圍所列。 The above embodiments are merely illustrative of the principles of the invention and its advantages, and are not intended to limit the invention. Modifications and variations of the above-described embodiments can be made without departing from the spirit and scope of the invention. Therefore, the scope of the invention is as set forth in the appended claims.
102‧‧‧發光疊層 102‧‧‧Lighting laminate
102a‧‧‧第一電性半導體層 102a‧‧‧First electrical semiconductor layer
102b‧‧‧發光層 102b‧‧‧Lighting layer
102c‧‧‧第二電性半導體層 102c‧‧‧Second electrical semiconductor layer
103‧‧‧半導體層 103‧‧‧Semiconductor layer
103a‧‧‧第一半導體層 103a‧‧‧First semiconductor layer
103b‧‧‧第二半導體層 103b‧‧‧Second semiconductor layer
103a1‧‧‧第一含鋁層 103a1‧‧‧First aluminum layer
103a2‧‧‧第二含鋁層 103a2‧‧‧Second aluminum-containing layer
103a1ce‧‧‧底部凹洞 103a1ce‧‧‧ bottom recess
103a2o‧‧‧穿透部 103a2o‧‧‧ penetration
103bo‧‧‧開口孔洞 103bo‧‧‧Open hole
103boe‧‧‧開口 103boe‧‧‧ openings
103v‧‧‧孔洞 103v‧‧‧ hole
104‧‧‧透明導電層 104‧‧‧Transparent conductive layer
105‧‧‧金屬層 105‧‧‧metal layer
106‧‧‧接合結構 106‧‧‧ joint structure
106a1‧‧‧第一接合層 106a1‧‧‧First joint layer
106a2‧‧‧第二接合層 106a2‧‧‧Second joint layer
107‧‧‧永久基板 107‧‧‧Permanent substrate
108‧‧‧保護層 108‧‧‧Protective layer
109‧‧‧電極 109‧‧‧Electrode
L‧‧‧光線 L‧‧‧Light
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| US9847450B2 (en) | 2017-12-19 |
| US20170352782A1 (en) | 2017-12-07 |
| US11005007B2 (en) | 2021-05-11 |
| US20200006595A1 (en) | 2020-01-02 |
| US20150108494A1 (en) | 2015-04-23 |
| US10453995B2 (en) | 2019-10-22 |
| TW201517305A (en) | 2015-05-01 |
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