TWI596678B - Semiconductor package structure and manufacturing method thereof - Google Patents

Description

Semiconductor package structure and manufacturing method thereof

The present invention relates to a package structure and a method of fabricating the same, and more particularly to a semiconductor package structure and a method of fabricating the same.

In the semiconductor industry, the production of integrated circuits (ICs) can be divided into three stages: the design of integrated circuits, the fabrication of integrated circuits, and the packaging of integrated circuits. After the fabrication of the integrated circuit of the wafer is completed, the active surface of the wafer is provided with a plurality of pads. Finally, the bare wafer obtained by wafer dicing can be electrically connected to the carrier through the pad. Generally, the carrier can be a lead frame, a substrate or a printed circuit board, and the wafer can be connected by wire bonding or flip chip bonding. Connected to the carrier to electrically connect the pads of the wafer to the contacts of the carrier to form a chip package.

Taking a package substrate as an example, most of them have a core layer, so the thickness is thick and the cost is high. On the other hand, in order to make the chip package have good heat dissipation efficiency, the current practice is mostly to attach the heat sink to the wafer, and further enclose the heat sink on the package encapsulant coated on the wafer. Alternatively, the heat sink is attached to the encapsulant and the heat sink is thermally coupled to the wafer by direct connection or indirect connection. Therefore, the overall thickness of the chip package is difficult to reduce.

The invention provides a method for fabricating a semiconductor package structure, which can produce a semiconductor package structure having a thin overall thickness and good heat dissipation effect.

The invention provides a semiconductor package structure which has a thin overall thickness and a good heat dissipation effect.

The invention provides a method for fabricating a semiconductor package structure, which comprises the following steps. A carrier board is provided. Configure the metal piece on the carrier board. A dielectric layer is formed on the carrier and the dielectric layer is coated with the metal sheet. The dielectric layer has opposing first and second surfaces, and the dielectric layer is coupled to the carrier with the first surface. A patterned wiring layer is formed on the second surface of the dielectric layer. The carrier is removed to expose the metal sheet to the first surface of the dielectric layer. Removing a portion of the dielectric layer to form at least one first opening on the first surface and a second opening on the second surface, wherein the first opening exposes a portion of the patterned wiring layer and the second opening exposes the metal sheet. The first wafer is disposed on the metal sheet such that the first wafer is located in the second opening and electrically connected to the patterned circuit layer. An encapsulant is formed on the second surface of the dielectric layer, and the encapsulant covers the first wafer and the patterned wiring layer.

In an embodiment of the invention, the method for fabricating the semiconductor package structure further includes forming at least one external connection terminal in the first opening, and the external connection terminal is electrically connected to the patterned circuit layer.

In an embodiment of the invention, the method for fabricating the semiconductor package structure further includes disposing a second wafer over the second surface of the dielectric layer before forming the encapsulant on the second surface of the dielectric layer, and The second wafer is electrically connected to the patterned wiring layer.

In an embodiment of the invention, the method for fabricating the semiconductor package structure further includes covering the second wafer with the encapsulant.

In an embodiment of the invention, the encapsulant described above fills the second opening.

The present invention provides a semiconductor package structure including a metal piece, a dielectric layer, a patterned wiring layer, a first wafer, and an encapsulant. The dielectric layer covers the metal sheet, wherein the dielectric layer has opposing first and second surfaces, at least one first opening on the first surface, and a second opening on the second surface. The metal sheets are located within the second opening and are exposed to the first surface and the second surface of the dielectric layer, respectively. The patterned wiring layer is disposed on the second surface of the dielectric layer. The first wafer is disposed on the metal sheet, wherein the first wafer is located in the second opening and electrically connected to the patterned circuit layer. The encapsulant is disposed on the second surface of the dielectric layer and covers the first wafer and the patterned circuit layer.

In an embodiment of the invention, the semiconductor package structure further includes at least one external connection terminal. The external connection terminal is disposed in the first opening, and the external connection terminal is electrically connected to the patterned circuit layer.

In an embodiment of the invention, the semiconductor package structure further includes a second wafer. The second wafer is disposed above the second surface of the dielectric layer and electrically connected to the patterned circuit layer.

In an embodiment of the invention, the second wafer is covered by an encapsulant.

In an embodiment of the invention, the bottom surface of the metal piece is flush with the first surface of the dielectric layer.

Based on the above, the semiconductor package structure fabricated by the method for fabricating the semiconductor package structure of the present invention does not have a core layer, and the wafer and the metal sheet thermally coupled to each other are buried in the opening of the dielectric layer. On the other hand, the metal sheet is exposed to one of the surfaces of the dielectric layer. Therefore, the overall thickness of the semiconductor package structure of the present invention can be greatly reduced, and at the same time, it has a good heat dissipation effect.

The above described features and advantages of the invention will be apparent from the following description.

1 to 8 are schematic cross-sectional views showing a manufacturing process of a semiconductor package structure according to an embodiment of the present invention. Referring to FIG. 1, first, a carrier 10 is provided. In the present embodiment, the carrier 10 can be made of a material having a high rigidity, so that it is less susceptible to bending and deformation. Referring to FIG. 1 , the metal piece 110 is disposed on the carrier 10 . The metal piece 110 can be directly attached to the carrier 10 through the bottom surface 111 thereof or temporarily fixed to the carrier 10 through a release film (not shown) on the bottom surface 111. The metal sheet 110 may be made of copper, aluminum, silver or other metal materials having good thermal conductivity.

Next, referring to FIG. 2, a semiconductor oxide (for example, cerium oxide) is formed on the carrier 10 by chemical vapor deposition (CVD), and the semiconductor oxide is covered with the metal oxide 110 to form a dielectric layer. 120. In the present embodiment, the dielectric layer 120 has opposing first and second surfaces 121 and 122, wherein the first surface 121 is coupled to the carrier 10 and substantially flush with the bottom surface 111 of the metal sheet 110. Next, referring to FIG. 3, the patterned wiring layer 130 is formed on the second surface 122 of the dielectric layer 120 by, for example, sputtering, printing, electroplating, electroless plating, chemical vapor deposition, or physical vapor deposition (PVD). . At this time, the dielectric layer 120 is located between the patterned wiring layer 130 and the carrier 10. Next, referring to FIG. 4, the carrier 10 is removed to expose the first surface 121 of the dielectric layer 120 and the bottom surface 111 of the metal sheet 110. In another perspective, the bottom surface 111 of the metal sheet 110 is, for example, exposed to the first surface 121 of the dielectric layer 120. It is worth mentioning that if the metal piece 110 is temporarily fixed to the carrier 10 through the release film on the bottom surface 111, the release film (not shown) will be removed when the carrier 10 is removed. And was removed.

Next, referring to FIG. 5, a portion of the dielectric layer 120 is removed by, for example, laser etching to form at least one first opening 123 (showing a plurality of schematically) on the first surface 121 and at the second A second opening 124 in the surface 122. In forming these first openings 123, the laser source is first aligned with the patterned wiring layer 130. Next, the laser beam is projected onto the first surface 121 of the dielectric layer 120 to etch the dielectric layer 120 until the patterned wiring layer 130 is exposed, and the principle is that the patterned wiring layer 130 is not damaged. On the other hand, when the second opening 124 is formed, the laser source is first aligned with the metal piece 110. Next, the laser beam is projected onto the second surface 122 of the dielectric layer 120 to etch the dielectric layer 120 until the metal sheet 110 is exposed, and the principle is that the metal sheet 110 is not damaged. As shown in FIG. 5, the cross-sectional area of the second opening 124 is, for example, smaller than the surface area of the metal piece 110. In other embodiments, the cross-sectional area of the second opening may be greater than or equal to the surface area of the metal sheet, and the end-to-end process requirements are adjusted.

Next, referring to FIG. 6, the first wafer 140 is disposed on the metal piece 110, and the first wafer 140 is disposed in the second opening 124. In the present embodiment, the active surface 141 of the first wafer 140 is exposed to the second surface 122 of the dielectric layer 120, in other words, the first wafer 140 is fixed to the metal sheet 110 with its back surface 142. In addition, the first wafer 140 can be adhered to the metal sheet 110 through the adhesive layer 150 (for example, a thermal conductive adhesive). Then, the wire 160 is bonded to the pad (not shown) and the patterned circuit layer 130 on the active surface 141 of the first wafer 140 by wire bonding to electrically connect the first die 140 and the patterned circuit layer 130. connection. Next, referring to FIG. 7 , the encapsulant 170 is formed on the second surface 122 of the dielectric layer 120 , and the encapsulant 170 covers the first wafer 140 and the patterned wiring layer 130 . On the other hand, the encapsulant 170 may further fill the second opening 124 to cover a portion of the surface of the metal sheet 110 exposed to the second opening 124, thereby fixing the first wafer 140 to the second opening 124. The encapsulant 170 may be an epoxy resin to prevent the patterned wiring layer 130, the first wafer 140, and the wires 160 from being affected by external moisture or foreign matter.

Thereafter, referring to FIG. 8, at least one external connection terminal 180 (two schematically shown) is formed in the first opening 123. The number of these external connection terminals 180 corresponds to the number of the first openings 123, and these external connection terminals 180 are electrically connected to the patterned wiring layer 130. In this embodiment, the external connection terminal 180 is partially buried in the first opening 123 and protrudes from the first surface 121 of the dielectric layer 120, but the invention is not limited thereto. In general, the external connection terminal 180 can be a solder ball. So far, the fabrication of the semiconductor package structure 100 has been substantially completed. Since the semiconductor package structure 100 does not have a core layer, and the first wafer 140 and the metal piece 110 thermally coupled to each other are buried in the second opening 124 of the dielectric layer 120, the overall thickness of the semiconductor package structure 100 can be greatly reduced. . On the other hand, since the bottom surface 111 of the metal piece 110 is exposed to the first surface 121 of the dielectric layer 120, the semiconductor package structure 100 can have a good heat dissipation effect.

Other embodiments are listed below for illustration. It is to be noted that the following embodiments use the same reference numerals and parts of the above-mentioned embodiments, and the same reference numerals are used to refer to the same or similar elements, and the description of the same technical content is omitted. For the description of the omitted portions, reference may be made to the foregoing embodiments, and the following embodiments are not repeated.

9 is a cross-sectional view showing a semiconductor package structure according to another embodiment of the present invention. Referring to FIG. 9 , the fabrication process of the semiconductor package structure 100A of the present embodiment is similar to that of the semiconductor package structure 100 of the above embodiment. The difference between the two is that the package encapsulant 170 is formed on the dielectric layer 120 . Before the second surface 122, the second wafer 190 is disposed above the second surface 122 of the dielectric layer 120, and the active surface 191 of the second wafer 190 faces the second surface 122 of the dielectric layer 120. In detail, in this embodiment, a plurality of bumps 181 are bonded between the active surface 191 of the second wafer 190 and the patterned wiring layer 130 by flip-chip bonding, so that the second wafer 190 is electrically connected to the pattern. The circuit layer 130 is formed. The bump 181 can be an electroplated bump, an electroless bump, a junction bump, a conductive polymer bump or a metal composite bump, and the material of the bump 181 can be selected from the group consisting of copper, gold, silver, tin, Indium, nickel/gold, nickel/palladium/gold, copper/nickel/gold, copper/gold, aluminum and alloys thereof. On the other hand, when the encapsulant 170 is formed on the second surface 122 of the dielectric layer 120, the encapsulant 170 further covers the second wafer 190 and the bumps 181. Therefore, the patterned wiring layer 130, the first wafer 140, the wires 160, the bumps 181, and the second wafer 190 covered by the encapsulant 170 are less susceptible to external moisture or foreign matter.

In summary, the semiconductor package structure fabricated by the method for fabricating a semiconductor package structure of the present invention does not have a core layer, and the wafer and the metal sheet thermally coupled to each other are buried in one of the openings of the dielectric layer. On the other hand, the external connection terminals electrically connected to the patterned wiring layer on the dielectric layer are partially buried in other openings of the dielectric layer, and the metal sheets are exposed to one surface of the dielectric layer. Therefore, the overall thickness of the semiconductor package structure of the present invention can be greatly reduced, and at the same time, it has a good heat dissipation effect.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧ Carrier Board
100, 100A‧‧‧ semiconductor package structure
110‧‧‧metal pieces
111‧‧‧ bottom
120‧‧‧ dielectric layer
121‧‧‧ first surface
122‧‧‧ second surface
123‧‧‧First opening
124‧‧‧second opening
130‧‧‧ patterned circuit layer
140‧‧‧First chip
141‧‧‧Active surface
142‧‧‧Back surface
150‧‧‧ glue layer
160‧‧‧ wire
170‧‧‧Package colloid
180‧‧‧External connection terminal
181‧‧‧Bumps
190‧‧‧second chip
191‧‧‧Active surface

1 to 8 are schematic cross-sectional views showing a manufacturing process of a semiconductor package structure according to an embodiment of the present invention. 9 is a cross-sectional view showing a semiconductor package structure according to another embodiment of the present invention.

100‧‧‧Semiconductor package structure

110‧‧‧metal pieces

111‧‧‧ bottom

120‧‧‧ dielectric layer

121‧‧‧ first surface

122‧‧‧ second surface

123‧‧‧First opening

124‧‧‧second opening

130‧‧‧ patterned circuit layer

140‧‧‧First chip

141‧‧‧Active surface

142‧‧‧Back surface

150‧‧‧ glue layer

160‧‧‧ wire

170‧‧‧Package colloid

180‧‧‧External connection terminal

Claims (11)

A method of fabricating a semiconductor package structure includes: providing a carrier; arranging a metal piece on the carrier; forming a dielectric layer on the carrier, and covering the metal layer with the dielectric layer, wherein The dielectric layer has a first surface and a second surface opposite to each other, and the dielectric layer is connected to the carrier by the first surface; forming a patterned circuit layer on the second surface of the dielectric layer Removing the carrier to expose the metal sheet to the first surface of the dielectric layer; removing a portion of the dielectric layer to form at least a first opening on the first surface and at the first a second opening on the second surface, wherein the at least one first opening exposes a portion of the patterned circuit layer, and the second opening exposes the metal piece; and a first wafer is disposed on the metal piece to make the first The wafer is located in the second opening and electrically connected to the patterned circuit layer; and an encapsulant is formed on the second surface of the dielectric layer, and the encapsulant covers the first wafer and the patterned circuit Floor. The method of fabricating the semiconductor package structure of claim 1, further comprising: forming at least one external connection terminal in the at least one first opening, and electrically connecting the at least one external connection terminal to the patterned circuit layer . The method for fabricating a semiconductor package structure according to claim 1, further comprising: Before forming the encapsulant on the second surface of the dielectric layer, disposing a second wafer over the second surface of the dielectric layer, and electrically connecting the second wafer to the patterned circuit Floor. The method for fabricating a semiconductor package structure according to claim 3, further comprising: covering the second wafer with the encapsulant. The method of fabricating a semiconductor package structure according to claim 1, wherein the encapsulant fills the second opening. A semiconductor package structure comprising: a metal piece; a dielectric layer covering the metal piece, wherein the dielectric layer has a first surface and a second surface opposite to each other, and at least one of the first surface An opening and a second opening on the second surface, wherein the metal piece is located in the second opening and exposed to the first surface and the second surface of the dielectric layer respectively; a patterned circuit layer And disposed on the second surface of the dielectric layer; a first wafer disposed on the metal sheet, wherein the first wafer is located in the second opening and electrically connected to the patterned circuit layer; An encapsulant disposed on the second surface of the dielectric layer and covering the first wafer and the patterned wiring layer. The semiconductor package structure as claimed in claim 6 further includes: The at least one external connection terminal is disposed in the at least one first opening, and the at least one external connection terminal is electrically connected to the patterned circuit layer. The semiconductor package structure of claim 6, further comprising: a second wafer disposed over the second surface of the dielectric layer and electrically connected to the patterned circuit layer. The semiconductor package structure of claim 8, wherein the second wafer is covered by the encapsulant. The semiconductor package structure of claim 6, wherein a bottom surface of the metal piece is flush with the first surface of the dielectric layer. The semiconductor package structure of claim 6, wherein the encapsulant fills the second opening.