TWI591760B - Semiconductor devices and methods for forming the same - Google Patents

Description

Semiconductor device and method of forming same

The present invention relates to a semiconductor device, and more particularly to an isolation structure for a semiconductor device and a method of forming the same.

A portion of the semiconductor device is formed within the substrate and the active region is separated by an isolation structure formed within the substrate. As the size of semiconductor devices continues to shrink and device densities continue to increase, the problem of conventional local oxidation of silicon (LOCOS) isolation techniques that are prone to surface roughness and bird's beak effects cannot be ignored. Therefore, shallow trench isolation (STI) is a commonly used isolation technique for semiconductor devices below 0.25 micrometers (μm).

Although the existing semiconductor devices and their formation methods have been developed in isolation structures to meet their intended intended use, they have not been fully met in all respects. Therefore, the isolation technology of semiconductor devices still needs to be worked hard. direction.

The present disclosure provides an embodiment of a shallow trench isolation structure of a semiconductor device and a method of forming the same, prior to removing the patterned mask for trench formation, performing a heat treatment process such that a proliferating oxidized portion is formed adjacent the edge of the isolation structure To overcome the etching process that subsequently removes excess material to form an isolation structure, It is easy to form a divot at the edge of the isolation structure due to over-etching, thereby forming a smoother gate oxide surface at the interface between the isolation structure and the active region to improve the gate oxide integrity (gate oxide integrity). , GOI), and reduce the probability of occurrence of point discharge and electrical breakdown effects, improving the performance and reliability of semiconductor devices.

According to some embodiments, a method of forming a semiconductor device is provided. The method of forming a semiconductor device includes forming a patterned mask on a substrate, the patterned mask comprising a pad oxide and a tantalum nitride layer on the pad oxide layer. The method of forming a semiconductor device further includes performing a first etching process on the substrate via the patterned mask to form a trench, and forming a layer of dielectric material within the trench and on the patterned mask. The method of forming a semiconductor device also includes performing a planarization process to remove a layer of dielectric material outside the trench. The method of forming a semiconductor device further includes performing a heat treatment process to form an oxidized portion adjacent to the dielectric material layer at an interface between the pad oxide layer and the substrate.

According to some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure formed in the substrate. The semiconductor device also includes a gate oxide layer formed on the substrate and a portion of the isolation structure, wherein the gate oxide layer has an extension at the edge of the isolation structure. The semiconductor device further includes a gate electrode layer formed on the gate oxide layer and the isolation structure.

100a, 100b‧‧‧ semiconductor structure

101, 201‧‧‧ base

111, 211‧‧ ‧ isolation structure

112, 212‧‧‧ dent

113, 213‧‧ ‧ gate oxide layer

115, 215‧‧ ‧ gate electrode layer

117‧‧‧ source

119‧‧‧汲polar

120‧‧‧active area

130, 230‧‧ ‧ gate structure

200‧‧‧ Process

201a‧‧‧ top

203‧‧‧Mat oxide layer

204‧‧‧patterned mask

205‧‧‧ layer of tantalum nitride

206‧‧‧ trench

207‧‧‧ patterned photoresist layer

209‧‧‧ dielectric material layer

210‧‧‧Oxidation Department

213a‧‧‧Extension

300‧‧‧First etching process

400‧‧‧ Flattening process

500‧‧‧ Heat treatment process

600‧‧‧Second etching process

D‧‧‧vertical distance

t ₁ , t ₂ , t ₃ , t ₄ ‧‧‧ thickness

t ₄ ‧‧‧distance

We can better understand the point of view of the present disclosure by the following detailed description in conjunction with the accompanying drawings. It is worth noting that some features may not be drawn to scale according to industry standard practice. In fact, in order to be able to clear It is discussed that the size of different features may be increased or decreased.

1A is a top view showing a semiconductor device, wherein FIG. 1C is a cross-sectional view showing the semiconductor device of the comparative example taken along line 1A of FIG. 1A, and FIG. 2I is a view showing the semiconductor device along the embodiment of the present disclosure. 1A-1 is a schematic cross-sectional view showing a different stage of forming a semiconductor device of a comparative example; FIG. 1C' is an enlarged schematic view showing a region of FIG. 1CA; FIG. 2A-2I According to some embodiments of the present disclosure, a schematic cross-sectional view showing different stages of forming a semiconductor device is shown; FIG. 2H' is an enlarged schematic view showing a region of FIG. 2H FIG. B according to some embodiments of the present disclosure; FIG. 2I' is a diagram according to the present disclosure Some embodiments show an enlarged schematic view of the area of Figure 2C.

The following disclosure provides many different embodiments or examples for implementing the various components of the semiconductor device provided. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are merely examples and are not intended to limit the disclosure. For example, reference to a first element formed above a second element in the description may include embodiments in which the first and second elements are in direct contact, and may also include additional elements formed between the first and second elements. Embodiments that make them in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of clarity and clarity, and is not intended to represent the relationship of the various embodiments and/

Some variations of the embodiments are described below. In the various figures and illustrated embodiments, like reference numerals are used to design It will be appreciated that additional operations may be provided before, during, and after the method, and that some of the recited operations may be substituted or deleted for other embodiments of the method.

In the prior art, since the size and depth of the recess at the edge of the isolation structure are too large, the gate oxide layer formed on the recess is thinner than the gate oxide layer on the substrate, so that the gate electrode layer is at the edge of the isolation structure and the semiconductor. The distance between the substrates is too close, and the surface curvature of the gate oxide layer and the gate electrode layer in the recess is too curved and not smooth, and problems such as tip discharge, electric collapse effect and short circuit are easily generated, and the implementation of the present disclosure The examples aim to solve these problems and improve the performance and reliability of semiconductor devices.

1A is a top view showing a semiconductor device 100a/100b, wherein FIG. 1C is a cross-sectional view showing the semiconductor device 100a of the comparative example taken along line 1A of FIG. 1A, and FIG. 2I is a view showing some embodiments according to the present disclosure. FIG. 1B-1C is a schematic cross-sectional view showing a different stage of forming a semiconductor device 100a of a comparative example, and FIG. 1C' is an enlarged schematic view showing a region of the first C-FIG. A. .

As shown in FIG. 1A, the active region 120 of the semiconductor device 100a includes a source 117 and a drain 119. The isolation structure 111 is located between the adjacent two active regions 120 and surrounds the active region 120 to isolate the two active regions 120. . The gate structure 130 of the semiconductor device 100a includes a gate oxide layer 113 and a gate electrode layer 115 on the gate oxide layer 113 (as shown in FIG. 1C), and the gate structure 130 is disposed at the source of the active region 120. 117 and the drain 119, and across the active area 120 and the isolation structure 111, the 1C figure is shown along the 1A A schematic cross-sectional view of line 1-1.

As shown in FIG. 1B, an isolation structure 111 is formed in the substrate 101, wherein the substrate 101 is a semiconductor substrate, and the edge of the isolation structure 111 has a distinct recess 112, which is formed by removing the substrate 101 for forming an isolation structure. When a patterned mask (not shown) of the trench of 111 is used, since an isotropic etching process is used, and the isolation structure 111 and the pad oxide material in the patterned mask are similar in material, the pad oxide layer is The thickness is smaller than the thickness of the isolation structure 111, and the phenomenon of excessive etching is likely to occur at the edge of the isolation structure 111 where the difference in thickness is most apparent, thus forming the recess 112.

As shown in FIGS. 1C and 1C', the gate oxide layer 113 and the gate electrode layer 115 are sequentially formed on the isolation structure 111 and the substrate 101. Since the edge of the isolation structure 111 has the recess 112, the recess in the isolation structure 111 The thickness t ₂ of the gate oxide layer 113 on 112 is smaller than the thickness t ₁ of the gate oxide layer 113 on the substrate 101. In some examples, the ratio of t ₂ to t ₁ is between 0.7 and 0.85. Since the gate oxide layer 113 formed on the recess 112 is thinner than the gate oxide layer 113 on the substrate 101, the gate electrode layer 115 is too close to the substrate 101 at the edge of the isolation structure 111, and the recess 112 is added. The surface of the gate oxide layer 113 and the gate electrode layer 115 are not flat, and are susceptible to tip discharge, electrical collapse, or even short circuit. Moreover, as the size of semiconductor devices is shrinking, the performance and reliability of semiconductor devices are also greatly reduced due to problems.

2A-2I are schematic cross-sectional views showing different stages of forming a semiconductor device 100b, in accordance with some embodiments of the present disclosure. The semiconductor device 100b includes a substrate 201. In some embodiments, the substrate 201 can be made of tantalum or other semiconductor material, or the substrate 201 can comprise other elemental semiconductor materials, such as germanium. (Ge). In some embodiments, substrate 201 is made of a compound semiconductor, such as tantalum carbide, gallium nitride, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, substrate 201 is made of an alloy semiconductor such as germanium, tantalum carbide, gallium arsenide or indium gallium phosphide. In some embodiments, substrate 201 comprises a silicon-on-insulator (SOI) substrate. In some embodiments, substrate 201 comprises an epitaxial layer. For example, substrate 201 has an epitaxial layer overlying the bulk semiconductor.

According to some embodiments, as shown in FIG. 2A, a pad oxide layer 203 and a tantalum nitride layer 205 are sequentially formed on the substrate 201. In some embodiments, the tantalum nitride layer 205 may be substituted with hafnium oxynitride or other similar materials. In some embodiments, the pad oxide layer 203 is formed using thermal oxidation or other suitable process. In some embodiments, the tantalum nitride layer 205 is formed using chemical vapor deposition (CVD) or other suitable process. The pad oxide layer 203 serves as a buffer layer for decomposing stress between the tantalum nitride layer 205 and the substrate 201, and the tantalum nitride layer 205 serves as a stop layer for the subsequent planarization process.

According to some embodiments, as shown in FIG. 2B, a patterned photoresist layer 207 is formed on the tantalum nitride layer 205. The region not covering the patterned photoresist layer 207 is a region where the isolation structure is formed later (for example, the region of the isolation structure 211 shown in FIG. 1A), and the region covering the patterned photoresist layer 207 is a region where the active region is subsequently formed (for example, The area of the active area 120 shown in Fig. 1A). Next, using the patterned photoresist layer 207 as a mask, the pad oxide layer 203 and the tantalum nitride layer 205 are patterned to form a patterned mask 204 as shown in FIG. 2C. The patterned mask 204 includes a pad oxide layer 203 and a tantalum nitride layer 205, and subsequently forms a trench in the substrate 201. Used in the etching process of the groove.

According to some embodiments, as shown in FIG. 2C, a first etch process 300 is performed on the substrate 201 via the patterned mask 204 to form trenches in the substrate 201, and trenches and patterned masks 204 in the substrate 201. The openings together form a trench 206 as shown in Figure 2D. In some embodiments, the first etch process 300 includes wet etch, dry etch, or other suitable process. In some embodiments, the dry etch comprises a plasma etch process using fluorine, chlorine or other suitable gas. In some embodiments, the depth of the trench 206' is less than 0.5 μm, but is not limited thereto, and may be adjusted to be larger or smaller depending on the element size of the semiconductor device.

Following the foregoing, as shown in FIG. 2E, a layer of dielectric material 209 is formed within trench 206 and patterned mask 204. In some embodiments, the dielectric material layer 209 is made of hafnium oxide, tantalum nitride, hafnium oxynitride or other suitable dielectric material. In some embodiments, the dielectric material layer 209 is made of a different material than the pad oxide layer 203. In some embodiments, the dielectric material layer 209 is formed using a chemical vapor deposition (CVD) process, an atmospheric pressure chemical vapor deposition (APCVD) process, and a high density plasma chemical vapor deposition (high). Density plasma chemical vapor deposition (HDPCVD) process or other suitable process.

According to some embodiments, as shown in FIG. 2E, the germanium nitride layer 205 is used as a stop layer, and a planarization process 400 is performed to remove the dielectric material layer 209 on the outer surface of the trench 206, that is, the tantalum nitride layer 205. The top surface of the dielectric material layer 209 in the trench 206 is flush with the top surface of the tantalum nitride layer 205, as shown in FIG. 2F. In some embodiments, the planarization process 400 can further remove portions of the tantalum nitride layer 205. In some embodiments, the planarization process 400 can include chemical mechanical polishing (chemical mechanical polishing, CMP) process, grinding process, etching process, other suitable processes, or a combination of the foregoing.

According to some embodiments, as shown in FIG. 2F, after the planarization process 400 is performed, oxygen is introduced into the semiconductor device 100b to perform the heat treatment process 500, and oxygen is diffused into the dielectric material layer 209 and the substrate 201 and the pad oxide layer 203. The interface in the vertical direction forms an oxidized portion 210 adjacent to the dielectric material layer 209 at the sidewall of the trench 206 at the interface between the pad oxide layer 203 and the substrate 201 in the horizontal direction, as shown in FIG. 2G, in which oxidation occurs. The portion 210 is formed at both side edges of the dielectric material layer 209 in the trench 206 to form a guanine effect structure similar to the LOCOS isolation technique. In some embodiments, the temperature of the heat treatment process 500 is in the range of from about 950 °C to about 1050 °C. In some embodiments, the heat treatment process has a time in the range of from about 15 minutes to about 40 minutes. It is to be noted that the shape and thickness of the oxidized portion 210 can be regulated by the temperature and time of the heat treatment process 500.

Thereafter, according to some embodiments, as shown in FIG. 2G, a second etching process 600 is performed to remove the tantalum nitride layer 205, the pad oxide layer 203, a portion of the dielectric material layer 209, and a portion of the oxide portion 210 to be exposed. The top surface 201a of the substrate 201 is formed to form an isolation structure 211 having sharp beak-like shapes on both sides, as shown in FIG. 2H. In some embodiments, the second etch process 600 includes wet etch, dry etch, or other suitable process. In some embodiments, wet etching can be performed in a one-stage process using a phosphoric acid solution. In other embodiments, wet etching can be performed in a two-stage process using phosphoric acid and hydrofluoric acid solutions. In some embodiments, the isolation structure 211 is a shallow trench isolation (STI) structure having a depth of less than 0.5 [mu]m.

Continuing the foregoing, the 2H' diagram is in accordance with some embodiments of the present disclosure, An enlarged schematic view of the B region of FIG. 2H is shown. As shown in FIG. 2H', the isolation structure 211 has a recess 212 near the top of both sides of the substrate 201. In some embodiments, the vertical distance d from the bottom surface of the recess 212 to the top surface 201a of the substrate 201 is less than about 50 Å. It should be noted that the recess 212 of the edge of the isolation structure 211 of the semiconductor device 100b according to the embodiment of the present disclosure is shallower than the recess 112 of the edge of the isolation structure 111 of the semiconductor device 100a of the first embodiment of the comparative example. This is because the semiconductor device 100b of the embodiment has undergone the heat treatment process 500 more than the semiconductor device 100a of the comparative example, so that after the subsequent second etching process 600 is performed, the semiconductor device 100b having a relatively flat surface is formed. In some embodiments, the depth of the recess 212 (e.g., the vertical distance d) can be adjusted by the shape and size of the second oxidized portion 210b formed by the temperature and time of the heat treatment process 500. In some other embodiments, the value of the vertical distance d is small enough to be ignored such that the entire top surface of the isolation structure 211 is substantially flat. In some other embodiments, the top surface of the isolation structure 211 is substantially flush with the top surface of the substrate 201.

According to some embodiments, as shown in FIG. 2I, the gate oxide layer 213 of the gate stack 230 of FIG. 1A is formed in the recess 212 and the region above and below the top surface 201a of the substrate 201, and is oxidized in the isolation structure 211 and the gate. A gate electrode layer 215 of the gate stack 230 of FIG. 1A is formed on the layer 213. In some embodiments, the gate oxide layer 213 and the gate electrode layer 215 are subjected to a thermal oxidation process, a chemical vapor deposition (CVD) process, a flowable chemical vapor deposition (FCVD) process, and atomic layer deposition. (Atomic layer deposition, ALD) process, low-pressure chemical vapor deposition (LPCVD) process, plasma enhanced chemical vapor phase A plasma enhanced chemical vapor deposition (PECVD) process, other suitable processes, or a combination of the foregoing are separately formed. In some embodiments, the gate oxide layer 213 may be made of a yttria or a high dielectric constant dielectric material, wherein the high dielectric constant dielectric material may be yttrium oxide, zirconium oxide, aluminum oxide, cerium oxide-alumina. Hafnium dioxide-alumina alloy, niobium oxide, niobium oxynitride, niobium oxide, niobium titanium oxide, niobium zirconium oxide, other suitable high dielectric constant materials or combinations thereof. In some embodiments, the gate electrode layer 215 comprises a metal or other suitable electrically conductive material, such as: tungsten, copper, nickel, aluminum, tungsten telluride, polycrystalline germanium, or combinations thereof.

As shown in FIG. 2I, the gate oxide layer 213 has an extension 213a in the recess 212 at the side edges of the isolation structure 211 adjacent to the substrate 201. In some embodiments, the distance from the top surface of the extension 213a of the gate oxide layer 213 to the interface between the isolation structure 211 and the substrate 201 in a direction perpendicular to the surface of the substrate 201 is in the range of about 130 Å to about 500 Å. 2I' is an enlarged schematic view showing a region of FIG. 2I in accordance with some embodiments of the present disclosure. In some embodiments, the distance t ₄ from the top surface of the extension 213a to the interface between the isolation structure 211 and the substrate 201 in a direction perpendicular to the surface (Z-axis) of the substrate 201 is only slightly less than or greater than the gate oxidation on the substrate 201. Layer 213 has a thickness t ₃ . In some embodiments, the ratio of t ₄ to t ₃ is greater than about 0.95. By the formation of the extension portion 213a, the top surface of the gate oxide layer 213 is smooth and largely flat from the substrate 201 to the isolation structure 211.

Comparing the semiconductor structure 100b of the embodiment with the semiconductor structure 100a of the comparative example, as shown in FIG. 1C', the thickness t ₂ of the gate oxide layer 113 of the semiconductor structure 100a of the comparative example at both side edges of the isolation structure 111 is The ratio of the thickness t ₁ on the substrate 101 is less than 0.85, and the semiconductor structure 100b of the embodiment is as shown in FIG. 2I. The gate oxide layer 213 has an extension 213a at the both side edges of the isolation structure 211, and the extension portion 213a The ratio of the distance t ₄ from the top surface to the interface between the isolation structure 211 and the substrate 201 in the direction perpendicular to the surface of the substrate 201 and the thickness t ₃ of the gate oxide layer 213 on the substrate 201 is greater than 0.95, and the gate of the embodiment The top surface of the electrode oxide layer 213 is smoother than the gate oxide layer 113 of the comparative example, and has no obvious recess feature, thereby avoiding problems such as tip discharge, electrical collapse effect, and short circuit, so that the performance and reliability of the semiconductor device are improved.

The semiconductor device of the embodiment of the present disclosure is formed by a heat treatment process adjacent to the dielectric material layer at the sidewall of the trench, and between the dielectric material layer and the substrate and the pad oxide layer, before the patterned mask is removed. An oxidized portion is formed at the junction to increase the thickness of the oxide layer at the edges of the two sides of the isolation structure to be formed later, to avoid the subsequent etching process of removing the patterned mask to form a recess at the edge of the isolation structure or to reduce the size of the recess and The depth, and in turn, a gate oxide layer with a flat surface can be formed in subsequent processes to improve the gate oxide integrity (GOI).

In the prior art, since the size and depth of the recess at the edge of the isolation structure are too large, the gate oxide layer formed on the recess is thinner than the gate oxide layer on the substrate, so that the gate electrode layer is at the edge of the isolation structure and the semiconductor. The distance between the substrates is too close, and the surface curvature of the gate oxide layer and the gate electrode layer in the recess is too curved and not smooth, and problems such as tip discharge, electric collapse effect and short circuit are easily generated, and the implementation of the present disclosure The examples aim to solve these problems and improve the performance and reliability of semiconductor devices.

The above summary of several embodiments is characteristic so as to belong to the present invention Those of ordinary skill in the art may have a better understanding of the present disclosure. Those having ordinary skill in the art should understand that they can design or modify other processes and structures based on the present disclosure to achieve the same objects and/or advantages as the embodiments described herein. It is also to be understood by those of ordinary skill in the art that the invention may be practiced without departing from the spirit and scope of the disclosure. Various changes, substitutions and substitutions.

100b‧‧‧Semiconductor device

201‧‧‧Base

201a‧‧‧ top

211‧‧‧Isolation structure

212‧‧‧ dent

213‧‧‧ gate oxide layer

213a‧‧‧Extension

215‧‧ ‧ gate electrode layer

230‧‧‧ gate structure

Claims (15)

A method of forming a semiconductor device includes: forming a patterned mask on a substrate, the patterned mask comprising a pad oxide layer and a tantalum nitride layer on the pad oxide layer; via the patterned mask pair The substrate is subjected to a first etching process to form a trench; a dielectric material layer is formed in the trench and the patterned mask; and a planarization process is performed to remove the dielectric material outside the trench And performing a heat treatment process to form an oxidized portion adjacent to the dielectric material layer at an interface between the pad oxide layer and the substrate. The method of forming a semiconductor device according to claim 1, wherein the forming the dielectric material layer comprises a high density plasma chemical vapor deposition process. The method of forming a semiconductor device according to claim 1, wherein the performing the planarization process comprises a chemical mechanical polishing process. The method of forming a semiconductor device according to claim 1, wherein the temperature of the heat treatment process is in a range from 950 ° C to 1050 ° C. The method of forming a semiconductor device according to claim 1, wherein the heat treatment process has a time ranging from 15 minutes to 40 minutes. The method for forming a semiconductor device according to claim 1, further comprising: after the heat treatment process, performing a second etching process to remove the tantalum nitride layer, the pad oxide layer, and a portion of the dielectric The material layer forms an isolation structure. The method of forming a semiconductor device according to claim 7, wherein The second etching process includes a wet etching process. The method of forming a semiconductor device according to claim 7, wherein the second etching process comprises a dry etching process. The method of forming a semiconductor device according to claim 7, wherein the isolation structure is a shallow trench isolation structure. The method for forming a semiconductor device according to claim 7, further comprising: forming a gate oxide layer on the substrate and a portion of the isolation structure; and forming a gate oxide layer and the isolation structure Gate electrode layer. A semiconductor device comprising: an isolation structure formed in a substrate; a gate oxide layer formed on the substrate and a portion of the isolation structure, wherein the gate oxide layer has an extension at an edge of the isolation structure And the extension has a portion between the isolation structure and the substrate; and a gate electrode layer is formed on the gate oxide layer and the isolation structure. The semiconductor device of claim 11, wherein the isolation structure is a shallow trench isolation structure. The semiconductor device of claim 11, wherein a distance from a top surface of the extension portion to a boundary between the isolation structure and the substrate in a direction perpendicular to a surface of the substrate is greater than a gate oxide layer on the substrate The thickness of the upper. The semiconductor device of claim 11, wherein a top surface of the extension portion to a boundary between the isolation structure and the substrate is perpendicular to the substrate table The ratio of the distance in the direction of the face to the thickness of the gate oxide layer on the substrate is greater than 0.95. The semiconductor device of claim 11, wherein a distance from a top surface of the extension portion to a boundary between the isolation structure and the substrate in a direction perpendicular to the surface of the substrate is in a range from 130 Å to 500 Å.