TWI584475B - Process for forming repair layer and mos transistor having repair layer - Google Patents

Description

Repair layer forming method and gold oxide semi-transistor structure with repair layer

The present invention relates to a method for forming a repair layer and a gold oxide semi-transistor structure having a repair layer, and more particularly to a method for forming a repair layer on a sidewall surface of a gate structure and a gold layer having a repair layer on a sidewall of the gate structure Oxygen semi-transistor structure.

As the component integration requirements increase, the transistor components completed on the semiconductor wafer must be smaller and smaller, but the size reduction will seriously affect the performance of the transistor component, such as the transistor on-state current (Ion) becomes smaller and the gate Missing leakage current (Jg) is too large. Therefore, how to effectively improve the performance of the transistor component under the condition of limited size is the main purpose of the development of the present case.

The present invention provides a method of forming a repair layer, the method comprising the following steps. First, a substrate is provided having a gate structure formed over the substrate, the gate structure including at least a gate dielectric layer and a gate conductor structure. Next, a nitridation process is performed to form a nitrogen-containing surface layer on the surface of the gate structure. Next, the nitrogen-containing surface layer is subjected to thermal oxidation to form a repair layer.

In a preferred embodiment of the present invention, the material of the substrate is germanium, and the material of the gate dielectric layer is tantalum oxide, tantalum nitride or hafnium oxynitride, and the material of the gate conductor structure is polysilicon.

In a preferred embodiment of the invention, the nitridation process is a decoupled plasma nitridation process.

In a preferred embodiment of the invention, the decoupling plasma nitridation process is performed at a pressure in the range of 5 millitorr (mTorr) to 15 millitorr (mTorr) and an energy range of 1000 watts to 2400 watts. (Watt), operating time range is 25 seconds to 45 seconds.

In a preferred embodiment of the invention, the thermal oxidation process is a wet rapid thermal oxidation process or a dry rapid thermal oxidation process.

In a preferred embodiment of the invention, the thermal oxidation process has a temperature in the range of from 800 °C to 900 °C.

In a preferred embodiment of the invention, the thermal oxidation process is a furnace tube heating oxidation process.

In a preferred embodiment of the invention, the furnace tube is heated to a temperature ranging from 700 ° C to 800 ° C.

In a preferred embodiment of the invention, the repair layer has a thickness in the range of 10 angstroms ( ) to 20 angstroms ( ).

In an embodiment of the invention, the repair layer is a ruthenium oxynitride layer.

In a preferred embodiment of the present invention, the repair layer forming method further comprises the steps of: forming a first spacer on the sidewall of the repair layer; forming a sacrificial spacer on the surface of the first spacer; and forming a surface on the surface of the sacrificial spacer Two gap walls.

In an embodiment of the invention, the material of the first spacer is a thickness of 50 angstroms ( ) to 100 angstroms ( The tantalum nitride, the material of the above-mentioned sacrificial spacer has a thickness ranging from 25 angstroms ( ) to 75 angstroms ( ) yttrium oxide and a thickness range of 200 angstroms ( ) to 400 angstroms ( The total thickness of the material of the tantalum nitride and the material of the second spacer is 200 angstroms ( ) to 400 angstroms ( ).

The invention also provides a gold-oxygen semi-transistor structure, disposed above the substrate, the gold-oxygen semi-transistor structure comprises: a gate dielectric layer disposed above the substrate; and a gate conductor structure disposed above the gate dielectric layer; And the repair layer covers at least the sidewall surface of the gate conductor structure, and the repair layer is a layer of oxynitride.

In an embodiment of the invention, the material of the substrate is germanium, and the material of the gate dielectric layer is tantalum oxide, tantalum nitride or hafnium oxynitride, and the material of the gate conductor structure is polysilicon.

In an embodiment of the invention, the repair layer has a thickness in the range of 10 angstroms ( ) to 20 angstroms ( ).

In an embodiment of the invention, the nitrogen mixing ratio in the ruthenium oxynitride layer ranges from 5% to 40%.

In an embodiment of the invention, the MOS semi-transistor structure further includes a first spacer formed on the sidewall of the repair layer; and a lightly doped 汲 structure formed in the substrate, the position and the width corresponding to the first a position and a width of the spacer; a sacrificial spacer formed on the first spacer surface; and a second spacer formed on the surface of the sacrificial spacer.

In an embodiment of the invention, the material of the first spacer is a thickness of 50 angstroms ( ) to 100 angstroms ( The tantalum nitride, the material of the above-mentioned sacrificial spacer has a thickness ranging from 25 angstroms ( ) to 75 angstroms ( ) yttrium oxide and a thickness range of 200 angstroms ( ) and 400 angstroms ( The composition of the tantalum nitride, the total thickness of the material of the second spacer is 200 angstroms ( ) to 400 angstroms ( ).

In an embodiment of the invention, the MOS semi-transistor structure further comprises a source/drain structure formed in the substrate, and the material of the source/drain structure is bismuth telluride (SiGe) or tantalum carbide (SiC).

The above and other objects, features and advantages of the present invention will become more <RTIgt;

The technical means discussed herein are a method of forming a repair layer and a gold oxide semi-transistor structure having a repair layer. In order to fully understand the present invention, a gate structure will be described as an example in the following description. Obviously, the implementation of the present invention is not limited to the specific details of such a gate structure, however, for the preferred embodiment of the present invention, it will be described in detail below. The present invention may be widely practiced in other embodiments, and the scope of the present invention is not limited thereto, and may be modified and modified without departing from the spirit and scope of the invention. Therefore, the scope of patent protection of the present invention is defined by the scope of the claims appended hereto.

Please refer to FIG. 1a, which is a schematic diagram of a gate structure during the fabrication of a MOS semiconductor, mainly showing the formation of a gate dielectric layer 100, a gate conductor structure 101, and a hard mask layer 102 on a germanium substrate 1. The gate structure 10 is constructed, wherein the gate conductor structure 101 is mostly completed by polysilicon, and the hard mask layer 102 is completed by tantalum oxide, tantalum nitride or hafnium oxynitride.

Since the polysilicon is etched when the gate conductor structure 101 is defined, defects are easily generated on the sidewalls, so that the furnace tube can be used for heating before the subsequent Lightly Doped Drain (LDD) process. A reoxidation process is performed by means of a furnace oxidation method, and a re-oxidation process at a temperature of about 750 ° C is formed on the sidewall of the gate conductor structure 101 as shown in FIG. 1b. , thickness range of 10 angstroms ( ) to 20 angstroms ( The ruthenium oxide layer 1010 is mainly used to repair the defects of the surface of the polysilicon and to prevent the thickness at the interface between the gate dielectric layer 100 and the gate conductor structure 101 from becoming thick, thereby improving the performance of the device.

In addition, in order to make the performance of the component better, another embodiment is proposed in the present invention. First, as shown in FIG. 2a, the structure shown in FIG. 1a is first subjected to a decoupling plasma nitridation process for forming a gate. A sidewall of the conductor structure 101 and a surface of the substrate form a nitrogen-containing surface layer 1011. In this embodiment, the decoupled plasma Nitridation (DPN) has a pressure in the range of 5 mTorr to 15 mTorr and an energy range of 1000 watts (Watt) to 2400 Watt, operating time range of 25 seconds to 45 seconds, implants nitrogen atoms into the sidewalls of the gate conductor structure 101 to form a nitrogen-containing surface layer 1011. In this embodiment, the nitrogen-containing surface layer 1011 has a thickness in the range of 10 angstroms ( ) to 20 angstroms ( ).

Next, a thermal oxidation process is performed on the gate structure 10 on which the nitrogen-containing surface layer 1011 has been formed, thereby forming a repair layer 1012 as shown in FIG. 2b, which is mainly made of barium oxynitride and has a thickness range of 10 angstroms ( ) to 20 angstroms ( ), preferably 15 angstroms thick ( The nitrogen mixing ratio in the cerium oxynitride layer ranges from 5% to 40%. The yttrium oxynitride repair layer 1012, in addition to repairing the defects of the sidewall of the gate conductor structure 101, provides the stress required for the transistor channel more than the above ruthenium oxide layer 1010, and can be supplemented by the use of nitrogen atoms to supplement polycrystalline germanium. The depletion of the gate conductor structure 101 caused by the loss of mass diffusion. When the material of the gate dielectric layer 100 is a yttrium oxynitride layer, the repair layer 1012 is further filled with yttrium oxynitride to supplement the nitrogen atoms that may be lost by the gate dielectric layer 100, thereby improving the dielectric layer of the gate dielectric layer 100. The electrical coefficient effectively enhances the performance of the component, for example, has a better time dependent dielectric breakdown (TDDB). The thermal oxidation process may be a rapid thermal oxidation (RTO) process with an operating temperature range of 800 ° C to 900 ° C. In another embodiment of the present invention, the thermal oxidation process may also be a dry rapid thermal oxidation process with an operating temperature range of 800 ° C to 900 ° C, or a furnace tube heating oxidation process with an operating temperature range of 700 ° C. Up to 800 ° C.

Then, as shown in FIG. 2c, a first spacer 12 is formed on the sidewall of the repair layer 1012, and the first spacer 12 and the gate structure 10 are used to define the lightly doped gate structure 13 in the substrate 1. The position and width of the lightly doped gate structure 13 correspond to the position and width of the first spacer 12. A mask layer (not shown) is then utilized, such as a tantalum nitride layer, having a thickness in the range of 150 angstroms ( ) to 250 angstroms ( Forming a recess in the substrate 1 in a self-aligned etching manner, thereby causing the recess to have a spacing distance from the first spacer 12 about the thickness of the mask layer, followed by an epitaxial process of germanium telluride (SiGe) or tantalum carbide (SiC) is formed in the recess and above the surface of the substrate 1 to complete the PMOS or NMOS source/drain structure 14, and finally remove the mask layer. Next, a dummy spacer 15 is formed on the surface of the first spacer 12 and a second spacer 16 is formed on the surface of the sacrificial spacer 15. The material of the first spacer 12 is in the range of 50 angstroms ( ) to 100 angstroms ( The tantalum nitride, the sacrificial spacer 15 is comprised of a thickness range of 25 angstroms ( ) to 75 angstroms ( ) yttrium oxide and a thickness range of 200 angstroms ( ) to 400 angstroms ( a two-layer structure composed of tantalum nitride, the total thickness of the material of the second spacer 16 is 200 angstroms ( ) to 400 angstroms ( The material of the second spacer 16 may be a two-layer structure composed of yttrium oxide and tantalum nitride. Further, as shown, a surface of SiGe or SiC is covered with a cap layer 140 (Si Cap) 140.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

1. . . Substrate

10. . . Gate structure

12. . . First spacer

13. . . Lightly doped 汲 structure

14. . . Source/drain structure

15. . . Sacrificial spacer

16. . . Second spacer

100. . . Gate dielectric layer

101. . . Gate conductor structure

102. . . Hard mask layer

1010. . . Cerium oxide layer

1011. . . Nitrogen-containing surface layer

1012. . . Repair layer

140. . . Cover layer

Figure 1a: Schematic diagram of the gate structure during the fabrication of a gold oxide semi-transistor.

Figure 1b: Schematic diagram of the formation of a yttrium oxide layer to repair the gate conductor structure.

Figure 2a is a schematic view showing the formation of a nitrogen-containing surface layer on the sidewalls of the gate conductor structure and the surface of the substrate.

Figure 2b: Schematic representation of the conversion of a nitrogen-containing surface layer to a repair layer.

Figure 2c: Schematic representation of the formation of a lightly doped gate structure and a source/drain structure in a substrate.

1. . . Substrate

10. . . Gate structure

100. . . Gate dielectric layer

101. . . Gate conductor structure

102. . . Hard mask layer

1012. . . Repair layer

Claims (18)

A repair layer forming method includes the steps of: providing a substrate having a gate structure formed thereon, the gate structure comprising at least a gate dielectric layer and a gate conductor structure; performing a nitridation process Nitrogen atoms are implanted on the surface of the gate structure to form a nitrogen-containing surface layer; the nitrogen-containing surface layer is subjected to a thermal oxidation method to form a repair layer, wherein the repair layer is a single-layer structure of oxynitride layer Forming a first spacer on the sidewall of the repair layer; forming a sacrificial spacer on the surface of the first spacer; and forming a second spacer on the surface of the sacrificial spacer. The method for forming a repair layer according to claim 1, wherein the material of the substrate is germanium, and the material of the gate dielectric layer is tantalum oxide, tantalum nitride or hafnium oxynitride, and the material of the gate conductor structure. It is polycrystalline. The repair layer forming method according to claim 1, wherein the nitriding process is a decoupled plasma nitriding process. The repair layer forming method according to claim 3, wherein the decompression plasma nitriding process is performed at a pressure ranging from 5 mTorr to 15 mTorr, and 1000 watts (Watt). Up to 2400 watts (Watt), operating time range is 25 seconds to 45 seconds. The repair layer forming method according to claim 1, wherein the thermal oxidation method is a wet rapid thermal oxidation method or a dry rapid thermal oxidation method. The repair layer forming method according to claim 5, wherein the thermal oxidation method has a temperature ranging from 800 ° C to 900 ° C. The repair layer forming method according to claim 1, wherein the thermal oxidation method is a furnace tube heating oxidation method. The repair layer forming method according to claim 7, wherein the furnace tube heating oxidation method has a temperature ranging from 700 ° C to 800 ° C. The repair layer forming method according to claim 1, wherein the repair layer has a thickness ranging from 10 angstroms to 20 angstroms. The method of forming a repair layer according to claim 1, wherein the repair layer is a ruthenium oxynitride layer. The repair layer forming method according to claim 10, wherein the material of the first spacer is a tantalum nitride having a thickness ranging from 50 Å to 100 Å, and the material of the sacrificial spacer is a yttria having a thickness ranging from 25 angstroms to 75 angstroms and a tantalum nitride having a thickness ranging from 200 angstroms (Å) to 400 angstroms (Å) and a total thickness of the material of the second spacer wall ranging from 200 angstroms to 400 angstroms . A metal oxide semi-transistor structure comprising: a gate dielectric layer disposed over a substrate; a gate conductor structure disposed over the gate dielectric layer; and a repair layer formed on the gate One side wall surface of the conductor structure, the repair The layer is a layer of oxynitride, wherein a contact surface of the substrate with the gate dielectric layer and a contact surface of the substrate with the repair layer are not coplanar. The gold-oxygen semi-transistor structure according to claim 12, wherein the material of the substrate is germanium, and the material of the gate dielectric layer is tantalum oxide, tantalum nitride or hafnium oxynitride, the gate conductor structure The material is polycrystalline germanium. The gold oxide semi-transistor structure of claim 12, wherein the repair layer has a thickness ranging from 10 angstroms (Å) to 20 angstroms (Å). The gold-oxygen semi-transistor structure according to claim 12, wherein the nitrogen oxynitride layer has a nitrogen mixing ratio ranging from 5% to 40%. The gold-oxygen semi-transistor structure according to claim 12, further comprising: a first spacer formed on a sidewall surface of the repair layer; and a lightly doped gate structure formed in the substrate, The position corresponds to the width to the position and width of the first spacer; a sacrificial spacer is formed on the first spacer surface; and a second spacer is formed on the sacrificial spacer surface. The gold-oxygen semi-transistor structure according to claim 16, wherein the material of the first spacer is tantalum nitride having a thickness ranging from 50 Å to 100 Å, and the sacrificial spacer The material consists of yttrium oxide having a thickness ranging from 25 angstroms (Å) to 75 angstroms (Å) and tantalum nitride having a thickness ranging from 200 angstroms (Å) to 400 angstroms (Å), and the total material of the second spacer. The thickness ranges from 200 angstroms (Å) to 400 angstroms (Å). The gold-oxygen semi-transistor structure according to claim 12, further comprising a source/drain structure formed in the substrate, the material of the source/drain structure being germanium telluride (SiGe) or tantalum carbide (SiC).