TWI584382B - Transistor voltage suppressor diode component and method of manufacturing same - Google Patents
Transistor voltage suppressor diode component and method of manufacturing same Download PDFInfo
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Description
本發明與暫態電壓抑制有關,特別是關於一種暫態電壓抑制器(Transient Voltage Suppressor,TVS)之低電容二極體元件及其製造方法。 The present invention relates to transient voltage suppression, and more particularly to a low capacitance diode element of a Transient Voltage Suppressor (TVS) and a method of fabricating the same.
由於暫態電壓抑制器(Transient Voltage Suppressor,TVS)需要在短時間導通高電流,其元件必須具有大面積的PN接面,因此具有高的寄生電容,導致操作速度變慢。 Since the Transient Voltage Suppressor (TVS) needs to conduct a high current in a short time, its components must have a large-area PN junction, and thus have a high parasitic capacitance, resulting in a slow operation speed.
為了達到低寄生電容以提升操作速度,傳統上係採用在大面積的單向齊納二極體(Zener diode)ZD或雙向齊納二極體BZD之路徑上串接具有較小電容值的二極體D之方式來降低暫態電壓抑制器的電容,如圖1A~圖1B所示,其中圖1A~圖1B分別繪示傳統的低電容單通道單向暫態電壓抑制器及低電容單通道雙向暫態電壓抑制器之示意圖。 In order to achieve low parasitic capacitance to increase the operating speed, it is conventionally used to connect two small-capacitance values on a path of a large-area unidirectional Zener diode ZD or a bidirectional Zener diode BZD. The mode of the body D is used to reduce the capacitance of the transient voltage suppressor, as shown in FIG. 1A to FIG. 1B, wherein FIG. 1A to FIG. 1B respectively show a conventional low-capacitance single-channel unidirectional transient voltage suppressor and a low-capacitance single. Schematic diagram of a channel bidirectional transient voltage suppressor.
雖然整體電容會因而降低,但由於具有較小電容值的二極體之元件面積亦相對較小,這也導致其對於靜電放電(Electrostatic Discharge,ESD)及突波(Surge)的防護能力受此小面積的二極體所限制而相對變弱,故無法承受較大功率的能量。因此,若為了能夠承受較大功率的能量而將二 極體之面積加大,就必須選擇再串接更多的二極體D來降低電容,如圖2A~圖2B所示,圖2A~圖2B分別為傳統的低電容多通道單向暫態電壓抑制器及低電容多通道雙向暫態電壓抑制器之示意圖。 Although the overall capacitance is reduced, the component area of the diode with a smaller capacitance value is relatively small, which also causes its protection against electrostatic discharge (ESD) and surge (Surge). Small-area diodes are relatively limited and relatively weak, so they cannot withstand higher power. Therefore, if you want to be able to withstand the energy of a larger power, As the area of the polar body increases, it is necessary to select more diodes D to reduce the capacitance, as shown in Figure 2A to Figure 2B. Figures 2A to 2B show the traditional low-capacitance multi-channel unidirectional transients. Schematic diagram of a voltage suppressor and a low capacitance multi-channel bidirectional transient voltage suppressor.
圖3A~圖3B則分別繪示傳統的具有N-type基板之二極體元件的兩種不同層狀結構,以及於該二極體元件中電流路徑上的等效電容之示意圖。 3A-3B are respectively schematic diagrams showing two different layered structures of a conventional diode element having an N-type substrate, and equivalent capacitances in a current path in the diode element.
然而,一旦串接的二極體D個數愈多時,將會導致其導通阻值(On-Resistance,Ron)變得愈大,使得其對於靜電放電及突波的防護能力因而變得愈差,此一缺點尚待克服。 However, once the number of diodes D connected in series is increased, the On-Resistance (Ron) becomes larger, so that the protection against electrostatic discharge and surge becomes more and more. Poor, this shortcoming has yet to be overcome.
有鑑於此,本發明提供一種暫態電壓抑制器之二極體元件及其製造方法,以解決先前技術所述及的問題。 In view of the above, the present invention provides a diode element of a transient voltage suppressor and a method of fabricating the same to solve the problems described in the prior art.
根據本發明之一較佳具體實施例為一種暫態電壓抑制器之二極體元件。於此實施例中,該二極體元件包括一基板、一第一阱區、一第二阱區、一第一電極及一第二電極。基板具有一第一表面。第一阱區形成於基板中且鄰近第一表面。第二阱區形成於基板中且鄰近第一表面。第一阱區及第二阱區之間具有一間距。第一電極導電性連接第一阱區。第二電極導電性連接第二阱區。其中一電流路徑形成於第一電極、第一阱區、基板、第二阱區至第二電極,且電流路徑通過多個PN接面,形成多個等效電容串聯的一等效電路。 A preferred embodiment of the present invention is a diode element of a transient voltage suppressor. In this embodiment, the diode component includes a substrate, a first well region, a second well region, a first electrode, and a second electrode. The substrate has a first surface. A first well region is formed in the substrate adjacent to the first surface. A second well region is formed in the substrate adjacent to the first surface. There is a spacing between the first well region and the second well region. The first electrode is electrically connected to the first well region. The second electrode is electrically connected to the second well region. One of the current paths is formed on the first electrode, the first well region, the substrate, the second well region to the second electrode, and the current path passes through the plurality of PN junctions to form an equivalent circuit in which a plurality of equivalent capacitors are connected in series.
在本發明之一實施例中,該間距在1um到10um之間。 In an embodiment of the invention, the spacing is between 1 um and 10 um.
在本發明之一實施例中,第一電極至少部分位於第一阱 區中。 In an embodiment of the invention, the first electrode is at least partially located in the first well In the district.
在本發明之一實施例中,第一電極位於第一阱區外。 In an embodiment of the invention, the first electrode is located outside of the first well region.
在本發明之一實施例中,第一阱區與第二阱區包括一第一導電性材料,基板包括一第二導電性材料,第一阱區、第二阱區及基板形成多個PN接面。 In an embodiment of the invention, the first well region and the second well region comprise a first conductive material, the substrate comprises a second conductive material, and the first well region, the second well region and the substrate form a plurality of PNs Junction.
在本發明之一實施例中,第一阱區與第二阱區具有相同的導電型。 In an embodiment of the invention, the first well region and the second well region have the same conductivity type.
在本發明之一實施例中,第一阱區的導電型不同於第二阱區的導電型。 In an embodiment of the invention, the conductivity type of the first well region is different from the conductivity type of the second well region.
根據本發明之另一較佳具體實施例亦為一種暫態電壓抑制器之二極體元件。於此實施例中,該二極體元件包括一具有第一導電型的基板、一具有第二導電型的深阱區、一第一阱區、一第二阱區、一具有第一導電型的第一電極及一具有第二導電型的第二電極。基板具有一第一表面。深阱區形成於基板中且鄰近第一表面。第一阱區形成於深阱區中且鄰近第一表面。第二阱區形成於深阱區中且鄰近第一表面,其中第一阱區及第二阱區間具有一間距。第一電極導電性連接第一阱區。第二電極導電性連接第二阱區。一電流路徑形成於第一電極、第一阱區、深阱區、第二阱區至第二電極,且該電流路徑通過多個PN接面,形成多個等效電容串聯的一等效電路。 Another preferred embodiment of the present invention is also a diode element of a transient voltage suppressor. In this embodiment, the diode element includes a substrate having a first conductivity type, a deep well region having a second conductivity type, a first well region, a second well region, and a first conductivity type. a first electrode and a second electrode having a second conductivity type. The substrate has a first surface. A deep well region is formed in the substrate adjacent to the first surface. A first well region is formed in the deep well region adjacent to the first surface. The second well region is formed in the deep well region adjacent to the first surface, wherein the first well region and the second well region have a pitch. The first electrode is electrically connected to the first well region. The second electrode is electrically connected to the second well region. a current path is formed in the first electrode, the first well region, the deep well region, the second well region to the second electrode, and the current path passes through the plurality of PN junctions to form an equivalent circuit of the plurality of equivalent capacitors connected in series .
根據本發明之又一較佳具體實施例為暫態電壓抑制器電路之二極體元件的製造方法。於此實施例中,該製造方法包括:提供一具有第一導電型的基板;於基板中形成一第一阱區及一第二阱區,其中第一 阱區與第二阱區間具有一間距;於基板中形成具有第一導電型的一第一電極,且第一電極與第一阱區導電性接觸;於基板中形成具有第二導電型的一第二電極,且第二電極與第二阱區導電性接觸。其中,第一電極與第二電極的摻雜濃度高於第一阱區與第二阱區的雜質濃度。 According to still another preferred embodiment of the present invention, a method of fabricating a diode element of a transient voltage suppressor circuit. In this embodiment, the manufacturing method includes: providing a substrate having a first conductivity type; forming a first well region and a second well region in the substrate, wherein the first The well region and the second well region have a spacing; a first electrode having a first conductivity type is formed in the substrate, and the first electrode is in conductive contact with the first well region; and a second conductivity type is formed in the substrate a second electrode, and the second electrode is in conductive contact with the second well region. The doping concentration of the first electrode and the second electrode is higher than the impurity concentration of the first well region and the second well region.
相較於先前技術,本發明係透過改變暫態電壓抑制器中與齊納二極體(Zener diode)串接之二極體元件的架構,將其原本相連的阱區加以分開一間距,藉以達到降低二極體元件的寄生電容而又不影響其對於靜電放電及突波的防護能力的具體功效。此外,本發明還可配合不同的摻雜濃度及製程參數選擇不同的間距,藉以決定該二極體元件之型式為何。 Compared with the prior art, the present invention separates the originally connected well regions by changing the structure of the diode elements connected in series with the Zener diode in the transient voltage suppressor. The specific effect of reducing the parasitic capacitance of the diode element without affecting its ability to protect against electrostatic discharge and surge is achieved. In addition, the present invention can also select different spacings according to different doping concentrations and process parameters, thereby determining the type of the diode component.
關於本發明之優點與精神可以藉由以下的發明詳述及所附圖式得到進一步的瞭解。 The advantages and spirit of the present invention will be further understood from the following detailed description of the invention.
ZD‧‧‧單向齊納二極體 ZD‧‧ unidirectional Zener diode
BZD‧‧‧雙向齊納二極體 BZD‧‧‧Two-way Zener diode
D‧‧‧二極體元件 D‧‧‧ diode components
UD、DD‧‧‧低電容二極體元件 UD, DD‧‧‧ low capacitance diode components
sub‧‧‧基板 Sub‧‧‧substrate
EL1、EL2‧‧‧電極 EL1, EL2‧‧‧ electrodes
P+、N+‧‧‧高濃度摻雜層 P+, N+‧‧‧ high concentration doping layer
P-、N-‧‧‧低濃度摻雜層 P-, N-‧‧‧ low concentration doping layer
4A~4B、5A~5B、6、7‧‧‧低電容二極體元件 4A~4B, 5A~5B, 6, 7‧‧‧Low Capacitance Diode Components
DR、DR1~DR2‧‧‧阱區 DR, DR1~DR2‧‧‧ well area
DR3‧‧‧深阱區 DR3‧‧‧ Deep Well Area
d、d1~d2‧‧‧間距 d, d1~d2‧‧‧ spacing
8A~8B、11、12A~12B‧‧‧低電容多通道暫態電壓抑制器 8A~8B, 11, 12A~12B‧‧‧ Low capacitance multi-channel transient voltage suppressor
P、I、G‧‧‧接腳 P, I, G‧‧‧ feet
IN‧‧‧輸入電流 IN‧‧‧Input current
OUT‧‧‧輸出電流 OUT‧‧‧Output current
SF‧‧‧表面 SF‧‧‧ surface
S10~S14‧‧‧步驟 S10~S14‧‧‧Steps
圖1A~圖1B分別繪示傳統的低電容單通道單向暫態電壓抑制器及低電容單通道雙向暫態電壓抑制器之示意圖。 1A-1B are schematic diagrams showing a conventional low-capacitance single-channel unidirectional transient voltage suppressor and a low-capacitance single-channel bidirectional transient voltage suppressor.
圖2A~圖2B分別繪示傳統的低電容多通道單向暫態電壓抑制器及低電容多通道雙向暫態電壓抑制器之示意圖。 2A-2B are schematic diagrams showing a conventional low-capacitance multi-channel unidirectional transient voltage suppressor and a low-capacitance multi-channel bidirectional transient voltage suppressor.
圖3A~圖3B分別繪示傳統的具有N-type基板之二極體元件的兩種不同層狀結構,以及於該二極體元件中電流路徑上的等效電容之示意圖。 3A-3B are respectively schematic diagrams showing two different layered structures of a conventional diode element having an N-type substrate, and equivalent capacitances in a current path in the diode element.
圖4A~圖4B分別繪示本發明一實施例之暫態電壓抑制器的低電容二極體元件的層狀結構,以及於該低電容二極體元件中電流路徑上 的等效電容之示意圖。 4A-4B illustrate a layered structure of a low capacitance diode element of a transient voltage suppressor according to an embodiment of the present invention, and a current path in the low capacitance diode element. Schematic diagram of the equivalent capacitance.
圖5A~5B分別繪示本發明另一實施例之暫態電壓抑制器的低電容二極體元件的層狀結構,以及於該低電容二極體元件中電流路徑上的等效電容之示意圖。 5A-5B are respectively a layered structure of a low capacitance diode element of a transient voltage suppressor according to another embodiment of the present invention, and a schematic diagram of an equivalent capacitance in a current path of the low capacitance diode element. .
圖6繪示當阱區DR1與阱區DR2間具有較小的間距d1之示意圖,當暫態電壓經過此結構時,d1會因阱區擴散而導通形成擊穿二極體(Punch-through Diode)元件。 6 is a schematic diagram showing a small spacing d1 between the well region DR1 and the well region DR2. When the transient voltage passes through the structure, d1 is turned on by the well region to form a breakdown diode (Punch-through Diode). )element.
圖7繪示當阱區DR1與阱區DR2間具有較大的間距d2之示意圖,當暫態電壓經過此結構時,阱區即使擴散但彼此仍不導通,而形成閘流體(Thyristor)元件。 FIG. 7 is a schematic diagram showing a large spacing d2 between the well region DR1 and the well region DR2. When the transient voltage passes through the structure, the well regions are not conductive even if they diffuse, forming a thyristor element.
圖8A~圖8B分別繪示本發明所揭露之低電容多通道單向暫態電壓抑制器及低電容多通道雙向暫態電壓抑制器之電路示意圖。 8A-8B are circuit diagrams showing a low capacitance multi-channel unidirectional transient voltage suppressor and a low capacitance multi-channel bidirectional transient voltage suppressor according to the present invention.
圖9繪示圖8A之低電容多通道單向暫態電壓抑制器的層狀結構之示意圖。 9 is a schematic diagram showing the layered structure of the low capacitance multi-channel unidirectional transient voltage suppressor of FIG. 8A.
圖10A~圖10B分別繪示圖8之低電容多通道單向暫態電壓抑制器的正向電流路徑及負向電流路徑。 10A-10B illustrate the forward current path and the negative current path of the low capacitance multi-channel unidirectional transient voltage suppressor of FIG. 8, respectively.
圖11繪示阱區DR1與阱區DR2電性相異之示意圖。 FIG. 11 is a schematic diagram showing that the well region DR1 and the well region DR2 are electrically different.
圖12A繪示低電容二極體元件UD中之部分的電極EL1位於阱區DR1中而彼此導電性連接之示意圖。 FIG. 12A is a schematic diagram showing that the electrodes EL1 of a portion of the low capacitance diode element UD are electrically connected to each other in the well region DR1.
圖12B繪示低電容二極體元件UD中之電極EL1位於阱區DR1外而彼此導電性連接之示意圖。 FIG. 12B is a schematic diagram showing that the electrodes EL1 in the low capacitance diode element UD are outside the well region DR1 and are electrically connected to each other.
圖13繪示根據本發明之另一較佳具體實施例的暫態電壓 抑制器電路之二極體元件的製造方法之流程圖。 FIG. 13 illustrates a transient voltage according to another preferred embodiment of the present invention. A flow chart of a method of fabricating a diode element of a suppressor circuit.
現在將詳細參考本發明的示範性實施例,並在附圖中說明所述示範性實施例的實例。另外,在圖式及實施方式中所使用相同或類似標號的元件/構件是用來代表相同或類似部分。在下述諸實施例中,當元件被指為「摻雜濃度高於」另一元件時,其比較標的為相同導電性摻雜物的濃度。 Reference will now be made in detail to the exemplary embodiments embodiments In addition, the same or similar elements or components are used in the drawings and the embodiments to represent the same or similar parts. In the embodiments described below, when an element is referred to as having a "doping concentration higher than" another element, it is compared to the concentration of the same conductive dopant.
請參照圖4A~圖4B,圖4A~圖4B分別繪示暫態電壓抑制器之低電容二極體元件的兩種不同層狀結構之示意圖。 Please refer to FIG. 4A to FIG. 4B . FIG. 4A to FIG. 4B are schematic diagrams showing two different layered structures of the low capacitance diode element of the transient voltage suppressor.
如圖4A所示,二極體元件4A包括具有第一導電性材料例如為N-type材料的基板sub、具有第二導電性材料例如為P-type材料的阱區DR1~DR2、做為輸入電極的P-type重摻雜區例如為EL1及做為輸出電極的N-type重摻雜區例如為EL2。基板sub具有一表面SF。阱區DR1~DR2形成於基板sub中且鄰近基板sub的表面SF。輸入電極EL1導電性連接阱區DR1且輸出電極EL2導電性連接阱區DR2。電極EL1及EL2均鄰近基板sub的表面SF。阱區DR1與阱區DR2之間具有一間距d,而不會彼此導電性連接。於實際應用中,阱區DR1與阱區DR2間之間距d可以是1um到10um之間,但不以此為限。 As shown in FIG. 4A, the diode element 4A includes a substrate sub having a first conductive material such as an N-type material, and well regions DR1 to DR2 having a second conductive material such as a P-type material as an input. The P-type heavily doped region of the electrode is, for example, EL1 and the N-type heavily doped region as an output electrode is, for example, EL2. The substrate sub has a surface SF. The well regions DR1 to DR2 are formed in the substrate sub and adjacent to the surface SF of the substrate sub. The input electrode EL1 is electrically connected to the well region DR1 and the output electrode EL2 is electrically connected to the well region DR2. The electrodes EL1 and EL2 are both adjacent to the surface SF of the substrate sub. The well region DR1 and the well region DR2 have a spacing d between them and are not electrically connected to each other. In practical applications, the distance d between the well region DR1 and the well region DR2 may be between 1 um and 10 um, but not limited thereto.
需注意的是,於輸入電極EL1、阱區DR1、基板sub、阱區DR2及輸出電極EL2間會形成有一電流路徑,並且電流路徑會通過多個PN接面,形成多個等效電容串聯的等效電路。 It should be noted that a current path is formed between the input electrode EL1, the well region DR1, the substrate sub, the well region DR2, and the output electrode EL2, and the current path passes through a plurality of PN junctions to form a plurality of equivalent capacitors connected in series. Equivalent Circuit.
以此實施例而言,由於該電流路徑依序通過了阱區DR1 與基板sub間之PN接面、基板sub與阱區DR2間之PN接面以及阱區DR2與電極EL2間之PN接面,並且每個PN接面均具有一等效電容,故可形成一具有三個等效電容串聯的等效電路。 In this embodiment, the current path sequentially passes through the well region DR1. a PN junction between the substrate sub, a PN junction between the substrate sub and the well DR2, and a PN junction between the well DR2 and the electrode EL2, and each PN junction has an equivalent capacitance, so that a An equivalent circuit with three equivalent capacitors in series.
於實際應用中,阱區DR1與DR2可以於同一道製程形成並可具有相同導電型(same conductive type),例如阱區DR1及DR2均為P-type或均為N-type。電極EL1~EL2的摻雜濃度會高於阱區DR1~DR2的摻雜濃度。 In practical applications, the well regions DR1 and DR2 may be formed in the same process and may have the same conductive type. For example, the well regions DR1 and DR2 are both P-type or N-type. The doping concentration of the electrodes EL1 to EL2 is higher than the doping concentration of the well regions DR1 to DR2.
同理,如圖4B所示,二極體元件4B包括具有第一導電性材料例如為N-type材料的基板sub、具有第一導電性材料例如為N-type材料的阱區DR1~DR2、P-type深阱區(deep well)DR3、做為輸入電極的P-type重摻雜區例如為EL1及做為輸出電極的N-type重摻雜區例如為EL2。基板sub具有一表面SF。深阱區DR3形成於基板sub中且鄰近基板sub的表面SF。N-type阱區DR1形成於深阱區DR3中且鄰近基板sub的表面SF。阱區DR2形成於深阱區DR3中且鄰近基板sub的表面SF。輸入電極EL1導電性連接阱區DR1且輸出電極EL2導電性連接阱區DR2。電極EL1及EL2均鄰近基板sub的表面SF。阱區DR1與DR2間具有一間距d,而不會彼此導電性連接。於實際應用中,阱區DR1與阱區DR2間之間距d可以是1um到10um之間,但不以此為限。 Similarly, as shown in FIG. 4B, the diode element 4B includes a substrate sub having a first conductive material such as an N-type material, and well regions DR1 to DR2 having a first conductive material such as an N-type material. The P-type deep well DR3, the P-type heavily doped region as the input electrode is, for example, EL1 and the N-type heavily doped region as the output electrode is, for example, EL2. The substrate sub has a surface SF. The deep well region DR3 is formed in the substrate sub and adjacent to the surface SF of the substrate sub. The N-type well region DR1 is formed in the deep well region DR3 and adjacent to the surface SF of the substrate sub. The well region DR2 is formed in the deep well region DR3 and adjacent to the surface SF of the substrate sub. The input electrode EL1 is electrically connected to the well region DR1 and the output electrode EL2 is electrically connected to the well region DR2. The electrodes EL1 and EL2 are both adjacent to the surface SF of the substrate sub. The well regions DR1 and DR2 have a spacing d between them and are not electrically connected to each other. In practical applications, the distance d between the well region DR1 and the well region DR2 may be between 1 um and 10 um, but not limited thereto.
需注意的是,於電極EL1、阱區DR1、深阱區DR3、阱區DR2及電極EL2間會形成有一電流路徑,並且電流路徑會通過多個PN接面,而形成多個等效電容串聯的等效電路。 It should be noted that a current path is formed between the electrode EL1, the well region DR1, the deep well region DR3, the well region DR2, and the electrode EL2, and the current path passes through the plurality of PN junctions to form a plurality of equivalent capacitors in series. Equivalent circuit.
以此實施例而言,該電流路徑依序通過了電極EL1與阱區DR1間之PN接面、阱區DR1與深阱區DR3間之PN接面以及深阱區DR3與阱 區DR2間之PN接面,每個PN接面都具有一等效電容,形成一具有三個等效電容串聯的等效電路。 In this embodiment, the current path sequentially passes through the PN junction between the electrode EL1 and the well region DR1, the PN junction between the well region DR1 and the deep well region DR3, and the deep well region DR3 and the well. The PN junction between the regions DR2, each PN junction has an equivalent capacitance, forming an equivalent circuit with three equivalent capacitors in series.
於實際應用中,阱區DR1與DR2可以於同一道製程形成並可具有相同導電型,例如阱區DR1及DR2均為P-type或均為N-type。電極EL1與EL2的摻雜濃度會高於阱區DR1與DR2及深阱區DR3的摻雜濃度。此外,深阱區DR3的導電型不同於基板sub及阱區DR1~DR2,也就是說,當基板sub及阱區DR1~DR2的導電型例如均為N-type時,深阱區DR3的導電型應為P-type。 In practical applications, the well regions DR1 and DR2 may be formed in the same process and may have the same conductivity type. For example, the well regions DR1 and DR2 are both P-type or N-type. The doping concentrations of the electrodes EL1 and EL2 are higher than the doping concentrations of the well regions DR1 and DR2 and the deep well region DR3. In addition, the conductivity type of the deep well region DR3 is different from that of the substrate sub and the well regions DR1 to DR2, that is, when the conductivity types of the substrate sub and the well regions DR1 to DR2 are both N-type, the conduction of the deep well region DR3 The type should be P-type.
請參照圖5A~圖5B,圖5A~圖5B分別繪示暫態電壓抑制器之低電容二極體元件另一實施例的兩種不同層狀結構之示意圖。 Please refer to FIG. 5A to FIG. 5B . FIG. 5A to FIG. 5B are schematic diagrams showing two different layered structures of another embodiment of the low capacitance diode element of the transient voltage suppressor.
於另一實際應用中,阱區DR1與DR2具有不同的導電型,如圖5A所示,二極體元件5A包括具有第二導電性材料例如為P-type的基板sub、具有第一導電性材料例如為N-type材料的深阱區、N-type阱區DR1、P-type阱區DR2、做為輸入電極的P-type重摻雜區例如為EL1及做為輸出電極的N-type重摻雜區例如為EL2。基板sub具有一表面SF。N-type阱區DR1形成於基板sub中且鄰近基板sub的表面SF。P-type阱區DR2形成於基板sub中且鄰近基板sub的表面SF。輸入電極EL1導電性連接N-type阱區DR1且輸出電極EL2導電性連接P-type阱區DR2。電極EL1及EL2均鄰近基板sub的表面SF。N-type阱區DR1與P-type阱區DR2之間具有一間距d,而不會彼此導電性連接。於實際應用中,N-type阱區DR1與P-type阱區DR2間之間距d可以是1um到10um之間,但不以此為限。 In another practical application, the well regions DR1 and DR2 have different conductivity types. As shown in FIG. 5A, the diode element 5A includes a substrate sub having a second conductive material such as a P-type, having a first conductivity. The material is, for example, a deep well region of an N-type material, an N-type well region DR1, a P-type well region DR2, and a P-type heavily doped region as an input electrode, such as EL1 and an N-type as an output electrode. The heavily doped region is, for example, EL2. The substrate sub has a surface SF. The N-type well region DR1 is formed in the substrate sub and adjacent to the surface SF of the substrate sub. The P-type well region DR2 is formed in the substrate sub and adjacent to the surface SF of the substrate sub. The input electrode EL1 is electrically connected to the N-type well region DR1 and the output electrode EL2 is electrically connected to the P-type well region DR2. The electrodes EL1 and EL2 are both adjacent to the surface SF of the substrate sub. The N-type well region DR1 and the P-type well region DR2 have a spacing d between them and are not electrically connected to each other. In practical applications, the distance d between the N-type well region DR1 and the P-type well region DR2 may be between 1 um and 10 um, but not limited thereto.
需注意的是,於輸入電極EL1、阱區DR1、基板sub、阱區 DR2及輸出電極EL2間會形成有一電流路徑,並且電流路徑會通過多個PN接面,形成多個等效電容串聯的等效電路。 It should be noted that the input electrode EL1, the well region DR1, the substrate sub, and the well region A current path is formed between the DR2 and the output electrode EL2, and the current path passes through a plurality of PN junctions to form an equivalent circuit in which a plurality of equivalent capacitors are connected in series.
以此實施例而言,該電流路徑依序通過了輸入電極EL1與阱區DR1間之PN接面、深阱區DR3與阱區DR2間之PN接面以及阱區DR2與輸出電極EL2間之PN接面,每個PN接面都具有一等效電容,形成一具有三個等效電容串聯的等效電路。 In this embodiment, the current path sequentially passes between the PN junction between the input electrode EL1 and the well region DR1, the PN junction between the deep well region DR3 and the well region DR2, and between the well region DR2 and the output electrode EL2. The PN junction, each PN junction has an equivalent capacitance, forming an equivalent circuit with three equivalent capacitors in series.
同理,如圖5B所示,二極體元件5B包括具有第二導電性材料例如為P-type材料的基板sub、具有第一導電性材料例如為N-type材料的阱區DR1、P-type阱區DR2、做為輸入電極的P-type重摻雜區例如為EL1及做為輸出電極的N-type重摻雜區例如為EL2。P-type基板sub具有一表面SF。阱區DR1~DR2形成於基板sub中且鄰近該表面SF。輸入電極EL1導電性連接阱區DR1且輸出電極EL2導電性連接阱區DR2。電極EL1及EL2均鄰近基板sub的表面SF。阱區DR1與DR2間具有一間距d,而不會彼此導電性連接。於實際應用中,阱區DR1與阱區DR2間之間距d可以是1um到10um之間,但不以此為限。 Similarly, as shown in FIG. 5B, the diode element 5B includes a substrate sub having a second conductive material such as a P-type material, and well regions DR1, P- having a first conductive material such as an N-type material. The type well region DR2, the P-type heavily doped region as the input electrode is, for example, EL1 and the N-type heavily doped region as the output electrode is, for example, EL2. The P-type substrate sub has a surface SF. The well regions DR1 to DR2 are formed in the substrate sub and adjacent to the surface SF. The input electrode EL1 is electrically connected to the well region DR1 and the output electrode EL2 is electrically connected to the well region DR2. The electrodes EL1 and EL2 are both adjacent to the surface SF of the substrate sub. The well regions DR1 and DR2 have a spacing d between them and are not electrically connected to each other. In practical applications, the distance d between the well region DR1 and the well region DR2 may be between 1 um and 10 um, but not limited thereto.
需說明的是,本發明還可根據不同的摻雜濃度及製程參數來改變上述阱區DR1與DR2間之間距d,藉以決定當暫態電壓通過此二極體元件時,等效為不同型式的半導體元件,例如擊穿二極體(Punch-through Diode)元件或閘流體(Thyristor)元件,但不以此為限。 It should be noted that, according to different doping concentrations and process parameters, the present invention can also change the distance d between the well regions DR1 and DR2, thereby determining that when the transient voltage passes through the diode component, the equivalent is different. The semiconductor component, such as a Punch-through Diode component or a Thyristor component, is not limited thereto.
舉例而言,如圖6所示,假設阱區DR1與DR2之間具有較小的間距d1(例如1um),當一暫態電壓通過元件6時,阱區DR1與DR2將會向外擴散而使得間距d1變小,最後阱區DR1與DR2會彼此導電性連接, 元件6形成擊穿二極體元件;如圖7所示,假設阱區DR1與DR2之間具有較大的間距d2(例如10um),當暫態電壓通過元件7時,阱區DR1與DR2雖會向外擴散而使得間距d2變小,但由於間距d2較大,所以阱區DR1與DR2無法彼此導電性連接,元件7形成類似矽控整流器(SCR)的閘流體元件,以上僅為舉例,但不以此為限。 For example, as shown in FIG. 6, assuming a small spacing d1 (eg, 1 um) between the well regions DR1 and DR2, when a transient voltage passes through the component 6, the well regions DR1 and DR2 will diffuse outward. The spacing d1 is made smaller, and finally the well regions DR1 and DR2 are electrically connected to each other. The element 6 forms a breakdown diode element; as shown in FIG. 7, assuming a large spacing d2 (for example, 10 um) between the well regions DR1 and DR2, when the transient voltage passes through the element 7, the well regions DR1 and DR2 are It will spread out to make the spacing d2 smaller, but because the spacing d2 is larger, the well regions DR1 and DR2 cannot be electrically connected to each other, and the element 7 forms a thyristor element similar to a controlled rectifier (SCR), which is only an example. But not limited to this.
接著,請參照圖8A~圖8B,圖8A~圖8B分別繪示本發明所揭露之低電容多通道單向暫態電壓抑制器及低電容多通道雙向暫態電壓抑制器之電路示意圖。 Next, please refer to FIG. 8A to FIG. 8B . FIG. 8A to FIG. 8B are respectively schematic diagrams showing the circuit of the low-capacitance multi-channel unidirectional transient voltage suppressor and the low-capacitance multi-channel bidirectional transient voltage suppressor according to the present invention.
如圖8A所示,低電容多通道單向暫態電壓抑制器8A包括單向齊納二極體ZD與彼此串接的低電容二極體元件UD與DD。其中,單向齊納二極體ZD之兩端分別耦接至接腳P及接腳G;低電容二極體元件UD之兩端分別耦接至接腳P及低電容二極體元件DD;低電容二極體元件DD之兩端分別耦接至低電容二極體元件UD及接腳G;接腳I耦接至低電容二極體元件UD與DD之間。 As shown in FIG. 8A, the low capacitance multi-channel unidirectional transient voltage suppressor 8A includes a unidirectional Zener diode ZD and low capacitance diode elements UD and DD connected in series with each other. The two ends of the unidirectional Zener diode ZD are respectively coupled to the pin P and the pin G; the two ends of the low capacitance diode element UD are respectively coupled to the pin P and the low capacitance diode element DD The two ends of the low-capacitance diode element DD are respectively coupled to the low-capacitance diode element UD and the pin G; the pin I is coupled between the low-capacitance diode elements UD and DD.
如圖8B所示,低電容多通道雙向暫態電壓抑制器8B包括雙向齊納二極體BZD與彼此串接的低電容二極體元件UD與DD。其中,雙向齊納二極體BZD之兩端分別耦接至接腳P及接腳G;低電容二極體元件UD之兩端分別耦接至接腳P及低電容二極體元件DD;低電容二極體元件DD之兩端分別耦接至低電容二極體元件UD及接腳G;接腳I耦接至低電容二極體元件UD與DD之間。 As shown in FIG. 8B, the low capacitance multi-channel bidirectional transient voltage suppressor 8B includes bidirectional Zener diodes BZD and low capacitance diode elements UD and DD connected in series with each other. The two ends of the bidirectional Zener diode BZD are respectively coupled to the pin P and the pin G; the two ends of the low capacitance diode element UD are respectively coupled to the pin P and the low capacitance diode element DD; The two ends of the low-capacitance diode element DD are respectively coupled to the low-capacitance diode element UD and the pin G; the pin I is coupled between the low-capacitance diode elements UD and DD.
接下來,將透過圖9為例來詳細說明圖8A之低電容多通道單向暫態電壓抑制器8A的層狀結構。 Next, the layered structure of the low capacitance multi-channel unidirectional transient voltage suppressor 8A of FIG. 8A will be described in detail through FIG. 9 as an example.
如圖9所示,單向齊納二極體ZD、低電容二極體元件UD及DD均形成於N-type基板sub中。接腳G分別耦接至單向齊納二極體ZD及低電容二極體元件DD;接腳I分別耦接至低電容二極體元件UD及DD;接腳P分別耦接至低電容二極體元件UD及單向齊納二極體ZD。 As shown in FIG. 9, the unidirectional Zener diode ZD, the low capacitance diode elements UD and DD are all formed in the N-type substrate sub. The pin G is coupled to the one-way Zener diode ZD and the low-capacitance diode element DD, respectively; the pin I is coupled to the low-capacitance diode elements UD and DD, respectively; the pin P is coupled to the low capacitance respectively The diode element UD and the one-way Zener diode ZD.
於此實施例中,單向齊納二極體ZD包括有阱區DR以及形成於阱區DR中之電極EL1~EL3,其中電極EL2與EL3彼此導電性連接而與電極EL1間隔設置。 In this embodiment, the unidirectional Zener diode ZD includes a well region DR and electrodes EL1 to EL3 formed in the well region DR, wherein the electrodes EL2 and EL3 are electrically connected to each other and spaced apart from the electrode EL1.
低電容二極體元件UD包括有彼此間隔設置的阱區DR1與DR2以及分別與阱區DR1與DR2導電性連接的電極EL1與EL2,其中電極EL2與阱區DR2電性相異,且阱區DR1與DR2間具有一間距d1。 The low capacitance diode element UD includes well regions DR1 and DR2 spaced apart from each other and electrodes EL1 and EL2 electrically connected to the well regions DR1 and DR2, respectively, wherein the electrode EL2 and the well region DR2 are electrically different, and the well region There is a distance d1 between DR1 and DR2.
低電容二極體元件DD包括有深阱區DR3、形成於深阱區DR3中且彼此間隔設置的阱區DR1與DR2以及分別與阱區DR1與DR2導電性連接的電極EL1與EL2,其中阱區DR1與深阱區DR3電性相異阱區DR2與深阱區DR3電性相異。電極EL1與阱區DR1電性相異,且阱區DR1與DR2間具有一間距d2。 The low capacitance diode element DD includes deep well regions DR3, well regions DR1 and DR2 formed in the deep well region DR3 and spaced apart from each other, and electrodes EL1 and EL2 electrically connected to the well regions DR1 and DR2, respectively, wherein the wells The region DR1 and the deep well region DR3 electrically different well region DR2 are electrically different from the deep well region DR3. The electrode EL1 is electrically different from the well region DR1, and has a pitch d2 between the well regions DR1 and DR2.
由圖9可知:接腳G分別耦接至單向齊納二極體ZD中之彼此導電性連接的電極EL2與EL3以及低電容二極體元件DD中之電極EL1;接腳I分別耦接至低電容二極體元件UD中之電極EL1及低電容二極體元件DD中之電極EL2;接腳P分別耦接至低電容二極體元件UD中之電極EL2及單向齊納二極體ZD中之電極EL1。 It can be seen from FIG. 9 that the pins G are respectively coupled to the electrodes EL2 and EL3 electrically connected to each other in the one-way Zener diode ZD and the electrodes EL1 in the low capacitance diode element DD; the pins I are respectively coupled The electrode EL1 in the low capacitance diode element UD and the electrode EL2 in the low capacitance diode element DD; the pin P is respectively coupled to the electrode EL2 and the one-way Zener diode in the low capacitance diode element UD Electrode EL1 in body ZD.
接著,將分別透過圖10A~圖10B來說明圖9中之低電容多通道單向暫態電壓抑制器8A的正向電流路徑及負向電流路徑。 Next, the forward current path and the negative current path of the low capacitance multi-channel unidirectional transient voltage suppressor 8A of FIG. 9 will be described with reference to FIGS. 10A to 10B, respectively.
如圖9及圖10A所示,對低電容多通道單向暫態電壓抑制器8A而言,正向電流路徑係指輸入電流IN透過接腳I進入低電容多通道單向暫態電壓抑制器8A,並且最後是透過接腳G將輸出電流OUT加以輸出。當輸入電流IN從接腳I進入低電容二極體元件UD後會依序流經低電容二極體元件UD中之電極EL1、阱區DR1、N-type基板sub、阱區DR2及電極EL2後流入單向齊納二極體ZD,然後再依序流經單向齊納二極體ZD中之電極EL1、阱區DR及電極EL3後流向接腳G,並由接腳G將輸出電流OUT加以輸出。也就是說,此實施例中之低電容多通道單向暫態電壓抑制器8A的正向電流路徑係以低電容二極體元件UD的電極EL1作為電輸入端並以單向齊納二極體ZD的電極EL3作為電輸出端,但不以此為限。 As shown in FIG. 9 and FIG. 10A, for the low capacitance multi-channel unidirectional transient voltage suppressor 8A, the forward current path refers to the input current IN through the pin I into the low capacitance multi-channel unidirectional transient voltage suppressor. 8A, and finally, the output current OUT is output through the pin G. When the input current IN enters the low-capacitance diode element UD from the pin I, it sequentially flows through the electrode EL1 in the low-capacitance diode element UD, the well region DR1, the N-type substrate sub, the well region DR2, and the electrode EL2. After flowing into the one-way Zener diode ZD, it then flows through the electrode EL1, the well region DR and the electrode EL3 in the one-way Zener diode ZD, and then flows to the pin G, and the output current is output by the pin G. OUT is output. That is, the forward current path of the low-capacitance multi-channel unidirectional transient voltage suppressor 8A in this embodiment is an electrode EL1 of the low-capacitance diode element UD as an electric input terminal and a one-way Zener diode The electrode EL3 of the body ZD serves as an electrical output, but is not limited thereto.
如圖9及圖10B所示,對低電容多通道單向暫態電壓抑制器8A而言,負向電流路徑係指輸入電流IN透過接腳G進入低電容多通道單向暫態電壓抑制器8A,並且最後是透過接腳I將輸出電流OUT加以輸出。當輸入電流IN從接腳G進入低電容二極體元件DD後會依序流經低電容二極體元件DD中之電極EL1、阱區DR1、深阱區DR3、阱區DR2及電極EL2後流向接腳I,並由接腳I將輸出電流OUT加以輸出。也就是說,此實施例中之低電容多通道單向暫態電壓抑制器8A的負向電流路徑係以低電容二極體元件DD的電極EL1作為電輸入端並以低電容二極體元件DD的電極EL2作為電輸出端,但不以此為限。 As shown in FIG. 9 and FIG. 10B, for the low-capacitance multi-channel unidirectional transient voltage suppressor 8A, the negative current path means that the input current IN passes through the pin G and enters the low-capacitance multi-channel unidirectional transient voltage suppressor. 8A, and finally the output current OUT is output through the pin I. When the input current IN enters the low-capacitance diode element DD from the pin G, it will sequentially flow through the electrode EL1 in the low-capacitance diode element DD, the well region DR1, the deep well region DR3, the well region DR2, and the electrode EL2. It flows to pin I, and the output current OUT is output by pin 1. That is to say, the negative current path of the low capacitance multi-channel unidirectional transient voltage suppressor 8A in this embodiment is the electrode EL1 of the low capacitance diode element DD as the electric input terminal and the low capacitance diode element. The electrode EL2 of the DD is used as an electrical output, but is not limited thereto.
需說明的是,除了圖9所繪示的低電容二極體元件DD中之阱區DR1及DR2電性相同的實施例之外,圖11則繪示了低電容多通道暫態電壓抑制器11中之低電容二極體元件DD的阱區DR1及DR2電性相異的實 施例。也就是說,本發明的暫態電壓抑制器中之低電容二極體元件中之阱區DR1及DR2間具有一間距且兩者之電性可以彼此相同或相異,並無特定之限制。 It should be noted that, in addition to the embodiment in which the well regions DR1 and DR2 in the low-capacitance diode device DD shown in FIG. 9 are electrically identical, FIG. 11 illustrates the low-capacitance multi-channel transient voltage suppressor. The well regions DR1 and DR2 of the low-capacitance diode element DD of 11 are electrically different Example. That is, the well regions DR1 and DR2 in the low capacitance diode device of the transient voltage suppressor of the present invention have a pitch therebetween and the electrical properties of the two may be the same or different from each other, and are not particularly limited.
此外,除了圖9所繪示的低電容二極體元件UD中之電極EL1形成於阱區DR1中的實施例之外,圖12A則繪示了低電容多通道暫態電壓抑制器12A中之低電容二極體元件UD僅有部分的電極EL1位於阱區DR1中而彼此導電性連接的實施例,而圖12B繪示了低電容多通道暫態電壓抑制器12B中之低電容二極體元件UD的電極EL1位於阱區DR1外而彼此導電性連接的實施例。也就是說,本發明的暫態電壓抑制器中之低電容二極體元件的電極EL1與阱區DR1(或電極EL2與阱區DR2)只要能夠彼此導電性連接即可,至於兩者彼此導電性連接的型式可以是電極EL1形成於阱區DR1中(或電極EL2形成於阱區DR2中)、部分的電極EL1位於阱區DR1中且部分的電極EL1位於阱區DR1外(或部分的電極EL2位於阱區DR2中且部分的電極EL2位於阱區DR2外)、或電極EL1位於阱區DR1外而彼此導電性連接(或電極EL2位於阱區DR2外而彼此導電性連接),並無特定之限制。 In addition, in addition to the embodiment in which the electrode EL1 in the low capacitance diode element UD is formed in the well region DR1, FIG. 12A illustrates the low capacitance multi-channel transient voltage suppressor 12A. The low-capacitance diode element UD has only a part of the electrodes EL1 located in the well region DR1 and electrically connected to each other, and FIG. 12B shows the low-capacitance diode in the low-capacitance multi-channel transient voltage suppressor 12B. The electrode EL1 of the element UD is located outside the well region DR1 and is electrically connected to each other. That is, the electrode EL1 and the well region DR1 (or the electrode EL2 and the well region DR2) of the low capacitance diode element in the transient voltage suppressor of the present invention can be electrically connected to each other as long as they are electrically conductive to each other. The pattern of the connection may be that the electrode EL1 is formed in the well region DR1 (or the electrode EL2 is formed in the well region DR2), a portion of the electrode EL1 is located in the well region DR1, and a portion of the electrode EL1 is located outside the well region DR1 (or a portion of the electrode) EL2 is located in the well region DR2 and part of the electrode EL2 is located outside the well region DR2), or the electrode EL1 is located outside the well region DR1 and is electrically connected to each other (or the electrode EL2 is outside the well region DR2 and is electrically connected to each other), and is not specified The limit.
根據本發明之另一較佳具體實施例為暫態電壓抑制器電路之二極體元件的製造方法。如圖13所示,首先,於步驟S10中,該製造方法提供一基板;接著,於步驟S12中,該製造方法於基板中形成一第一阱區及一第二阱區,且第一阱區與第二阱區間具有一間距。 Another preferred embodiment of the present invention is a method of fabricating a diode element of a transient voltage suppressor circuit. As shown in FIG. 13, first, in step S10, the manufacturing method provides a substrate; then, in step S12, the manufacturing method forms a first well region and a second well region in the substrate, and the first well The zone has a spacing from the second well zone.
於實際應用中,第一阱區與第二阱區之間距較佳為1um到10um之間,但不以此為限。此外,第一阱區及第二阱區可以於同一道製程形成且具有相同導電型,或是第一阱區及第二阱區分別於不同道製程 形成且具有不同導電型,並無特定之限制。 In practical applications, the distance between the first well region and the second well region is preferably between 1 um and 10 um, but not limited thereto. In addition, the first well region and the second well region may be formed in the same process and have the same conductivity type, or the first well region and the second well region are respectively in different processes. Formed and have different conductivity types, and there is no particular limitation.
然後,於步驟S14中,該製造方法分別於基板中形成具有第一導電型的第一電極與具有第二導電型的第二電極,致使第一電極與第一阱區導電性接觸且第二電極與第二阱區導電性接觸。需注意的是,第一電極與第二電極的摻雜濃度會高於第一阱區與第二阱區的雜質濃度。 Then, in step S14, the manufacturing method respectively forms a first electrode having a first conductivity type and a second electrode having a second conductivity type in the substrate, such that the first electrode is in conductive contact with the first well region and the second The electrode is in conductive contact with the second well region. It should be noted that the doping concentration of the first electrode and the second electrode may be higher than the impurity concentration of the first well region and the second well region.
於一實施例中,該製造方法的步驟S10與步驟S12之間可進一步包括:在基板中形成一深阱區,並將第一阱區與第二阱區形成於深阱區中,其中深阱區的導電型異於基板、第一阱區及第二阱區。 In an embodiment, the step S10 and the step S12 of the manufacturing method may further include: forming a deep well region in the substrate, and forming the first well region and the second well region in the deep well region, wherein the deep The conductivity type of the well region is different from the substrate, the first well region, and the second well region.
相較於先前技術,本發明係透過改變暫態電壓抑制器中與齊納二極體串接之二極體元件的架構,將其原本相連的阱區加以分開一間距,藉以達到降低該二極體元件的等效電容而又不影響其對於靜電放電及突波的防護能力。此外,本發明還可配合不同的摻雜濃度及製程參數設定不同的間距,藉以決定該低電容二極體元件之型式為何。 Compared with the prior art, the present invention separates the originally connected well regions by changing the structure of the diode elements connected in series with the Zener diodes in the transient voltage suppressor, thereby reducing the two. The equivalent capacitance of the polar body component does not affect its ability to protect against electrostatic discharge and surge. In addition, the present invention can also set different pitches according to different doping concentrations and process parameters, thereby determining the type of the low capacitance diode element.
藉由以上較佳具體實施例之詳述,係希望能更加清楚描述本發明之特徵與精神,而並非以上述所揭露的較佳具體實施例來對本發明之範疇加以限制。相反地,其目的是希望能涵蓋各種改變及具相等性的安排於本發明所欲申請之專利範圍的範疇內。 The features and spirit of the present invention will be more apparent from the detailed description of the preferred embodiments. On the contrary, the intention is to cover various modifications and equivalents within the scope of the invention as claimed.
4A‧‧‧二極體元件 4A‧‧‧ diode components
sub‧‧‧基板 Sub‧‧‧substrate
P+、N+‧‧‧高濃度摻雜層 P+, N+‧‧‧ high concentration doping layer
P-、N-‧‧‧低濃度摻雜層 P-, N-‧‧‧ low concentration doping layer
DR1~DR2‧‧‧阱區 DR1~DR2‧‧‧ Well Area
EL1~EL2‧‧‧電極 EL1~EL2‧‧‧electrode
d‧‧‧間距 D‧‧‧ spacing
SF‧‧‧表面 SF‧‧‧ surface
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| CN201610164226.4A CN107026156B (en) | 2016-02-01 | 2016-03-22 | Diode element of transient voltage suppressor and method of manufacturing the same |
| US15/138,346 US10043790B2 (en) | 2016-02-01 | 2016-04-26 | Diode device of transient voltage suppressor and manufacturing method thereof |
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| TWI733957B (en) * | 2017-11-24 | 2021-07-21 | 源芯半導體股份有限公司 | Transient voltage suppressor |
| CN110349948B (en) * | 2018-04-04 | 2021-11-30 | 旺宏电子股份有限公司 | Electrostatic discharge protection device and application thereof |
| TWI745595B (en) | 2018-06-05 | 2021-11-11 | 源芯半導體股份有限公司 | Electrostatic discharge protection device |
| TWI743384B (en) * | 2018-07-31 | 2021-10-21 | 立積電子股份有限公司 | Anti-parallel diode device |
| US10388647B1 (en) * | 2018-08-20 | 2019-08-20 | Amazing Microelectronic Corp. | Transient voltage suppression device |
| CN110875304B (en) * | 2018-08-31 | 2022-06-17 | 无锡华润上华科技有限公司 | Transient voltage suppression device and method of manufacturing the same |
| US10930637B2 (en) * | 2018-09-06 | 2021-02-23 | Amazing Microelectronic Corp. | Transient voltage suppressor |
| US10636872B1 (en) * | 2018-10-31 | 2020-04-28 | Globalfoundries Inc. | Apparatus and method to prevent integrated circuit from entering latch-up mode |
| TWI756539B (en) | 2019-05-15 | 2022-03-01 | 源芯半導體股份有限公司 | Semiconductor device with diode and scr |
| CN110556416A (en) * | 2019-06-29 | 2019-12-10 | 上海长园维安微电子有限公司 | Low-residual-voltage large-surge unidirectional snapback TVS device and manufacturing method thereof |
| CN111312710B (en) * | 2020-04-03 | 2024-04-26 | 欧跃半导体(西安)有限公司 | ESD device with low residual voltage and low capacitance value and preparation method thereof |
| US11978809B2 (en) * | 2022-06-27 | 2024-05-07 | Amazing Microelectronic Corp. | Transient voltage suppression device |
| FR3148495A1 (en) * | 2023-05-04 | 2024-11-08 | Stmicroelectronics International N.V. | Electrostatic discharge protection device |
| CN117116936B (en) * | 2023-09-25 | 2024-04-26 | 深圳长晶微电子有限公司 | Unidirectional surge protection device and manufacturing method thereof |
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