TWI582925B - Semiconductor component package structure and manufacturing method thereof - Google Patents

Description

Semiconductor component package structure and manufacturing method thereof

The present invention relates to a package structure, and more particularly to a semiconductor device package structure having a better heat dissipation effect and a method of fabricating the same.

With the advancement of the times, various electronic devices have become closer to people's lives, and have become an inseparable part of people's lives. For example, mobile phones, personal computers, tablets and other electronic devices needed in life bring us great convenience in life. These electronic devices have a large number of semiconductor components inside, but in the case of long-term operation, the temperature of these semiconductor components is increased, and if they are not effectively radiated, these semiconductor components may be damaged.

In Taiwan Patent No. 1417994, a semiconductor device package structure is disclosed. Referring to FIG. 6, the semiconductor device package structure 1 includes a top substrate 71, a top external conductive terminal 71A, a top internal conductive trace 71B, a bottom substrate 72, an underlying external conductive terminal 72A, and an underlying conductive trace. 72B, an insulating layer 80, and a wafer 90. The heat generated by the wafer 30 during operation is mainly transmitted to the outside through the top substrate 71 and the bottom substrate 72, and part of the heat is generated by the top external conductive terminal 71A, the top internal conductive trace 71B, and the bottom external conductive terminal 72A. And the inner conductive trace 72B of the bottom layer is thermally conducted to the outside to achieve the heat dissipation effect.

However, with the advancement of technology, the speed at which the wafer 90 operates is becoming higher and higher, and the amount of heat generated is also increasing. The above-mentioned heat conduction method is increasingly incompatible with demand. In addition, the top substrate 71 and the bottom substrate 72 are respectively disposed between the top internal conductive trace 71B and the top external conductive terminal 71A and the bottom internal conductive trace 72B and the top external conductive terminal 71A, and the top substrate 71 and the bottom substrate 72 are made of glass. Made of fiber, the heat transfer coefficient is low, so the waste heat generated by the wafer 90 is not easily discharged. As a result, heat is accumulated on the semiconductor element, so that the temperature of the wafer 90 is higher and higher, and the lifetime of the wafer 90 is lowered.

Therefore, how to design a semiconductor component package structure to have a better heat dissipation effect is worthy of consideration in the art.

It is an object of the present invention to provide a semiconductor device package structure which has a better heat dissipation effect without causing a short circuit of the circuit.

An object of the present invention is to provide a semiconductor device package structure including a semiconductor device,

A top substrate, a bottom substrate, an insulating layer and a two-metal conductive layer. The top substrate is mainly made of a conductive metal and has a first separation area on the top substrate. The first separation area divides the top substrate into two mutually non-electrically connected blocks. The bottom substrate is mainly made of a conductive metal, and has a second partition on the bottom substrate, and the second partition divides the bottom substrate into two mutually non-electrically connected blocks. The insulating layer is disposed between the top substrate and the bottom substrate. The metal conductive layer is located on two sides of the insulating layer and is connected to the top substrate and the bottom substrate. The top substrate and the bottom substrate are in contact with the semiconductor element.

In the above semiconductor device package structure, the top substrate and the bottom substrate are mainly made of copper.

In the above semiconductor device package structure, the lower surface of the top substrate has at least one first conductive pad, and the upper surface of the bottom substrate has at least one second conductive pad, and the semiconductor component is located at the first Between the conductive pad and the second conductive pad.

The semiconductor device package structure further includes a solder paste, and the solder paste is coated on the first conductive pad and the second conductive pad.

In the above semiconductor device package structure, the two sides of the metal conductive layer respectively have at least one through hole, and the metal conductive layer is formed on the inner surface of the through hole.

The above semiconductor element package structure, wherein the semiconductor element is a diode.

The above method for manufacturing a semiconductor device package structure includes the following steps:

(a) providing an upper metal plate and a lower metal plate;

(b) the semiconductor component is disposed on the lower metal plate;

(c) superposing the upper metal plate and the lower metal plate such that the semiconductor component is located between the upper metal plate and the lower metal plate;

(d) performing a filling operation to form an insulating layer between the upper metal plate and the lower metal plate;

(e) drilling the upper metal plate and the lower metal plate to form a plurality of through holes;

(f) forming a metal conductive layer on the inner surface of the through hole, the metal conductive layer connecting the upper metal plate and the lower metal plate;

(g) forming a plurality of first partitions and a plurality of second partitions on the upper metal plate and the lower metal plate, respectively, the first and second partitions respectively separating the upper metal plate and the lower metal The board is divided into a plurality of zone plates, and each zone plate has the through hole;

(h) A cutting operation is performed to form a plurality of semiconductor element package structures.

The manufacturing method of the semiconductor device package structure, wherein the upper surface of the upper metal plate has at least one first conductive pad in the step (a), and the upper surface of the lower metal plate has at least one second conductive pad .

In the above method for fabricating a semiconductor device package structure, a solder paste is applied on the first conductive pad and the second conductive pad between the steps (a) and (b).

In the above method for manufacturing a semiconductor device package structure, in the step (d), the filling operation is performed by a capillary phenomenon from a gap formed by two sides of the upper metal plate and the lower metal plate when they are superposed Fill the gel.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the preferred embodiments will be described below in detail with reference to the accompanying drawings.

1‧‧‧Semiconductor component package structure

2‧‧‧Semiconductor component package structure

3‧‧‧Semiconductor component package structure

10‧‧‧Semiconductor components

20‧‧‧Top substrate

20A‧‧‧First top block

20B‧‧‧second top block

21‧‧‧First partition

211‧‧‧First insulation solder mask

22‧‧‧First Conductive Pad

26‧‧‧Upper metal plate

30‧‧‧ bottom substrate

30A‧‧‧First bottom block

30B‧‧‧second bottom block

31‧‧‧Second compartment

311‧‧‧Second insulation solder mask

32‧‧‧Second conductive pad

33‧‧‧ solder paste

36‧‧‧Under metal sheet

40‧‧‧Insulation

50‧‧‧Metal conductive layer

60‧‧‧through hole

71‧‧‧ top substrate

71A‧‧‧Top external conductive terminal

71B‧‧‧Top internal conductive track

72‧‧‧Bottom substrate

72A‧‧‧ bottom external conductive terminal

72B‧‧‧Underground internal conductive track

80‧‧‧Insulation

90‧‧‧ wafer

S1~S8‧‧‧Steps

1 is a side cross-sectional view showing a semiconductor device package structure according to an embodiment of the present invention.

FIG. 2 is a structural diagram of a semiconductor device package structure according to another embodiment of the present invention.

3 is a top plan view showing a semiconductor device package structure according to another embodiment of the present invention.

4A to 4G illustrate a manufacturing process of the semiconductor device package structure 3 described above.

FIG. 5 illustrates the steps of a method of fabricating the semiconductor device package structure 3.

FIG. 6 is a structural diagram of a conventional semiconductor device package structure.

Please refer to FIG. 1. FIG. 1 is a side cross-sectional view showing a semiconductor device package structure according to an embodiment of the present invention. The semiconductor device package structure 2 includes a semiconductor device 10, a top substrate 20, a bottom substrate 30, an insulating layer 40, and a two-metal conductive layer 50. In the present embodiment, the semiconductor element 10 is a diode. The top substrate 20 is mainly made of a conductive metal (for example, copper), and has a first partition 21 on the top substrate 20, and the first partition 21 divides the top substrate 20 into two non-electricalities. Connected blocks. In addition, the bottom substrate 30 is mainly made of a conductive metal (for example, copper), and has a second partition 31 on the bottom substrate 30. The second partition 31 divides the bottom substrate 30 into two. Blocks that are not electrically connected to each other. In addition, the insulating layer 40 is disposed between the top substrate 20 and the bottom substrate 30 and surrounds the semiconductor device 10. The semiconductor element 10 is in contact with the top substrate 20 and the bottom substrate 30. Further, the metal conductive layer 50 is formed on both sides of the semiconductor element package structure 2, and is connected to the top substrate 20 and the bottom substrate 30.

Referring to FIG. 1 , the first separation region 21 on the top substrate 20 of the semiconductor component package structure 2 divides the top substrate 20 into two mutually non-electrically connected blocks, which are respectively the first top region. The block 20A and the second top block 20B, the first top block 20A is located on the right side of the first partition 21 on the top substrate 20, and the second top block 20B is the first partition 21 on the top substrate 20. On the left side. Similarly, the second partition 31 on the bottom substrate 30 divides the bottom substrate 30 into two mutually non-electrically connected blocks, which are the first bottom block 30A and the second bottom portion, respectively. Block 30B, the first bottom block 30A is on the right side of the second partition 31 on the bottom substrate 30, and the second bottom block 30B is on the left side of the second partition 31 on the bottom substrate 30. The first top block 20A, the first bottom block 30A, and the metal conductive layer 50 are electrically connected to each other to form a positive terminal of the semiconductor device package structure 2, and are electrically connected to the positive terminal of the semiconductor device 10. In contrast, the second top block 20B and the second bottom block 30B are electrically connected to the metal conductive layer 50 to form a negative terminal of the semiconductor device package 2, and are electrically connected to the negative terminal of the semiconductor device 10. It can be seen from the above that the provision of the first separation region 21 and the second separation region 31 can prevent the positive terminal and the negative terminal of the semiconductor device package structure 2 from being electrically connected to each other without causing a short circuit. Moreover, the semiconductor device package structure 2 can be disposed on a circuit board (not shown) by wire bonding or surface bonding technology. In addition, the insulating layer 40 can block moisture and suspended particles in the outside air, so that the semiconductor element 10 is not contaminated by external moisture or suspended particles, and the quality of the semiconductor element 10 is ensured.

2 and FIG. 3, FIG. 2 is a structural diagram of a semiconductor device package structure according to another embodiment of the present invention, and FIG. 3 is a top view of a semiconductor device package structure according to another embodiment of the present invention. In this embodiment, the same components as those in the embodiment shown in FIG. 1 will be denoted by the same reference numerals and will not be described in detail. The lower surface of the top substrate 20 of the semiconductor device package structure 3 has a first conductive pad 22, and the upper surface of the bottom substrate 30 has a second conductive pad 32. The semiconductor component 10 is located between the first conductive pad 22 and the second conductive pad 32. In addition, a solder paste 33 is coated on the first conductive pad 22 and the second conductive pad 32. This solder paste 33 is electrically connected to the semiconductor element 10. In this embodiment, the solder paste 33 may be replaced by a conductive paste. After the conductive paste is applied to the first conductive pad 22 and the second conductive pad 32, the conductive paste is dried. The conductive paste is cured to produce a bonding effect, so that the semiconductor component 10 is fixed between the first conductive pad 22 and the second conductive pad 32. In addition, at least one through hole 60 is formed on each of the two sides of the semiconductor device package structure 3 (in the embodiment, the left side of the semiconductor device package structure 3 has a through hole 60, and the right side has a through hole 60). And the metal conductive layer 50 is formed on the inner surface of the through hole 60. Further, the first separation region 21 has a first insulating solder resist layer 211 thereon. Similarly, the second separation region 31 has a second insulating solder resist layer 311.

Please refer to FIG. 4A to FIG. 4G and FIG. 5 . FIG. 4A to FIG. 4G illustrate the manufacturing process of the semiconductor device package structure 3 , and FIG. 5 illustrates the steps of the method for manufacturing the semiconductor device package structure 3 . First, referring to step S1, as shown in FIG. 4A, an upper metal plate 26 and a lower metal plate 36 are provided. The lower surface of the upper metal plate 26 has at least one first conductive pad 22, and the upper surface of the lower metal plate 36 has at least one second conductive pad 32. Then, referring to step S2, as shown in FIG. 4B, a solder paste 33 is applied to the first conductive pad 22 on the lower surface of the upper metal plate 26 and the second conductive pad on the upper surface of the lower metal plate 36. 32. Thereafter, referring to step S3, as shown in FIG. 4C, the semiconductor element 10 is disposed between the lower metal plate 36 and the upper metal plate 26. More specifically, the semiconductor device 10 is placed between the first conductive pad 22 and the second conductive pad 32, and the metal plate 36 and the upper metal plate 26 and the semiconductor device 10 which have been coated with the solder paste 33 are coated. Place in the welding furnace. Then, the solder paste 33 is subjected to a high-temperature action to produce a bonding effect, and the semiconductor element 10 is bonded to the lower metal plate 36 and the upper metal plate 26. After that, referring to step S4, as shown in FIG. 4D, since the upper metal plate 26 and the lower metal plate 36 are stacked, a gap is formed on the two sides, so that the gap can be filled by the capillary phenomenon to form a gap. The insulating layer 40 and the package structure in which the insulating layer 40 has been formed are baked by an oven, so that the insulating layer 40 formed after the filling operation is cured by the action of high temperature.

Next, referring to step S5, as shown in FIG. 4E, the upper metal plate 26 and the lower metal plate 36 are drilled to form a plurality of through holes 60 on both sides of each semiconductor element 10, and by means of electroplating. To form a metal conductive layer 50 on the via 60. Thereafter, referring to step S6, as shown in FIG. 4F, chemical etching is applied to the upper metal plate 26 and the lower metal plate 36, respectively, to form a plurality of first separation regions 21 and a plurality of second separation regions 31 on the upper metal. Plate 26 and lower metal plate 36. After that, referring to step S7, as shown in FIG. 4G, the first insulating layer 21 of the semiconductor device package structure 3 is coated with a first insulating solder resist layer 211, and the second partition region 31 is coated with a second insulating solder resist. Layer 311. Finally, referring to step S8, a cutting operation is performed to form a plurality of semiconductor element package structures 3 (as shown in FIG. 2).

In summary, the top substrate 20 and the bottom substrate 30 of the semiconductor device package structure 2 or the semiconductor device package structure 3 of the present embodiment are made of a conductive metal as compared with the conventional semiconductor device package structure 1. Therefore, by the heat conduction effect of the metal substrate, the heat generated by the semiconductor element 10 during operation can be more quickly conducted and emitted to the outside without causing the semiconductor element 10 to be damaged by the high temperature.

The present invention has been disclosed in the above preferred embodiments. However, it is not intended to limit the scope of the present invention, and it is possible to make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

2‧‧‧Semiconductor component package structure

10‧‧‧Semiconductor components

20‧‧‧Top substrate

20A‧‧‧First top block

20B‧‧‧second top block

21‧‧‧First partition

30‧‧‧ bottom substrate

30A‧‧‧First bottom block

30B‧‧‧second bottom block

31‧‧‧Second compartment

40‧‧‧Insulation

50‧‧‧Metal conductive layer

Claims (10)

[Item 1] A semiconductor component package structure comprising:
a semiconductor component;
a top substrate, mainly made of a conductive metal, and having a first separation region on the top substrate, the first separation region dividing the top substrate into two mutually non-electrically connected blocks;
a bottom substrate, which is mainly made of a conductive metal, and has a second partition on the bottom substrate, the second partition divides the bottom substrate into two mutually non-electrically connected blocks;
An insulating layer disposed between the top substrate and the bottom substrate; and a second metal conductive layer on the two sides of the insulating layer and connected to the top substrate and the bottom substrate;
The top substrate and the bottom substrate are in contact with the semiconductor element. [Item 2] The semiconductor device package structure according to claim 1, wherein the top substrate and the bottom substrate are mainly made of a copper material. [Item 3] The semiconductor device package structure of claim 1, wherein the lower surface of the top substrate has at least one first conductive pad, and the upper surface of the bottom substrate has at least one second conductive pad. And the semiconductor component is located between the first conductive pad and the second conductive pad. [Item 4] The semiconductor device package structure of claim 3, further comprising a solder paste coated on the first conductive pad and the second conductive pad. [Item 5] The semiconductor device package structure of claim 1, wherein each of the two sides of the metal conductive layer has at least one through hole, and the metal conductive layer is formed on an inner surface of the through hole. [Item 6] The semiconductor device package structure of claim 1, wherein the semiconductor device is a diode. [Item 7] A method of fabricating a semiconductor component package structure, comprising the steps of:
(a) providing an upper metal plate and a lower metal plate;
(b) the semiconductor component is disposed on the lower metal plate;
(c) superposing the upper metal plate and the lower metal plate such that the semiconductor component is located between the upper metal plate and the lower metal plate;
(d) performing a filling operation to form an insulating layer between the upper metal plate and the lower metal plate;
(e) drilling the upper metal plate and the lower metal plate to form a plurality of through holes;
(f) forming a metal conductive layer on the inner surface of the through hole, the metal conductive layer connecting the upper metal plate and the lower metal plate;
(g) forming a plurality of first partitions and a plurality of second partitions on the upper metal plate and the lower metal plate, respectively, the first and second partitions respectively separating the upper metal plate and the lower metal The board is divided into a plurality of zone plates, and each zone plate has the through hole;
(h) A cutting operation is performed to form a plurality of semiconductor element package structures. [Item 8] The method of manufacturing a semiconductor device package structure according to claim 7, wherein the lower surface of the upper metal plate in the step (a) has at least one first conductive pad, and the upper surface of the lower metal plate There is at least one second conductive pad. [Item 9] The method of fabricating a semiconductor device package structure according to claim 7, wherein a solder paste is applied on the first conductive pad and the second lead between the steps (a) and (b) On the welding pad. [Item 10] The method of manufacturing a semiconductor device package structure according to claim 7, wherein in the step (d), the glue filling operation is performed by the capillary phenomenon when the upper metal plate and the lower metal plate are overlapped. The gap formed in the side of the second side is filled with a colloid.