TWI582966B - Multi-cell chip - Google Patents

Description

Polycrystalline wafer

This invention relates to a wafer, and more particularly to a rewritable polycrystalline wafer.

In the era of information explosion, integrated circuits have been inextricably linked to daily life. In the case of food and clothing, it is common to use products consisting of integrated circuit components. As semiconductor process technology continues to evolve, more and more arithmetic processing units can be integrated into a single wafer and fabricated using high-order semiconductor process technology. Due to the cost of manufacturing high-order semiconductor processes (such as photomasks), current solutions are mostly based on high computational considerations to design wafers. If the user designs the wafer based on high computational power considerations, for example, integrating multiple arithmetic processing units into the wafer, the cost of the high-computation wafer will be high, and it is not suitable for low-cost and low-computing power requirements. In the electronics. That is to say, after the current design or fabrication of the wafer is completed, the current scheme can no longer provide the user with an elastic choice between the wafer computing power and the wafer cost.

In view of this, the present invention provides a multi-cell wafer in which a multi-cell wafer is usable (operable) after being connected to a desired power source and signal. When the poly unit wafer has not been re-cut, the data can be dispersed in a plurality of unit cells in the poly unit wafer. The signals of different unit cells in the multi-cell wafer can be transmitted through the signal transmission line group between the unit cells. In addition, the user can elastically cut the polycrystalline silicon wafer in units of unit cells according to actual applications, required computing power or cost considerations, and cut into a plurality of sub-wafers, wherein the cut portions are cut. The sub-chip can still be used after it has been connected to the required power and signal (still operational). In this way, the flexibility of use of the polycrystalline wafer after design or fabrication can be improved. In addition, when a part of the unit cell in the poly unit cell fails, the poly unit wafer can be cut into sub-wafers having fewer unit cells to remove the failed unit cell, wherein the failed unit cell is removed. The sub-wafers can still be used normally. Therefore, the usability (yield) of the poly unit wafer can be improved.

The multi-cell wafer of the present invention can be used (operable) after being connected to a desired power source and signal, wherein the multi-cell wafer can include a semiconductor substrate, a plurality of unit cells, and a plurality of signal transmission line groups. Such unit cells can be disposed on a semiconductor substrate. Any two of the unit cells may have a space between them. The signal transmission line groups are respectively disposed on at least a portion of the spaced spaces, and are respectively used for signal transmission between at least some of the adjacent cells. The polycrystalline silicon wafer can be cut through a portion of the spaced spaces to cut off some of the signal transmission line groups, so that the poly unit wafer can be divided into a plurality of sub-wafers, wherein the cut portions of the sub-wafers It can still be used after connecting the required power and signal (still working).

In an embodiment of the invention, at least one of the cells of the poly unit cell may have a plurality of pads, wherein the pads are coupled to an external chip for signal transmission.

In an embodiment of the invention, the signal transmission line groups may be used to perform data transmission or power transmission between the at least some adjacent cells.

In an embodiment of the invention, each of the sub-wafers described above has a different number of unit cells.

In an embodiment of the invention, each of the plurality of unit cells may include at least one detection line. The detection line can be used to automatically detect whether the signal transmission line group between the unit cell and the adjacent unit cell is cut off, and accordingly generate a detection signal.

In an embodiment of the invention, the detecting circuit may include a buffer, a first resistor, and a second resistor. The input end of the buffer is coupled to the power supply terminal through a signal line of the signal transmission line group between the unit cell and the adjacent unit cell, and the output end of the buffer is used to generate the detection signal. The first resistor is coupled between the input end of the buffer and the ground. The second resistor is coupled between the input of the buffer and the output of the buffer.

In an embodiment of the invention, each of the plurality of unit cells further includes at least one interface circuit. The at least one interface circuit can be coupled to the signal transmission line group between the unit cell and the adjacent unit cell, and can be coupled to the at least one detection line to receive the detection signal. When the at least one detecting line detects that the signal transmission line group is cut, the at least one interface circuit can automatically isolate the connection between the unit cell and the signal transmission line group.

In an embodiment of the invention, each of the aforementioned unit cells may include a plurality of circuits. Each of such circuits may have an identification (ID), wherein the identification code is read-only and unique to identify each of the circuits.

In an embodiment of the invention, each of the aforementioned unit cells may include an identification code. The identification code is read-only and unique to identify each of these cells.

In an embodiment of the invention, each of the unit cells described above cooperates with a software, and each of the unit cells determines whether the software is allowed to be used according to the identification code.

In an embodiment of the invention, each of the unit cells is configured to execute a software, and each of the unit cells uses an identification code as a key to encrypt the software or Decrypt.

In an embodiment of the invention, the partial unit cells are used to simultaneously execute a software, and the identification code of one of the partial unit cells is used as a key to encrypt or decrypt the software.

In an embodiment of the invention, the functions of the cells described above are not identical.

In an embodiment of the invention, the areas of the unit cells described above are not completely the same.

Based on the above, the poly unit wafer of the embodiment of the present invention can be elastically cut to be cut into a plurality of sub-wafers depending on actual application, performance, or cost requirements. As a result, the flexibility of the use of the polycrystalline wafer after use in design or fabrication can be improved. On the other hand, if a part of the unit cell on the poly unit cell fails, the poly unit wafer can be cut into sub-wafers with fewer unit cells to remove the failed unit cell, and the failed unit cell is removed. The sub-wafer can still be used (still operational), thus increasing the usable rate (yield) of the wafer.

The above described features and advantages of the invention will be apparent from the following description.

DETAILED DESCRIPTION OF THE INVENTION Reference will now be made in detail to the exemplary embodiments embodiments In addition, wherever possible, the same reference numerals in the drawings

Please refer to FIG. 1 and FIG. 2 at the same time. FIG. 1 is a schematic diagram of the structure of a polycrystalline silicon wafer 100 in a wafer 10 according to an embodiment of the invention. FIG. 2 is an enlarged schematic view showing one of the unit cells 140 of the poly unit cell wafer 100 according to an embodiment of the invention. Wafer 10 can include a plurality of polycell wafers 100 (shown in Figure 1) in which multi-cell wafers 100 are usable (operable) after being connected to the desired power source and signal. For example, the poly cell wafer 100 can operate by receiving a power supply voltage and an input signal, and accordingly generate an output signal, but the invention is not limited thereto.

The poly unit cell wafer 100 may include a semiconductor substrate 180, a plurality of signal transmission line groups 120 (including signal transmission line groups 120_U, 120_R, 120_D, 120_L), and a plurality of unit cells 140 (including unit cells 140_8, 140_12, 140_13, 140_14, 140_18). . The unit cell 140 can be disposed on the semiconductor substrate 180. There are spaced spaces 110 between any two adjacent cells 140. Each of the signal transmission line groups 120 may be disposed on the space 110 between any two adjacent cells 140 and used to perform signal transmission between any two adjacent cells 140, but the present invention is not limited thereto. In other embodiments of the present invention, the space 110 between the adjacent cells 140 may not be configured with the signal transmission line group 120, such as the poly unit wafer 100" of FIG. 8, wherein the cell 140_8 of FIG. The space 110 between the cell 140_9 and the cell 140_9 is not configured with the signal transmission line group 120, but the cell 140_8 and the cell 140_9 can still transmit signals through other unit cells (for example, the cells 140_13 and 140_14).

Please refer to FIG. 1 and FIG. 2 at the same time. In an embodiment of the invention, the signal transmission line group 120 can be used for data transmission or power transmission between two adjacent cells 140, but the invention is not limited thereto. In addition, as shown in FIG. 2, each of the unit cells 140 may have a plurality of pads 145, but the present invention is not limited thereto. In other embodiments of the present invention, a portion of the unit cells 140 in the poly unit wafer 100 may have pads 145, while the remaining unit cells 140 in the poly unit wafer 100 may have no pads 145. The pad 145 can be coupled to an external wafer (not shown) to allow the cell 140 to be signaled with an external wafer. In an embodiment of the invention, the pad 145 of the cell 140 can be electrically connected to the external chip by a flip chip wafer bonding technique, but the invention is not limited thereto.

In detail, in the exemplary embodiment shown in FIG. 1 of the present invention, the poly unit wafer 100 includes 25 unit cells 140, wherein 25 unit cells 140 are arranged in an array pattern of 5 by 5 on the semiconductor substrate 180. on. In addition, any two adjacent cells 140 may be coupled to each other through a corresponding signal transmission line group 120 for signal transmission. For example, as shown in FIG. 1, the unit cell 140_13 and the unit cell 140_8 are coupled to each other via the signal transmission line group 120_U for signal transmission; the unit cell 140_13 and the unit cell 140_12 are coupled to each other via the signal transmission line group 120_L. Signal transmission is performed; the unit cell 140_13 and the unit cell 140_18 are coupled to each other via the signal transmission line group 120_D for signal transmission; and the unit cell 140_13 and the unit cell 140_14 are coupled to each other via the signal transmission line group 120_R for signal transmission. Transmission, the rest can be deduced by analogy. Since the signal transmission line group 120 (including the signal transmission line group 120_U, 120_R, 120_D, 120_L) is an on-chip interface (OCI) inside the poly unit wafer 100, the signal transmission speed between the unit cells 140 can be improved. .

In an embodiment of the invention, the user can elastically cut the poly unit wafer 100 according to actual application, performance or cost requirements to cut the poly unit wafer 100 into a plurality of sub-wafers, wherein each of the cut wafers A sub-wafer may include at least one unit cell 140, and a portion of the sub-wafer after cutting may still be used normally. For example, the cut partial sub-wafer can operate by receiving a power supply voltage and an input signal, and accordingly generate an output signal, but the invention is not limited thereto. Still further, the polycrystalline cell wafer 100 is cut based on at least one unit cell 140 and can be cut through the space 110, such as shown by the cutting line 290 shown in FIG.

In the exemplary embodiment shown in FIG. 1, the poly unit wafer 100 can be cut into 25 array type sub-wafers, and the unit cell 140 in the diced sub-wafer can be an M-by-N array pattern, wherein M and N are integers greater than or equal to 1 and less than or equal to 5. Please refer to FIG. 3 below. FIG. 3 is a schematic diagram of a cutting of the poly unit wafer 100 of FIG. The poly unit wafer 100 can be cut through the spaces 110_1 and 110_2. In detail, the poly unit wafer 100 can be cut through the dicing lines 390_1, 390_2 to divide the poly unit wafer 100 into four sub-wafers 332, 334, 336, 338, wherein the diced four sub-chips 332 Some of the sub-wafers in 334, 336, and 338 can still be used normally after the required power and signal are connected.

As shown in FIG. 3, the sub-wafer 332 includes four unit cells 140, and the four unit cells 140 are in an array pattern of 2 times 2, and any two of the four unit cells 140 are still permeable to corresponding signal transmission lines. Group 120 performs signal transmission. The sub-wafer 334 includes six unit cells 140, and the six unit cells 140 are in an array pattern of two times three, and any two of the six unit cells 140 can still transmit signals through the corresponding signal transmission line group 120. The sub-wafer 336 includes six unit cells 140, and the six unit cells 140 are in an array pattern of three times two, and any two of the six unit cells 140 can still transmit signals through the corresponding signal transmission line group 120. The sub-wafer 338 includes nine unit cells 140, and the nine unit cells 140 are in an array pattern of three times three, and any two of the nine unit cells 140 can still transmit signals through the corresponding signal transmission line group 120.

Incidentally, the number and arrangement of the unit cells 140 of the polycrystalline cell wafer 100 shown in FIG. 1 are only an example. The number and arrangement of the unit cells 140 of the poly unit wafer 100 can be determined by the designer. Depending on the application or design needs. In addition, the cutting manner of the poly unit wafer 100 shown in FIG. 3 is only an example, and the user can cut the poly unit wafer 100 according to actual application or design requirements, so that the cut sub-chip can be cut. The number of unit cells 140 (e.g., four) in (e.g., sub-wafer 332 of Fig. 3) is in line with actual needs and has an optimized computing power. As a result, the effect of reducing the cost of the hardware can be achieved and the flexibility in the use of the wafer can be increased.

Since any signal transmission line group (for example, the signal transmission line group 120_L) between two adjacent unit cells (for example, the unit cells 140_12 and 140_13 shown in FIG. 1) is likely to be cut during wafer cutting, in order to avoid cutting off The signal transmission line group (for example, the signal transmission line group 120_L) exhibiting a floating state affects the normal operation of the unit cell (for example, the unit cells 140_12 and 140_13 shown in FIG. 1), and thus each unit cell (for example, as shown in FIG. 1) The cells 140_12 and 140_13) may have an automatic detection mechanism to automatically detect whether the signal transmission line group (for example, the signal transmission line group 120_L) is cut off.

For example, once the signal transmission line group 120_L between the cells 140_12 and 140_13 is cut due to wafer dicing, the cells 140_12 and 140_13 can isolate the input signal from the floating state signal transmission line group 120_L to avoid Unknown input signals affect the normal operation of the cells 140_12 and 140_13.

Please refer to FIG. 1 and FIG. 4 . FIG. 4 is a schematic structural diagram of the interface circuit and the detection circuit in the unit cell 140 of FIG. 1 . Each of the cells 140 may include at least one detection line 447 for automatically detecting whether the corresponding signal transmission line group 120 is cut off, and accordingly generating the detection signal DS. For example, the unit cell 140_13 shown in FIG. 1 can include four detection lines 447 as shown in FIG. 4, which can be used to automatically detect whether the signal transmission line groups 120_U, 120_D, 120_L, 120_R are cut off.

In addition, each cell 140 can also include at least one interface circuit 445. The interface circuit 445 can be coupled to the signal transmission line group 120 between adjacent cells and can be coupled to the detection line 447 to receive the detection signal DS. When the detection circuit 447 detects that the signal transmission line group 120 between adjacent cells is cut off, the interface circuit 445 can automatically isolate the connection between the cell 140 and the signal transmission line group 120 to avoid the signal transmission line group 120. The logic level of the ambiguous input signal affects the normal operation of the unit cell 140.

In an embodiment of the invention, the detection line 447 can include a buffer BUF and resistors R1, R2. The input end of the buffer BUF can be coupled to a power supply terminal VDD through a signal line W1 of the signal transmission line group 120. The output of the buffer BUF is used to generate the detection signal DS. The resistor R1 is coupled between the input end of the buffer BUF and the ground GND. The resistor R2 is coupled between the input end and the output end of the buffer BUF.

For example, when the signal transmission line group 120_L between the cells 140_12 and 140_13 is not cut, the input end of the buffer BUF may pass through the signal line of the signal transmission line group 120_L (the signal line W1 shown in FIG. 4). The power supply signal from the power supply terminal VDD is received, so the buffer BUF can output the logic high level detection signal DS. In this way, the cells 140_12 and 140_13 can judge that the signal transmission line group 120_L is not cut according to the detection signal DS of the logic high level, so that the interface circuit between the unit cell 140_12 and the unit cell 140_13 can transmit the unit cell 140_12 ( The interface circuit 445), the signal transmission line group 120_L, and the interface circuit of the unit cell 140_13 (the interface circuit 445 shown in FIG. 4) are used for signal transmission.

In contrast, once the signal transmission line group 120_L between the cells 140_12 and 140_13 is cut due to wafer dicing, the input terminal of the buffer BUF can be pulled down to the logic low level through the resistor R1, so the buffer BUF can be output. Logic low level detection signal DS. In this way, the cells 140_12 and 140_13 can judge that the signal transmission line group 120_L has been cut according to the logic low level detection signal DS. At this time, the interface circuit in the cell 140_12 (such as the interface circuit 445 shown in FIG. 4) can input the input signal of the signal transmission line group 120_L from the floating state to the unit cell 140_12 according to the logic low level detection signal DS. The internal circuit is isolated to prevent the input signal of ambiguous logic level from affecting the normal operation of the cell 140_12. Similarly, the interface circuit in the cell 140_13 (such as the interface circuit 445 shown in FIG. 4) can input the input signal of the signal transmission line group 120_L from the floating state to the unit cell 140_13 according to the logic low level detection signal DS. The internal circuit is isolated to prevent the input signal of ambiguous logic level from affecting the normal operation of the cell 140_13.

Incidentally, the relationship between the logic high and low level of the detection signal DS of the above example and the disconnection of the signal transmission line group 120_L is only an example. It is well known in the art that the relationship between the logic level of the detection signal DS and the disconnection of the signal transmission line group 120_L can be defined by the designer according to actual needs.

In the above embodiment, the function of each unit cell 140 shown in FIG. 1 may be identical or not identical. In fact, the present invention does not limit the function of each of the unit cells 140 in the poly unit wafer 100. For example, the 25 unit cells 140 shown in FIG. 1 may be, for example, all Microcontroller Units (MCUs). Alternatively, the ten cells 140 shown in FIG. 1 may be, for example, a microcontroller, while the remaining 15 cells 140 are memories. In simple terms, the user can flexibly design the function of each unit cell 140 according to actual application or design requirements.

In the embodiment shown in FIG. 1, the area of each unit cell 140 is the same, and the 25 unit cells 140 are arranged in an array pattern on the poly unit wafer 100, but the invention is not limited thereto. Please refer to FIG. 1 and FIG. 5 at the same time. FIG. 5 is a schematic diagram of the structure of a poly unit wafer 100' in a wafer 10 according to another embodiment of the invention. The poly unit wafer 100' shown in Fig. 5 also includes a semiconductor substrate 180, a plurality of signal transmission line groups 120, and a plurality of unit cells 540. However, compared to FIG. 1, the area of each unit cell 540 of FIG. 5 is not completely the same, and the arrangement of the unit cells 540 is not a simple array pattern. For example, the area of the unit cell 540_8 shown in FIG. 5 is four times that of the unit cell 540_7, and the area of the unit cell 540_14 is twice that of the unit cell 540_7, but the invention is not limited thereto. In fact, the area of each of the unit cells 540 shown in Figure 5 and the arrangement of the unit cells 540 on the polycrystalline wafer 100' may depend on the actual application or design requirements. In addition, other details of the polycrystalline cell wafer 100' shown in FIG. 5 can be analogized with reference to the related descriptions of FIGS. 1 to 4, and therefore will not be described again.

Please refer back to Figure 1 and Figure 2 below. As shown in FIG. 2, each unit cell 140 can include an identification (ID) 241. The identification code 241 in each unit cell 140 is read-only and unique and can be used to identify each unit cell 140. After the unit cell 140 is manufactured, the identification code 241 can be burned into the unit cell 140 in a single burning manner, but the invention is not limited thereto. The identification code 241 in the unit cell 140 can be read by the software executed in the unit cell 140, or can be read by the external wafer (not shown) through the pad 145. In addition, the identification code 241 burned into the unit cell 140 has passed the registration procedure and is unique. Therefore, by reading the identification code 241 of the unit cell 140, it can be determined whether the unit cell 140 is genuine.

In an embodiment of the invention, the identification code 241 can also be used to protect software implemented on the unit cell 140, wherein the software can cooperate with the unit cell 140. For example, each cell 140 can determine whether to allow the use of the software based on its own identification code 241. In this way, the user can be prevented from purchasing only one set of software, but the software is used on different unit cells 140.

In some applications, the above software may be stored in a memory external to the unit cell 140. In order to prevent the software stored in the external memory from being stolen or the content of the software being analyzed, each unit cell 140 may use its own identification code 241 as a key to encrypt the software, and then encrypt the software. The software is stored in external memory. When the unit cell 140 is to execute or use the above software, it is only necessary to read the encrypted software from the external memory, and then use the identification code 241 of the unit cell 140 as a key to decrypt the encrypted software. In an embodiment of the present invention, the encryption and decryption functions of the unit cell 140 can be implemented by using a hardware circuit, but the invention is not limited thereto. In another embodiment of the present invention, the encryption and decryption functions of the unit cell 140 can also be implemented using an encryption and decryption software program, wherein the encryption and decryption software program can be stored in the one-time programming inside the unit cell 140 (One Time) Program, OTP) Memory or Multi Time Program (MTP) memory, and the encryption and decryption software programs cannot be read from outside the unit cell 140.

Please refer back to Figure 1 and Figure 2 below. In an embodiment of the invention, the plurality of cells 140 of the polycrystalline wafer 100 shown in FIG. 1 can be used to simultaneously execute a soft body. Since the plurality of unit cells 140 have a plurality of different identification codes 241, the poly unit wafer 100 can encrypt, decrypt, mount, or execute the software by using the identification code 241 of one of the unit cells 140 as a key. For example, when the unit cells 140_8, 140_13 shown in FIG. 1 are used to simultaneously execute a software, the identification code of the unit cell 140_8 (the identification code 241 shown in FIG. 2) can be used as a key to encrypt the software. And decrypting, the unit cell 140_8 can transmit the decrypted software data to the unit cell 140_13 through the signal transmission line group 120_U. In this way, the software can be installed or executed by the unit cells 140_8, 140_13.

Please refer back to Figure 2 and Figure 3 below. In an embodiment of the invention, the four cells 140 of the illustrated sub-wafer 332 of FIG. 3 can also be used to simultaneously execute a software. Since the four cells 140 of the sub-wafer 332 have four different identification codes 241, the sub-wafer 332 can encrypt, decrypt, install or execute the software by using the identification code 241 of one of the cells 140 as a key. . Similarly, the remaining sub-wafers 334, 336, 338 can be analogized according to the above description, and therefore will not be described again.

Please refer to FIG. 6 below. Figure 6 is a block diagram showing the structure of a unit cell 140' of the polycrystalline cell wafer 100 of Figure 1. The cell 140' shown in Figure 6 can include two circuits 642, 644, wherein the circuit 642 can have an identification code 641 and the circuit 644 can have an identification code 643. The identification code 641 of circuit 642 is read-only and unique and can be used to identify circuit 642. Likewise, the identification code 643 of circuit 644 is read-only and unique and can be used to identify circuit 644. Incidentally, the number of circuits in the unit cell 140' shown in Fig. 6 is merely an example and is not intended to limit the present invention. The number of circuits in the cell 140' can be determined by the designer depending on the actual application or design requirements. In addition, the function of the identification code 641 of the circuit 642 and the identification code 643 of the circuit 644 is similar to the identification code 241 of the unit cell 140 shown in FIG. 2, so the identification code 641 of the circuit 642 and the identification code 643 of the circuit 644 are The function can be referred to the related description of FIG. 2 above, and will not be described here.

Please refer to FIG. 7. FIG. 7 is a schematic diagram of an application of the polycrystalline cell wafer 100 of FIG. In the present embodiment, the unit cell 140_P may be, for example, a processor, and the unit cell 140_M may be, for example, a quad-port memory, and the unit cell 140_P and the unit cell 140_M are alternately arranged on the poly unit wafer 100. On the semiconductor substrate 180. The arrangement of the cells 140_P, 140_M shown in Figure 7 is suitable for mental network or image processing, which can improve the processing speed of the switching network or image edge reference, and make the switching network or image edge reference easier. achieve.

In summary, the poly unit wafer of the embodiment of the present invention can be elastically cut to be cut into a plurality of sub-wafers according to actual application, performance or cost requirements. As a result, the flexibility of the use of the polycrystalline wafer after use in design or fabrication can be improved. On the other hand, if a part of the unit cell on the poly unit wafer fails, the poly unit wafer can be cut into sub-wafers with fewer unit cells to remove the failed unit cell, wherein the failed unit cell is removed. Subsequent sub-wafers can still be used normally, so that the usable rate (yield) of the wafer can be improved.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧ wafer

100, 100', 100" ‧ ‧ multi-cell wafer

110, 110_1, 110_2‧‧‧ separated spaces

120, 120_D, 120_L, 120_R, 120_U‧‧‧ signal transmission line group

140, 140', 140_8, 140_9, 140_12, 140_13, 140_14, 140_18, 140_P, 140_M, 540, 540_7, 540_8, 540_14‧‧ unit cell

145‧‧‧ solder pads

180‧‧‧Semiconductor substrate

241, ID, 641, 643‧ ‧ identification code

290, 390_1, 390_2‧‧‧ cutting line

332, 334, 336, 338‧‧‧ sub-wafer

445‧‧‧Interface circuit

447‧‧‧Detection line

640, 642, 644‧‧‧ circuits

BUF‧‧‧ buffer

DS‧‧‧Detection signal

GND‧‧‧ ground terminal

R1, R2‧‧‧ resistance

VDD‧‧‧ power terminal

W1‧‧‧ signal line

The following drawings are a part of the specification of the invention, and illustrate the embodiments of the invention FIG. 1 is a schematic diagram of the structure of a polycrystalline silicon wafer in a wafer according to an embodiment of the invention. 2 is an enlarged schematic view of a unit cell of a poly unit cell wafer according to an embodiment of the invention. 3 is a schematic view of a cut of the poly unit cell of FIG. 1. 4 is a schematic structural view of a interface circuit and a detection line in the unit cell of FIG. 1. FIG. 5 is a schematic structural diagram of a poly unit wafer in a wafer according to another embodiment of the invention. 6 is a schematic view showing the structure of a unit cell of the poly unit cell of FIG. 1. 7 is a schematic diagram of an application of the polycrystalline cell wafer of FIG. 1. FIG. 8 is a schematic structural diagram of a poly unit wafer in a wafer according to still another embodiment of the invention.

10‧‧‧ wafer

100‧‧‧Multicell wafer

110‧‧‧ separated space

120, 120_D, 120_L, 120_R, 120_U‧‧‧ signal transmission line group

140, 140_8, 140_12, 140_13, 140_14, 140_18‧‧‧ unit cell

180‧‧‧Semiconductor substrate

Claims (13)

A polycrystalline cell wafer comprising: a semiconductor substrate; a plurality of unit cells disposed on the semiconductor substrate, each of the unit cells having a space between adjacent cells; and a plurality of signal transmission line groups, The signal transmission line groups are respectively disposed on at least a portion of the spaced spaces, and are respectively configured to perform signal transmission between at least a portion of adjacent cells, wherein the poly unit wafer is usable, and the poly unit wafer Cutting through a portion of the spaced spaces to cut a portion of the signal transmission line groups, such that the poly unit wafer is divided into a plurality of sub-wafers, wherein the cut portions of the sub-wafers are still usable, wherein the Each of the unit cells includes: at least one detection line for automatically detecting whether the signal transmission line group between the unit cell and the adjacent unit cell is cut off, and accordingly generating a detection signal. The polycrystalline cell wafer of claim 1, wherein at least one of the cells has a plurality of pads, wherein the pads are coupled to an external wafer for signal transmission. The polycrystalline cell wafer of claim 1, wherein the signal transmission line groups are respectively configured to perform data transmission or power transmission between the at least partially adjacent cells. The polycrystalline cell wafer of claim 1, wherein each of the sub-wafers has a different number of unit cells. The multi-cell wafer of claim 1, wherein the at least one detecting circuit comprises: a buffer, the input end of the buffer transmitting the signal transmission line between the unit cell and the adjacent unit cell a signal line in the group is coupled to a power supply end, and an output end of the buffer is used to generate the detection signal; a first resistor is coupled between the input end of the buffer and a ground end And a second resistor coupled between the input of the buffer and the output of the buffer. The polycrystalline cell wafer of claim 1, wherein each of the unit cells further comprises: at least one interface circuit coupled to the signal transmission line between the unit cell and the adjacent unit cell And the group is coupled to the at least one detection line to receive the detection signal, wherein when the at least one detection line detects that the signal transmission line group between the unit cell and the adjacent unit cell is cut off The at least one interface circuit automatically isolates the connection between the unit cell and the signal transmission line group. The polycrystalline cell wafer of claim 1, wherein each of the unit cells further comprises: a plurality of circuits, each of the circuits having an identification code, wherein the identification code is read only And unique, to identify each of the circuits. The multi-cell wafer of claim 1, wherein each of the unit cells further comprises: an identification code, the identification code being read-only and unique for the unit cells Each of them is identified. The poly unit cell of claim 8, wherein each of the unit cells cooperates with a software, and each of the unit cells determines whether the software is allowed to be used according to the identification code. . The poly unit cell of claim 8, wherein each of the unit cells is configured to execute a software, and each of the unit cells uses the identification code as a key to the software. Encrypt or decrypt. The polycrystalline cell wafer of claim 8, wherein a portion of the cells are used to simultaneously execute a software, and the identification code of one of the portions of the unit cells is used as a key. To encrypt or decrypt the software. The polycrystalline cell wafer of claim 1, wherein the functions of the unit cells are not identical. The polycrystalline cell wafer of claim 1, wherein the cells are not completely identical in area.