TWI581435B - High voltage MOSFET structure and processing method - Google Patents

Description

High voltage MOSFET structure and processing method

The present invention generally relates to the structure and fabrication process of semiconductor power devices. More specifically, the present invention relates to a simplified high voltage (HV) metal oxide semiconductor field effect transistor (MOSFET) simplified structural configuration and fabrication process.

Conventional techniques for fabricating high voltage (HV) MOSFET devices still face many difficulties and limitations due to various trade-offs that further improve device performance. In vertical semiconductor power devices, there is a trade-off between the source resistance of one of the performance properties (ie, the on-state resistance, commonly referred to by RdsA, ie, Rds x active area) and the breakdown voltage that the power device can withstand. To address the difficulties and limitations of these performance trade-offs, we have studied a variety of device structures. A special P-synthesis (PCOM) structure has also been specially developed for this purpose. Specifically, a high voltage (HV) MOSFET device with a PCOM structure includes a P-type doped region surrounding the sidewalls of the mask trench for P-type body regions and mask trenches on the top surface of the semiconductor substrate. A connection is formed between the lower P-type doped regions. In order to form sidewall doped regions around the trench sidewalls, conventional methods employ an additional implantation mask with an implant opening to perform an implant process on the sidewalls of the trench at selected locations of the mask trench. In addition, to ensure that dopant ions are implanted into the bottom of the trench sidewalls, high energy dopant ions must be implanted. Need to use Additional masking and high energy doping ion processes add to the cost of fabrication. In addition, high energy implantation and diffusion processes at the bottom of the trench sidewalls are generally not easy to control the formation of doped regions. The uncertainty of these preparation processes leads to drastic changes in device performance, making it inconvenient to accurately control the quality of the preparation.

1A is a plan view showing an implantation mask 100 used in a conventional process, and FIGS. 1B and 1C are diagrams showing a high voltage (HV) MOSFET fabricated by a conventional process along lines 1-1' and 2-2' of FIG. 1A. Two cross-sectional views of the device structure. As shown in FIG. 1A, the injection opening 11 is located on a selected area of the trench 12. In order to prepare a MOSFET device capable of withstanding high power operation, a PCOM (P-synthesis) structure is formed. In the PCOM MOSFET structure, a dedicated doped region is formed in the portion 16 below the P-type body region 13 through the implantation opening 11, thereby, as shown in FIG. 1C, the P-type body region and the trench are formed. The P-type doped regions 15 under the trenches 12 are connected. At the same time, in other regions, by implanting the mask 100, formation of a doped region under the body region is prevented. The implantation mask shown in Fig. 1A prevents the dopant from being implanted through the sidewalls of the trench in the region around 1-1'. Fig. 1B shows a structure in which a doped region surrounds the sidewall of the trench, connecting the body region and the doped region below the bottom of the trench. As shown in FIG. 1B-1C, the high voltage (HV) MOSFET device further includes a planar gate 17 formed over the semiconductor substrate, and a source 18 and a P++ junction 19 formed on top of the P-type body region 13. .

The conventional fabrication process as shown in Figures 1A through 1C requires an additional implantation mask. In addition, high energy implantation of a P-type dopant, such as a P-type dopant implant in the Mev region, is required, as shown in FIG. 1C, forming a doped region below the body region surrounding the trench sidewall. Additional masking and high energy injection requirements increase manufacturing costs.

Therefore, it is necessary for those skilled in the art to improve the manufacturing method of the power device, especially the device with the PCOM structure, to solve the above technical limitations. SUMMARY OF THE INVENTION It is an object of the present invention to provide a new and improved method of fabrication and device structure that eliminates the need for additional implantation masks and high energy implants to overcome the aforementioned difficulties and limitations.

Therefore, an aspect of the present invention is to provide a new and improved preparation method capable of implanting a P-type doped region of a trench sidewall without an additional implantation mask and high energy doping implantation, thereby reducing the fabrication cost. And solve the above limitations and difficulties.

Specifically, an aspect of the present invention is that the implantation process utilizes a special structure of the sidewalls at the end of the trench, the sidewalls perpendicular to the longitudinal direction of the trench are exposed, opening the space as part of the trench. Since there is no need to penetrate the semiconductor substrate, only the opening space of the trench can be used to emit the doping ions. Therefore, the P-type doping region can be implanted through the end trench, without using high-energy doping ions. The bottom P-type doped region formed at the bottom of the trench is touched. A PCOM-doped region connecting the P-type body region formed on the top surface of the semiconductor substrate and the P-type doping region at the bottom of the trench is formed only at the sidewall of the trench end point. Compared with the traditional method, high energy doping injection is not required, which saves cost.

In addition, one aspect of the present invention is that the implantation process utilizes a special structure of the sidewalls of the trench at which the trench is bent, where the sidewalls perpendicular to the longitudinal direction of the trench are exposed, opening the space as part of the trench. Additionally, one aspect of the present invention is that the implantation process utilizes a special configuration of the sidewalls of the trench at the trench recess where the sidewalls perpendicular to the longitudinal direction of the trench are exposed, opening the space as part of the trench. Since there is no need to penetrate the semiconductor substrate, only the opening space of the trench can be transmitted, and the dopant ions can be emitted. Thus, through the sidewalls, P-type doping regions can be implanted, and the bottom P-type doped regions formed at the bottom of the trench can be accessed without using high energy doping ions.

Another aspect of the present invention is that the sidewall doping implantation is performed in the longitudinal direction of the trench above the trench sidewall at the end of the trench, the trench curvature and the trench recess, and the implantation process can be better controlled. . More precise control of device performance parameters and reduced manufacturing process variations due to uncertainty caused by high energy doping implantation.

In a preferred embodiment, the present invention provides a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes a plurality of mask trenches formed on top of the semiconductor substrate, each mask trench having a trench end point, the end sidewalls being perpendicular to the longitudinal direction of the trench and starting vertically from the top surface The lower portion extends to the bottom surface of the groove. The semiconductor power device further includes a trench bottom P-type doped region disposed under the trench bottom surface, and a sidewall P-type doped region disposed along the end sidewall, wherein the sidewall P-type doped region is along the trench The end sidewall extends vertically downward to access the P-type doped region at the bottom of the trench and connects the P-type doped region at the bottom of the trench to the P-type body region formed on the top surface of the semiconductor substrate.

In another preferred embodiment, the present invention provides a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes a plurality of mask trenches formed on top of the semiconductor substrate, each mask trench having a plurality of minute bends in a predetermined region, the trench sidewalls being perpendicular to the longitudinal direction of the trench and from The top surface begins to extend vertically to the underside of the trench. The semiconductor power device further includes a trench bottom P-type doped region disposed under the trench bottom surface, and a sidewall P-type doped region disposed along the curved sidewall, wherein the sidewall P-type doped region is along the trench The curved side wall extends vertically downward to touch the bottom of the groove P-type The doped region is connected to the bottom P-type doped region of the trench to the P-type body region formed on the top surface of the semiconductor substrate.

In another preferred embodiment, the present invention provides a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes a plurality of mask trenches formed on top of the semiconductor substrate, each mask trench having a plurality of minute recesses in a predetermined region, the trench sidewalls being perpendicular to the longitudinal direction of the trenches, and Vertically extending from the top surface to the bottom surface of the groove. The semiconductor power device further includes a trench bottom P-type doped region disposed under the trench bottom surface, and a sidewall P-type doped region disposed along the sidewall of the recess, wherein the sidewall P-type doped region is along the trench The recessed sidewalls of the trench extend vertically downward to contact the P-type doped region at the bottom of the trench and connect the P-type doped region at the bottom of the trench to the P-type body region formed on the top surface of the semiconductor substrate.

In a preferred embodiment, the present invention also provides a method for fabricating a semiconductor power device on a semiconductor substrate. The method comprises the steps of: a) using a hard oxide mask over the semiconductor substrate, then forming a pattern of the hard oxide mask according to the predefined trench structure; b) etching through the patterned hard mask, Forming a plurality of trenches on the top of the semiconductor substrate, each trench having a trench end point, a slight bend or a minute recess, the sidewall being perpendicular to the longitudinal direction of the trench and extending vertically downward from the top surface To the bottom surface of the trench; c) using a vertical (zero) high energy implant to form a trench bottom P-type doped region under the trench bottom surface, and then remove the hard mask; d) above the trench sidewall and the bottom surface of the trench, Growing an oxide liner; and e) utilizing a low energy tilt implant in which dopant ions are implanted along a predetermined tilt angle, sidewall P-type doped regions are formed along vertical sidewalls, and sidewall P-type doped regions are vertically along trench sidewalls Extend downward to touch the bottom of the groove The P-type doped region is connected to the P-type body region formed on the top surface of the semiconductor substrate. In one embodiment, the implanted dopant ion tilt angle is approximately 45 degrees from the sidewall surface.

These and other features and advantages of the present invention will become apparent to those skilled in the <RTIgt;

11‧‧‧Injection opening

12‧‧‧ trench

13‧‧‧P-type body area

15‧‧‧P-type doped area

16‧‧‧Area

17‧‧‧ planar gate

18‧‧‧ source

19‧‧‧P++ connector

100‧‧‧Injection mask

101‧‧‧Substrate

110‧‧‧Terminal end wall

110’‧‧‧Terminal end wall

111‧‧‧hard mask

115‧‧‧Thin oxide layer

120‧‧‧ trench

120’‧‧‧ trench

125'‧‧‧ oxide layer

130‧‧‧P-type doped area

140‧‧‧P-type doped area

142‧‧‧Sacrificial materials

200‧‧‧ trench

210‧‧‧Bend

220‧‧‧ side wall

250‧‧‧ trench

260‧‧‧ notch

270‧‧‧ side wall

T‧‧‧thickness

T2‧‧‧ thickness

T1‧‧‧ thickness

Figure 1A shows a top view of the implantation mask used in the conventional process, and Figs. 1B and 1C show the grooves grown through the implantation mask shown in Fig. 1A, in two different directions, two of the PCOMP structures. Side view.

Figure 2A shows a top view of a conventional trench structure on a semiconductor substrate.

The side views shown in Figures 2B, 2C-1, 2C-2, 2D-1, 2D-2, 2E-1, and 2E-2 respectively show the preparation of a PCOMP structure in two different orientations of the trench of the present invention. Process steps.

The side views shown in Figs. 2F-1 and 2F-2 show alternative embodiments shown in Figs. 2E-1 and 2E-2.

The side views shown in Figs. 2G-1, 2G-2, 2H-1, and 2H-2 respectively show another alternative embodiment shown in Figs. 2E-1 and 2E-2.

Figure 3A shows a top view of an alternative structure of trenches of different lengths on a semiconductor substrate of the present invention.

Fig. 3B shows a plan view of the semiconductor substrate shown in Fig. 3A after vertical and oblique implantation to form a PCOMP structure.

Figure 4A shows a top view of an alternative structure of a trench on a semiconductor substrate in accordance with one embodiment of the present invention, wherein the trench has a non-linear portion containing a slight curvature.

Fig. 4B is a plan view showing the semiconductor substrate shown in Fig. 4B after vertical and oblique implantation to form a PCOMP structure.

Figure 5A shows a top view of another alternative structure of a trench on a semiconductor substrate in accordance with one embodiment of the present invention, wherein the trench has a non-linear portion containing minute recesses.

Fig. 5B is a plan view showing the semiconductor substrate shown in Fig. 5A after vertical and oblique implantation to form a PCOMP structure.

The technical solution of the present invention will be further described below with reference to the accompanying drawings.

Figure 2A shows a top view of a conventional trench structure on a semiconductor substrate. 2B, 2C-1, 2C-2, 2D-1, 2D-2, 2E-1, 2E-2, 2F-1, 2F-2, 2G-1, 2G-2, 2H-1 and 2H-2 The side views shown in the figures represent process steps for preparing a PCOM structural arrangement along line 1-1' and line 2-2' in Figure 2A, respectively, in various embodiments of the present invention.

As shown in FIG. 2A, a plurality of trenches 120 are formed on the semiconductor substrate 101, each of which has a trench end sidewall 110. A plurality of trenches 120 are prepared as follows: as shown in FIG. 2B, an oxide hard mask 111 is deposited over the semiconductor substrate; then, a hard mask is formed according to a predefined structure similar to that shown in FIG. 2A a pattern of the film 111; then anisotropically etching away the semiconductor substrate through the patterned hard mask 111 101, a plurality of trenches 120 are formed. As shown in FIGS. 2C-1 and 2C-2, each trench 120 has a trench end point 110.

First, a vertical high-energy P-type doping implant (zero degree) is performed, and a patterned hard mask 111 is formed to form a P-type doped region 130 under the bottom surface of the trench 120, as shown in FIGS. 2D-1 and 2D-2. Show. The P-type doped region 130 acts as a RESURF at the bottom of the trench, providing maximum breakdown voltage (BV) latching performance.

As shown in Figures 2E-1 and 2E-2, the hard mask 111 is removed, and then a thin oxide is deposited on the top surface of the substrate 101, on the sidewalls and bottom surface of the trench 120, and at the end sidewall 110. Layer 115, the same thickness is indicated by t. A low energy tilted P-type dopant implant is then performed, such as a 45 degree angle. In the 2E-1 diagram, a P-type doped region 140 is prepared on the top surface of the substrate, under the bottom surface of the trench 120, and at the top of the trench sidewall. In the 2E-2 diagram, oblique implanting is also performed at the end face sidewall 110 at the end of the trench 120, so that the entire length along the trench end sidewall 110, below the bottom surface of the trench 120, and at the top of the substrate 101 On the surface, a P-type doping region 140 is prepared. A PCOMP structure configuration is obtained, the formed P-type doped region 140 is along the entire length of the trench end sidewall 110, and the trench end sidewall 110 connects the P-body region (not shown) to the bottom P-type doping. Zone 130 requires no additional implant mask and does not require high energy implants. The fabrication process continues with standard process steps to complete the entire device.

In the 2E-1 and 2E-2 diagrams, as described above, a thin oxide layer 115 of uniform thickness t is deposited on the top surface of the substrate 101 and on the sidewalls and the bottom surface of the trench 120 and the end sidewall 110. The side views shown in Figures 2F-1 and 2F-2 are similar to those in Figures 2E-1 and 2E-2. In the present embodiment, the oxide layer 125' is deposited on the top surface of the substrate 101 and the bottom surface of the trench 120. Upper, the thickness t2 of the oxide layer 125' is greater than the thickness t1 of the oxide layer 125, and the oxide layer 125 covers the sidewall of the trench 120 and the trench end sidewall 110. Therefore, after the low energy tilt angle implantation is performed, as shown in FIG. 2F-1, the P-type doping region 140 is formed only at the top portion around the sidewall of the trench 120. In the 2F-2 diagram, the P-doped region 140 is formed only along the entire length of the trench end sidewall 110. Therefore, the PCOMP structure configuration is obtained, and the doped region 140 is formed along the entire length of the trench end sidewall 110 to connect the P-type body region (not shown) formed on the bottom surface of the semiconductor substrate to the bottom P-type. The doped region 130 eliminates the need for an additional implantation mask and does not require high energy implantation. The preparation of the entire device was completed in accordance with standard preparation procedures.

In an alternative embodiment, if a thin oxide layer 115 having a uniform thickness t is deposited on the top surface of the substrate 101, as well as the sidewalls and bottom surfaces of the trenches 120 and the end sidewalls 110, and 2E-1 and 2E-2 Similar to the figure, the oblique injection of the oxide layer at the bottom of the trench 120 is prevented. Before the oblique implant is performed, as shown in the 2G-1 and 2G-2 diagrams, a sacrificial material 142 is deposited on the bottom of the trench 120 for deposition. The thickness is controllable. Layer 142 can be a high density plasma (HDP) oxide photoresist, TEOS, and the like. Therefore, after the low energy tilt angle implantation, as shown in FIG. 2G-1, the P-type doping region 140 is formed only on the top of the sidewall around the trench 120 and the top surface of the semiconductor substrate 101, in the second G-2 diagram. The P-doped region 140 is formed only along the entire length of the trench end sidewall 110 and the top surface of the semiconductor substrate 101. Then, prior to the next process step of filling the trenches 120 with polysilicon, as shown in Figures 2H-1 and 2H-2, the sacrificial material layer 142 is removed first. The preparation of the entire device was completed in accordance with standard preparation procedures.

Figures 3A-3B illustrate an alternate embodiment of the present invention. As shown in FIG. 3A, a top view of an optional trench structure on the semiconductor substrate 101 of the present invention, The trench end point is prepared at a predetermined area, and the length of the trench 120' can be adjusted (eg, the length of the trench 120' is smaller than the length of the trench 120 shown in FIG. 2A), thereby adjusting the density of the trench end sidewall 110' and The density of the PCOMP structure configuration, and thus the PCOMP structure with the P-type doped region is disposed along the entire length of the trench end sidewall, connecting the P-type body region formed on the top surface of the semiconductor substrate to the trench bottom P- The doped region, the PCOMP structure is distributed over the entire area of the semiconductor substrate. Fig. 3B is a plan view showing the semiconductor substrate 101 after the implantation process by the above-described preparation of the PCOMP structure. As shown in FIG. 3B, a P-type dopant is vertically implanted through the trench hard mask, and a P-type doping region 130 may be formed under the bottom surface of the trench 120', and obliquely implanted at the trench end sidewall 110'. The P-type dopant can form a P-type doped region 140 along the entire length of the trench end sidewall 110'. Depending on the space between the two end points of two adjacent trenches 120', the P-type doped regions 140 may be merged together, as shown in Figure 3B, or spaced apart from one another (not shown).

Figures 4A-4B show an alternative embodiment of the invention. 4A is a plan view showing an alternative trench structure on the semiconductor substrate 101 of the present invention. As shown in FIG. 4A, each trench 200 has a nonlinear portion, which is minutely formed in a predetermined region. The composition is curved to form the trench sidewalls 220 in a direction that is not in line with the axial direction of the trenches. In the bend 210 shown in FIG. 4A, the trench sidewall 220 is perpendicular to the axial direction of the trench 200. Therefore, the entire vertical length of the side wall 220 is exposed, and the doping ions incident along the axial direction of the groove with the oblique angle perform oblique ion implantation. Since the entire vertical length of the trench sidewalls is exposed, oblique ion implantation can be performed with low energy dopant ions to reach the bottom of the trench sidewalls 220. Fig. 4B is a plan view showing the semiconductor substrate 101 after the implantation process by the above-described preparation of the PCOMP structure. As shown in Figure 4B As shown, the P-type dopant is vertically implanted through the trench hard mask, and a P-type doped region 130 is formed under the bottom surface of the trench 200, and the tilt angle P at the trench sidewall 220 and the trench end sidewall 110 The -type doping implant forms a P-type doped region 140 along the entire length of the trench sidewall 220 and the endpoint sidewall 110.

Figures 5A-5B illustrate an alternate embodiment of the present invention. Figure 5A shows a top view of an optional trench structure on the semiconductor substrate 101 of the present invention. As shown in Figure 5A, each trench 250 has a non-linear portion, which is tiny in a predetermined area. The recesses 260 are formed to form the trench sidewalls 270 in a direction that is not in line with the axial direction of the trenches. In the recess 260 shown in FIG. 5A, the trench sidewall 270 is perpendicular to the axial direction of the trench 250. Therefore, the entire vertical length of the side wall 270 is exposed, and the doping ions incident along the axial direction of the groove with the oblique angle perform oblique ion implantation. Since the entire vertical length of the trench sidewalls is exposed, oblique ion implantation can be performed with low energy dopant ions to reach the bottom of the trench sidewalls 270. Fig. 5B is a plan view showing the semiconductor substrate 101 after the implantation process by the above-described preparation of the PCOMP structure. As shown in FIG. 5B, the P-type dopant is vertically implanted through the trench hard mask, a P-type doped region 130 is formed under the bottom surface of the trench 250, and the trench sidewall 270 and the trench are floated at the recess 260. An oblique angle P-type doping implant at the end sidewall 110 forms a P-type doped region 140 along the entire length of the trench sidewall 220 and the endpoint sidewall 110.

In general, the optional trench structure as shown in Figs. 4A, 4B and 5A, 5B can be further configured by preparing the trenches to form portions of the width reduction or enlargement in a specific region. Forming trench sidewalls in the trench portions of these regions, in a direction perpendicular to the axial direction of the trenches, thereby exposing the entire vertical length of the sidewalls, allowing implanted ions to pass through Throughout the vertical depth of the sidewall, high energy ion implantation is not required when preparing a PCOMP configuration. In addition, an optional trench structure can be configured by preparing trenches with laterally complete structures to keep the trenches exposed for full vertical depth implants in the PCOMP structure configuration without the need for high energy ion implantation.

While the invention has been described in detail, the preferred embodiments of the invention Various changes and modifications will no doubt become apparent to those skilled in the art after reading the Detailed Description. Accordingly, the appended claims are intended to cover all such modifications and modifications

130‧‧‧P-type doped area

140‧‧‧P-type doped area

200‧‧‧ trench

Claims (10)

A semiconductor power device disposed in a semiconductor substrate, comprising: a trench formed on a top portion of the semiconductor substrate, extending axially along the trench, wherein the trench further includes a nonlinear portion, the non- The linear portion includes a non-linear trench sidewall extending in a surface of the semiconductor substrate that is not in the same direction as the trench axis, such that the entire vertical length of the non-linear trench sidewall is exposed to directly receive the oblique tilt injection along the trench Doping ions, along the entire vertical length of the sidewall of the nonlinear trench, forming a sidewall doping region; and a trench bottom doping region disposed under the trench bottom surface, the sidewall doping region along the nonlinear trench sidewall Extending downward to touch the doped region at the bottom of the trench, picking up the doped region at the bottom of the trench to the top surface of the semiconductor substrate. The semiconductor power device of claim 1, wherein the non-linear portion of the trench comprises a micro-curved trench comprising a trench sidewall that is perpendicular to an axial direction of the trench. The semiconductor power device of claim 1, wherein the non-linear portion of the trench comprises a trench recess, each trench recess having a recessed portion having a reduced width of the trench, including perpendicular to the The groove recess sidewall in the axial direction of the groove. The semiconductor power device according to claim 1, wherein The trench is lined with an insulating layer that covers the sidewall and the bottom surface of the trench. The semiconductor power device of claim 1, wherein the trench is lined with an insulating layer covering the sidewall and the bottom surface of the trench, wherein the insulating layer covers the sidewall and the bottom surface of the trench The thickness is approximately the same. The semiconductor power device of claim 1, wherein the trench is lined with an insulating layer covering the sidewall and the bottom surface of the trench, wherein the insulating layer covers the sidewall to have a thickness smaller than the insulating layer. The layer covers the thickness of the bottom surface of the trench. The semiconductor power device of claim 1, wherein the non-linear portion of the trench is disposed at a specified position over the entire area of the semiconductor substrate. The semiconductor power device of claim 1, wherein the device further comprises: a high voltage MOSFET device. The semiconductor power device of claim 1, wherein the device further comprises: a high voltage IGBT device. A method for fabricating a semiconductor power device on a semiconductor substrate, the method comprising: providing a hard mask over the semiconductor substrate, and forming a pattern of the hard mask according to a predefined trench structure; Etching the semiconductor substrate through the patterned hard mask, forming a plurality of trenches on the top of the semiconductor substrate, along the surface of the semiconductor substrate Parallel trenches extend axially, wherein each trench has a non-linear portion comprised of non-linear trench sidewalls extending in the same direction as the trench axis on the surface of the semiconductor substrate; utilizing vertical high energy implantation, Forming the trench bottom doping region under the bottom surface of the trench, and then removing the hard mask; depositing an insulating layer covering the trench sidewall and the trench bottom surface; and performing low energy oblique implantation along the trench axis so that Forming a sidewall doped region along the entire vertical length of the sidewall of the nonlinear trench, wherein the sidewall doped region extends downward along the entire vertical length of the nonlinear trench to touch the doped region at the bottom of the trench to pick up the trench The bottom of the trench is doped to the top surface of the semiconductor substrate.