TWI579979B - Power semiconductor device and method of manufacturing same - Google Patents

Description

Power semiconductor device and method of manufacturing same

The present invention relates generally to packaging of power semiconductor devices, and more particularly to a power semiconductor device having an efficient heat dissipation effect and having an ultra-thin size, and a method of fabricating the same.

In power transistor applications, the final overall size and heat dissipation of the semiconductor device are two important parameters. The heat dissipation performance of a semiconductor device is usually improved by exposing a part of the electrodes of the transistor, but the implementation process is often difficult to control and the heat dissipation effect is not good. Figure 1A shows a series of tank-type DirectFET MOSFETs developed by International Rectifier IR. The company demonstrated the technology in "Board Mounting Application Note 2002" in January 2002 under the theme "DirectFET Technology". Suitable for industrial applications requiring very low on-resistance RDSon, such as high power DC motors, DC/AC inverters, and high current switching applications such as dynamic ORing hot swap and electric fuses. In FIGS. 1A to 1B, the canned structure 10 as a metal outer casing is provided with a square groove-shaped cavity, and a periphery of the canned structure 10 is left with a horizontally extending flat peripheral portion, especially at the periphery. A pair of opposite lead portions 10a, 10b are provided on the side. A MOSFET die 11 is built into the open cavity, and the drain electrode on the back of the MOSFET die 11 is directly adhered to the outer casing of the canned structure 10 while the MOSFET is The source electrode 11a and the gate electrode 11b on the front surface of the die 11 can be coplanar with the pair of lead portions 10a, 10b of the can-fill structure 11. Thereby, the source electrode 11a, the gate electrode 11b, and the two lead portions 10a, 10b can be soldered to the pads on the PCB circuit board in synchronization. The DirectFET package has an ultra-thin thickness of no more than 0.7mm, providing an ideal solution for space-constrained high-power industrial power supply designs.

2A-2B are a series referred to as an X-FET package, and FIG. 2A shows a schematic view of the wafer holder 20 before being unpatched, the wafer holder 20 having a recessed flat-shaped valley as a patch area. 20b, and a platform portion 20a as a lead having a relatively high position relative to the valley portion 20b and extending in a horizontal manner on both sides of the valley portion 20b. In FIG. 2B, the bottom electrode of the MOSFET wafer, which is not illustrated, is adhered to the upper surface of the valley portion 20b. After the molding step is completed, the source electrode 21a and the gate electrode 21b on the front surface of the MOSFET wafer are coplanar with the upper surface of the land portion 20a. As shown in FIG. 2B, the wafer is completely encapsulated and not visible by the molding body 25. However, it is necessary to ensure that the source electrode 21a, the gate electrode 21b, and the land portion 20a are exposed from the molding body 25 as electrode terminals.

In these prior art, it can be found that the opposite sides of the wafer are provided with a substantially symmetrical set of pins, such as the lead portions 10a, 10b of FIG. 1B and a pair of platform portions 20a as pins of FIG. 2B. Bilateral symmetrical pin packaging generally requires a larger package size to accommodate the set of pins. Furthermore, based on the consideration of coplanarity, it is usually required that the thickness of the MOSFET wafer must be controlled very accurately. For example, the thickness of the MOSFET wafer must be exactly the same as the depth of the cavity in FIG. 1B, or the thickness of the wafer should be the same as that in FIG. 2A. The depth of the depressed valley portion 20b is uniform, and such a restriction condition is extremely likely to cause an extremely narrow thickness error range of the wafer, which poses a great challenge to equipment precision and cost control. Secondly, the package of Figure 2B often needs to be followed by a larger area pin. The platform portion 20a is plated with a metal layer. Before this, the gate electrode 21b and the source electrode 21a need to be covered with a peelable tape, and the bare surface of the platform portion 20a is separately plated with a metal layer, and then the tape is peeled off. This will undoubtedly lead to more complicated processes.

The present invention discloses a power semiconductor device comprising: a metal base having an upper portion and a lower portion respectively located on two planes shifted up and down, the position of the upper portion being set higher than the position of the lower portion; a film layer on the upper surface of the metal base, wherein a plurality of contact holes penetrating the film layer are disposed in a region of the film layer over the upper surface of the upper portion, and the film layer covers the upper surface of the lower portion Locating at least one opening through the film layer; a power MOSFET wafer adhered to the opening, the electrode on the bottom surface of the wafer is adhered to the region where the upper surface of the lower portion is exposed to the opening by the conductive material; and further includes a plurality of metal bumps And a block, wherein a metal bump is disposed at an area where the upper surface of the upper portion is exposed to each of the contact holes, and at least one metal bump is disposed on each of the electrodes on the top surface of the wafer.

In an embodiment, the upper surface of the upper portion is disposed flush with the top surface of the wafer. In still other preferred variations, the upper surface of the upper portion is disposed slightly higher or lower than the top surface of the wafer.

In another embodiment, the method further includes: a plastic body covering the metal base, the wafer, and each of the metal bumps to which the film layer is attached, wherein the lower surface of the lower portion is from the bottom surface of the plastic body The top end exposed and the flattened metal bumps are exposed from the top surface of the molded body.

In another embodiment, the lower portion is exposed from the bottom surface of the molding body The lower surface is covered with a metallic coating such as a tin metal coating.

In another embodiment, the film layer is an aluminum metal layer having an aluminum oxide passivation layer on the upper surface thereof for reinforcing the bonding between the molding body and the film layer at the interface where the molding body and the film layer are bonded. Strength.

The invention further discloses a method for fabricating a power semiconductor device, comprising the steps of: first providing a lead frame comprising a plurality of metal pedestals, each metal pedestal having an upper portion and a lower portion respectively located on two planes offset from top to bottom The position of the upper portion is set to be slightly higher than the position of the lower portion, and the height is substantially equal to the thickness of one wafer; wherein a film layer attached to the upper surface of the metal base is provided with a film penetrating through the film layer a plurality of contact holes and at least one opening, wherein the contact holes are provided in a region of the film layer covering the upper surface of the upper portion, and the opening is provided in a region of the film layer covering the upper surface of the lower portion; a region of the lower portion of the lower portion of the metal base exposed to the opening is adhered to a wafer; and then a metal bump is implanted at a region where the upper surface of the upper portion is exposed to each of the contact holes, and is simultaneously disposed At least one metal bump is placed on each of the electrodes on the top surface of the wafer; thereafter the lead frame is cut to separate the metal base.

In one embodiment, the step of providing a metal pedestal having an upper portion and a lower portion includes: adhering the film layer to the upper surface of the metal pedestal in an initial state; then selectively etching the film a layer, a plurality of contact holes and at least one opening penetrating through the film layer are etched; thereafter, the flat metal base is stamped into a stepped shape, and in the punching step, the metal base is provided with a contact hole with the film layer A portion of the overlap of the regions is stamped into an upper portion, and another portion of the metal base overlapping the region of the film layer where the opening is provided is punched into an underlying portion.

In another embodiment, the method further includes after the metal bump is implanted The following step: performing a molding process of coating a lead frame, a wafer, and each of the metal bumps to which the film layer is attached, a coating layer in which the lower surface of the lower portion of each metal base is from the plastic sealing layer The bottom surface is exposed, and each metal bump is covered by the plastic sealing layer; the plastic sealing layer is ground and thinned until the metal bump is exposed, the top surface of each metal bump is flattened, and the top end surface of the metal bump is molded from the plastic The thinned top surface of the layer is exposed; while the lead frame is cut, the plastic sealing layer is also cut together to cut and break the laminate of the lead frame containing the plastic layer and the film layer between adjacent wafers.

In another embodiment, the method includes plating the lower surface exposed from the bottom surface of the plastic seal layer on the lower portion of each metal base after the molding process but before grinding the thinned plastic seal layer. A metal coating.

In another embodiment, the method, wherein the step of forming a film layer comprises laminating the film layer of a material of an aluminum metal layer to an upper surface of a flat metal base.

According to the packaging process disclosed by the present invention, the total thickness of the semiconductor device, that is, the pitch between the top surface and the bottom surface of the molded body can finally reach, for example, 0.25 to 0.35 mm, which is in line with the current trend of light weight and thinness of the current package size.

10‧‧‧canned structure

10a, 10b‧‧‧ pin department

11‧‧‧ MOSFET die

11a, 21a‧‧‧ source electrode

11b, 21b‧‧‧ gate electrode

20‧‧‧ Wafer holder

20b‧‧‧Shell Department

20a‧‧‧ Platform Department

25‧‧‧plastic body

101‧‧‧Metal base

1010‧‧‧Square metal base

101a‧‧‧Top part

101b‧‧‧lower part

1010-1, 1010-2‧‧ ‧ overlap

102‧‧‧film layer

102-1‧‧‧Opening area with contact holes

102-2‧‧‧Opened area

103a‧‧‧Contact hole

103b‧‧‧ openings

104‧‧‧MOSFET wafer

104a, 104b‧‧‧ electrodes

105a, 105b, 105c, 105'b‧‧‧ metal bumps

106‧‧‧plastic layer

1060‧‧‧plastic body

107‧‧‧Metal coating

200‧‧‧ lead frame

Figures 1A-1B are DirectFETs developed by IR Corporation.

2A-2B are conventional X-FET series packages.

Figure 3 is a bird's eye view of the metal base structure of the present invention.

4A to 4C are flow charts showing a method of manufacturing a metal pedestal with a film layer of the present invention.

5A to 5H are schematic views showing a manufacturing process of the power semiconductor device of the present invention.

6A to 6D show the completed power semiconductor device of the present invention.

Figure 3 shows a metal base 101 having an upper surface covered with a film layer 102, but the opposite lower surface of the metal base 101 is bare and does not cover any film layers. The material of the metal base 101 is, for example, copper. The metal base 101 includes an upper portion 101b and a lower portion 101a having a height difference from each other, and the flat upper portion 101b and the flat lower portion 101a are substantially integrally formed, and they are respectively located at two upper and lower portions The mutually parallel planes allow the metal base 100 to have a stepped structure. A plurality of contact holes 103a are etched in a region of the film layer 102 over the upper surface of the upper portion 101b. The contact holes 103a penetrate the thickness of the film layer 102, and the contact holes 103a are preferably arranged in a row on the same line. Further, at least an opening 103b is also etched in a region of the film layer 102 over the upper surface of the lower portion 101a, which also penetrates the thickness of the film layer 102. Thereby, a partial region of the upper surface of the upper portion 101b is exposed at the contact hole 103a, and a partial region of the upper surface of the lower portion 101a is exposed at the opening 103b. The shape of the contact hole 103a and the opening 103b is not limited herein. In some embodiments, the opening 103b should be capable of matching a square shape of the wafer to form a square opening, and the contact hole 103a should be capable of being spherical with a solder ball or the like. The shape is matched to create a circular opening.

4A to 4C show how the integrally formed upper portion 101b and lower portion 101a are formed. As shown in FIG. 4A, a square metal base 1010 or a flat surface of a metal flat plate structure having an initial stage can form a thin film layer 102 by various means, although a commonly used coating method or deposition sputtering can be realized. However, the method adopted by the present invention is to apply the film layer 102. Laminated to the upper surface of the flat metal base 1010, the thin film layer 102 may be selected from a metal layer such as aluminum. Thereafter, as shown in FIG. 4B, a photoresist (not shown) is applied to the film layer 102, and an opening pattern is formed in the photoresist coating by conventional photolithography, and then photo-induced. The resist serves as an etching mask, and the contact hole 103a and the opening 103b are etched in the thin film layer 102, and then the photoresist is peeled off. As shown in FIG. 4C, the metal base 1010, which is originally in the form of a flat plate, is press-drawn into a final upper portion 101b (upset) and a lower portion by means of, for example, a punch or a stamp. The stepped metal base 101 of 101a (down-set) is formed to have an upper portion 101b and a lower portion 101a which are presented in an integrated structure. In the steps of FIGS. 4B to 4C, the overlapping portion 1010-1 of the metal base 1010 with the region 102-1 of the film layer 102 in which the contact hole 103a is opened is punched into the upper portion 101b, and the metal base is simultaneously synchronized. The overlapping portion 1010-2 of the region 102-2 of the film layer 102 having the opening 103b is punched into the lower portion 101a, so that the contact hole 103a is reserved in the film layer 102 to cover the upper portion. The area above the upper surface of 101b, and the opening 103b is reserved in the area where the film layer 102 covers the upper surface of the lower portion 101a, and the transition portion between the lower portion 101a and the upper portion 101b is also covered by the film layer. 102 is completely covered. In the stamping step, the film layer 102 preferably selects a metal having good ductility because sharp stamping or bending induces cracking of the bend line position of the film layer 102, and the material of the film layer 102 will be described later in detail.

5A shows a lead frame 200 including a plurality of metal pedestals 101 interconnected by ribs, and the metal pedestal 101 is also interconnected with the peripheral frame or support link of the lead frame 200 by the ribs. Even, the film layer 102 is actually attached to the lead frame 200. The layout of the metal base 101 on the lead frame 200 has various options, for example, any two different metal bases 101 appear in exactly the same arrangement, or an adjacent pair of metals The two metal pedestals 101 included in the susceptor 101 are set to be mirror-symmetrical to each other, and a plurality of sets of such metal pedestal 101 pairs are disposed in the lead frame 200. In FIG. 5B, the step of performing a patch is performed by coating a conductive material on a region where the upper surface of the lower portion 101a is exposed to the opening 103b in the thin film layer 102, a conductive material such as solder paste or conductive silver paste, etc., and a vertical power MOSFET. The wafer 104 is adhered to the lower portion 101a, and the electrode provided on the back surface or the bottom surface of the wafer 104 is adhered to the region of the upper surface of the lower portion 101a exposed to the opening 103b by a conductive material, such as a bottom electrode and a metal base. The base 101 is electrically connected. In addition, the patching step may also be a patching method such as eutectic soldering instead of coating a conductive material. In FIG. 5C, the step of performing ball implantation is performed by implanting a metal bump 105a in a region where the upper surface of the upper portion 101b is exposed to each of the contact holes 103a, and a metal bump on the electrode 104a on the top surface of the wafer 104. Block 105c, and a plurality of metal bumps 105b constituting a ball array on the top surface of the wafer 104, the metal bumps 105a-105b are typically solder balls or other alternative wedge-shaped metal blocks, etc., if Solder balls require reflow soldering. The electrodes 104a, 104b are, in particular examples, the gate and source of the MOSFET wafer 104, respectively.

In FIG. 5C, the advantage of selecting the aluminum metal layer for the film layer 102 is that the metal bumps 105a-105b having the solder adhesion effect and generally accompanied by the solder material generally have a higher infiltration with respect to the metal base 101 of the copper material. However, the metal bumps 105a to 105b have a lower wettability with respect to the metal aluminum. When the metal bump 105a is adhered to the region where the upper surface of the upper portion 101b is exposed to the contact hole 103a, even if the reflow is performed thereon, since the thin film layer 102 repels the material of the remote metal bump 105a, the metal bump 105a does not Since it is slightly melted, it spreads to the periphery and is less likely to collapse. As a result, the metal bump 105a is firmly and stably held at the contact hole 103a, and is not melted and expanded onto the film layer 102 outside the periphery of the contact hole 103a. In a In the embodiment, if the upper surface of the aluminum metal thin film layer 102 is naturally oxidized or artificially oxidized to form a passivation layer such as aluminum oxide, the wettability between the metal bump 105a and the passivation layer is worse, which is to maintain the metal bump 105a. The original appearance is more effective. The selection of the aluminum metal here is merely exemplary, and the material of any of the other thin film layers 102 may be less wetted than the metal bumps 105a and the metal base 101.

In FIGS. 5D to 5E, a conventional molding process is performed, and a molding compound 106 is formed by using a molding compound such as an epoxy resin. The molding layer 106 has a film layer 102 and a lead frame 200 including a plurality of metal pedestals 101. The wafer 104 and each of the metal bumps 105a-105c are coated in such a manner that the lower surface of the lower portion 101a of each metal base 101 is exposed from the bottom surface of the molding layer 106, as shown in FIG. 5E. At the same time, each of the metal bumps 105a, 105b, 105c is completely covered by the molding layer 106 without being exposed. The material of the film layer 102 is selected to be stronger than the bonding strength between the metal base 101 and the plastic sealing layer 106, especially after the upper surface of the film layer 102 induces the growth of the alumina passivation layer. The roughness of the upper surface of the film layer 102 is additionally increased to further strengthen the bonding force between the film layer 102 and the mold layer 106.

In FIG. 5F, after the molding process, a metal plating step is performed next, and a metal is plated on the lower surface of the lower portion 101a of each metal base 101 exposed from the bottom surface of the plastic sealing layer 106. A coating 107, such as a tin plated metal coating. As shown in FIG. 5G, a grinding step is performed to polish the thinned plastic sealing layer 106 from the original top surface of the molding layer 106 until the metal bumps 105a-105c are exposed and the molding layer 106 is thinned to a preset requirement. The thickness, the original upwardly raised top end of the metal bumps 105a-105c will be ground away, and the top end faces of the respective metal bumps 105a-105c that are flattened and flush with the thinned top surface of the plastic seal layer 106 are formed in synchronization to each other. The top end faces of the flattened metal bumps 105a to 105c are naturally exposed from the thinned top surface of the plastic seal layer 106. In FIG. 5H, a dicing process is performed to scribe a stack between adjacent wafers 104 comprising a mold layer 106, a film layer 102, and a leadframe 200 with the film layer 102, after the dicing step, adjacent The ribs belonging to the lead frame assembly between the metal pedestals 101 are cut, and the ribs between the metal pedestal 101 and the peripheral frame or the support link of the lead frame 200 are also cut, so that the metal pedestal 101 It was separated. At the same time, the molding layer 106 is cut to form a plurality of molding bodies 1060, each of which corresponds to a metal base 101 to which the film layer 102 is attached, a wafer 104 adhered to the metal base 101, and a wafer. Each of the metal bumps 105a to 105c implanted on the 104 is covered by the lower surface of the lower portion 101a from the bottom surface of the molding body 1060. Alternatively, the lower portion 101a may be molded from the plastic molding. The exposed lower surface of the bottom surface of the body 1060 is plated with a metal coating 107, and the top surface of each of the metal bumps 105a 105c is flattened from the thinned top surface of the original plastic sealing layer 106, that is, the top of the subsequent molding body 1060. The face is exposed.

In FIG. 6A, a top view of the top surface of the power semiconductor device is shown. The top surfaces of the planarized bumps of the metal bumps 105a-105c are exposed from the top surface of the molded body 1060. In FIG. 6B, the bottom surface of the power semiconductor device is shown. In a plan view, the lower surface of the lower portion 101a of the metal base is exposed from the bottom surface of the molded body 1060, and a metal coating 107 may be plated on the exposed lower surface of the lower portion 101a. The embodiment of Figure 6C can be slightly modified in conjunction with the embodiment of Figure 5C, in view of the large current flowing through the source, more metal bumps 105b can be placed on electrode 104b than in Figure 5C, with a larger number of metal bumps. The 105b can withstand a larger current value, and in this way, the on-resistance can be further effectively reduced. The embodiment of Figure 6D can be slightly modified based on the embodiment of Figure 5C to directly coat or place a larger size/volume of metal bumps 105'b On the electrode 104b, instead of the original plurality of metal bumps 105b, the size of the metal bumps 105'b is much larger than that of the metal bumps 105b. Similarly, the metal bumps 105'b pass through the packaging process of FIGS. 5D-5H. And obtaining a flattened tip end surface which is exposed from the top surface of the molded body 1060 and has a large area, and the top end surface area of the metal bump 105'b is larger than the top end surface area of the original metal bumps 105a to 105c. Many, the metal bumps 105'b can also carry a large current and function to reduce the on-resistance. The embodiment of Figure 6D is another method that is slightly modified based on the embodiment of Figure 5C, primarily to increase the density of the metal bumps 105b of Figure 5C, forcing the spacing between adjacent metal bumps 105b to decrease. When they are brought closer to each other, once the metal bumps 105b are slightly melted and deformed in the reflow step, the adjacent metal bumps 105b are brought into contact with each other and overlapped until all the metal bumps on the electrode 104b are adhered. The blocks 105b are fused together to form a large-sized metal bump 105'b during which the film layer 102 suppresses the deformation of the metal bump 105a at the contact hole 103a in Fig. 5C, even if we actively induce the metal bump on the electrode 104b. The blocks 105b are fused to each other, but the metal bumps 105a adjacent to each other at the upper portion are not fused.

In a preferred but non-limiting embodiment, as shown in FIG. 5D, the upper surface of the upper portion 101b is disposed to be coplanar with the top or front surface of the wafer 104, which ensures that all of the metal bumps are in FIG. 5G. The planarized tip faces formed in the steps are of the same size, and these standardized top faces are easily butt-fitted to match the standard pads of the same size on the PCB. However, unlike the prior art, it is normal that the upper surface of the upper portion 101b and the top surface of the wafer 104 are no longer coplanar, and there is no problem. The upper surface of the upper portion 101b is slightly higher or lower than the top surface of the wafer 104 in accordance with the inventive spirit of the present invention, because the top end faces of the metal bumps 105a, 105b, 105c in FIG. 5G are formed by grinding, It is ensured that the top end faces of the metal bumps 105a, 105b, 105c are absolutely coplanar, and their top end faces are flush with the thinned top surface of the plastic seal layer 106, the only difference being that when the metal bumps are After the position of any one of the 105a or the metal bumps (105b, 105c) is raised, the position thereof is relatively higher than the position of the remaining metal bumps, and the person who is raised in the same grinding step is removed by the grinding. The volume that is dropped is relatively large, and as a result, the exposed area/size of the top surface of the elevated person is larger than the exposed area/size of the top surface of the lower one. This result does not cause a substantial dilemma, as long as the area or size of the corresponding pad on the PCB is adjusted. From this, it can be known that the thickness tolerance range of the wafer 104 or the error or tolerance range of the height difference between the upper portion and the lower portion is extremely wide, and the object of the present invention can be attained by the prior art.

Observing the metal base 101, another advantage of the present invention is that only one side edge of the lower portion 101a is set to be bent obliquely upward and then extended in the horizontal direction from the upper portion 101b, which is essentially equivalent to the limitation. The area of the metal base 101. In a pair of opposite side edges of the lower portion 101a, only a single upper portion 101b is provided on one of the side edges of the pair of side edges, and the other side edge of the side edge has no metal base Any member of 101, whereby the level of the same size wafer is adhered compared to the canned structure 10 having the bilateral pins 10a, 10b of FIG. 1A or the wafer holder 20 having the double-sided pin platform portion 20a of FIG. 2A Under the circumstance, the overall size of the metal base 101 can be minimized, which is well known to those skilled in the art. According to the packaging process disclosed by the present invention, the total thickness of the semiconductor device, that is, the pitch between the top surface and the bottom surface of the molded body 1060 can finally reach, for example, 0.25 to 0.35 mm, which is in line with the current trend of light weight and thinness of the current package size.

While the present invention has been described above in terms of the preferred embodiments thereof, it is not intended to limit the invention, and it is to be understood that those skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. The scope of patent protection of the invention shall be subject to the application attached to this specification. The scope defined by the patent scope shall prevail.

105a, 105b, 105c‧‧‧ metal bumps

Claims (9)

A power semiconductor device comprising: a metal base having an upper portion and a lower portion respectively located on two upper and lower staggered planes; a film layer attached to the upper surface of the metal base; a plurality of contact holes, a region over the upper surface of the film layer covering the upper portion and penetrating the film layer; at least one opening disposed in a region covering the upper surface of the film layer of the lower portion, and extending through the a thin film layer; a wafer adhered to the opening, an electrode of the bottom surface of the wafer is adhered to a region of the upper surface of the lower portion exposed to the opening by a conductive material; a plurality of metal bumps, wherein the upper portion is upper The metal bumps are disposed on the surface of each of the contact holes, and at least one of the metal bumps is disposed on each of the top surfaces of the top surface of the wafer; wherein the lower portion is The lower surface of the bottom surface of the molding body is covered with a metal coating. The power semiconductor device according to claim 1, wherein an upper surface of the upper portion is disposed flush with a top surface of the wafer. The power semiconductor device according to claim 1, further comprising a plastic package covering the metal base, the wafer and the metal bumps to which the film layer is attached, wherein The lower surface of the lower portion is exposed from the bottom surface of the molding body, and the flattened top end surfaces of the metal bumps are exposed from the top surface of the molding body. The power semiconductor device according to claim 3, wherein the film layer is an aluminum metal layer having an aluminum oxide passivation layer on the upper surface thereof, where the interface between the mold body and the film layer is adhered The bonding strength between the molding body and the film layer is strengthened. A method of manufacturing a power semiconductor device, comprising the steps of: providing a lead frame comprising a plurality of metal pedestals, each metal pedestal having an upper portion and a lower portion respectively located on two upper and lower staggered planes; The contact hole and the at least one opening are in a film layer attached to the upper surface of the metal base, wherein the contact holes are disposed on a region of the film layer covering the upper surface of the upper portion, the opening Provided in a region of the film layer overlying the upper surface of the lower portion; a wafer is adhered to a region of the lower surface of each of the metal bases exposed to the opening; and each of the metal bases The upper surface of the upper portion is exposed to a region of each of the contact holes to implant a metal bump, and at least one metal bump is implanted on each electrode disposed on the top surface of the wafer; cutting the lead frame to separate the Some metal bases. The method of claim 5, wherein the step of providing the metal bases having the upper portion and the lower portion comprises: each of the metal bases having a flat shape at an initial stage Forming the thin film layer on the upper surface; selectively etching the thin film layer, etching the contact holes and the opening through the thin film layer; Stamping each of the metal bases into a step shape, and a first portion of each of the metal bases overlapping with a region where the film layer is provided with a contact hole is punched into the upper portion, each of the metal bases A second portion of the seat overlapping the region in which the film layer is provided with an opening is stamped into the lower portion. The method of claim 5, wherein after the implanting the metal bumps, the method further comprises the steps of: performing a molding process to form the lead frame to which the film layer is attached, the wafer and each metal a plastic sealing layer coated on each of the bumps, wherein a lower surface of each of the lower portions of the metal bases is exposed from a bottom surface of the plastic sealing layer, and each of the metal bumps is covered by the plastic sealing layer; Thinning the plastic sealing layer until the metal bumps are exposed, forming a top end surface of each of the metal bumps flattening and exposing the top end surfaces of the metal bumps from the thinned top surface of the plastic sealing layer; cutting the lead frame At the same time, the plastic sealing layer is cut together to cut and break the laminate of the lead frame including the plastic sealing layer and the film layer between the adjacent wafers. The method of claim 7, wherein, after the molding process, before grinding and thinning the plastic sealing layer, the method further comprises the step of: forming a lower portion of each of the metal bases from the plastic sealing layer A metal coating is applied to the exposed lower surface of the bottom surface. The method of claim 6, wherein the step of forming the film layer is to laminate the film layer to an upper surface of each of the metal pedestals, and the film layer is an aluminum metal Floor.