TWI578445B - Memory structure and method for manufacturing the same - Google Patents

Description

Memory structure and manufacturing method thereof 【0001】

This specification relates to a semiconductor structure and a method of fabricating the same. The present specification relates in particular to a memory structure and a method of fabricating the same.

【0002】

The memory generally includes an array region and a peripheral region. The memory cells located in the array region are controlled by wires such as bit lines and word lines. These wires extend from the array area to the peripheral area and connect the decoder to the peripheral area. In the array area, the wires can be formed in a regular environment. However, in areas such as near the boundary, the wires must be formed in a more complex environment. This complex environment can result in higher failure rates. For example, in a typical three-dimensional vertical gate NAND memory, the fan-out portion of the word line is formed outside of the stacked layers of bit lines. That is, the word line is fabricated across the boundaries of the bit line. Thus, based on the unpredictability of optical or etched behavior in the boundary regions of the bit lines, bridges may occur between word lines.

[0003]

In this specification, an improved memory structure is provided. The fan-out portion of the wire above the stacked layer is built in a virtual array area, that is, built on the virtual stack layer. As a result, the wires are integrally formed in a relatively regular area, which can reduce the failure rate.

[0004]

According to some embodiments, a method of fabricating a memory structure is provided. This manufacturing method includes the following steps. First, a plurality of stacked layers are formed on a substrate. The stacked layers are separated from one another by a plurality of trenches. The stacked layers respectively comprise a plurality of electrically conductive strings and a plurality of insulated strings that are alternately stacked. Forming a plurality of memory layers that conformally cover the stacked layers, respectively. A conductive material is formed in the trench and on the stacked layer. The electrically conductive material has a top portion. One or more holes are formed in the conductive material in each of the trenches. A plurality of predetermined regions for forming a plurality of wires are respectively defined at the top portion of the conductive material. The predetermined area includes a first predetermined area and a second predetermined area, wherein the first predetermined area and the second predetermined area are connected to each other, and the first predetermined area extends in a direction perpendicular to a direction in which one of the stacked layers extends, the second The predetermined area extends along the extending direction of the stacked layers. Next, a portion of the top portion of the conductive material that is not formed in the predetermined region is removed. A wire is formed on a top portion of the conductive material remaining in the predetermined area.

[0005]

According to some embodiments, a memory structure is provided. The memory structure includes a substrate, a plurality of stacked layers, a plurality of memory layers, a conductive material, and a plurality of wires. The stacked layers are on the substrate. The stacked layers are separated from each other by a plurality of trenches. The stacked layers respectively comprise a plurality of electrically conductive strings and a plurality of insulated strings that are alternately stacked. The memory layers conformally cover the stacked layers, respectively. The conductive material is located in the trench and on the stacked layer. The electrically conductive material in the trench forms one or more holes in each of the trenches. The wires are on a conductive material. The wires respectively comprise a first portion and a second portion, the first portion and the second portion being connected to each other, the first portion extending in a direction perpendicular to a direction in which one of the stacked layers extends, and the second portion extending along the extending direction of the stacked layer .

[0006]

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

[0041]

104‧‧‧Stacking layer
114‧‧‧Electrical materials
122‧‧‧Predetermined area
1221‧‧‧First scheduled area
1222‧‧‧second booking area
204‧‧‧Stacked layers
214‧‧‧Electrical materials
222‧‧‧Predetermined area
2221‧‧‧First scheduled area
2222‧‧‧Second Schedule
304‧‧‧Stacked layers
314‧‧‧Electrical materials
318‧‧‧Cutting channel
322‧‧‧Predetermined area
3221‧‧‧First scheduled area
3222‧‧‧Second Schedule
322A‧‧‧Extension
404‧‧‧Stacking layer
414‧‧‧Electrical materials
418‧‧‧ cutting channel
422‧‧‧Predetermined area
4221‧‧‧First scheduled area
4222‧‧‧Second Schedule
422A‧‧‧Extension
422B‧‧‧Extension
500‧‧‧Substrate
502‧‧‧ buried layer
504‧‧‧Stacked layers
506‧‧‧Electrical string
508‧‧‧Insulated string
510‧‧‧Oxide layer
512‧‧‧ memory layer
514‧‧‧Electrical materials
514A‧‧‧Top part
516‧‧‧Insulation
518‧‧‧ cutting channel
520‧‧‧Remove the channel
522‧‧‧Predetermined area
5221‧‧‧First scheduled area
5222‧‧‧Second Schedule
524‧‧‧Wire
5241‧‧‧Part 1
5242‧‧‧Part II
H‧‧‧ Hole
T‧‧‧ trench

【0007】

1A to 1C are views showing the concept of a method of fabricating a memory structure according to an embodiment.
2A-2B illustrate the concept of a method of fabricating a memory structure in accordance with an embodiment.
3A-3C illustrate the concept of a method of fabricating a memory structure in accordance with an embodiment.
4A-4C illustrate the concept of a method of fabricating a memory structure in accordance with an embodiment.
5A-12B illustrate a method of fabricating a memory structure in accordance with an exemplary embodiment.

[0008]

A method of fabricating a memory structure will be provided below. First, a plurality of stacked layers are formed on a substrate. The stacked layers are separated from one another by a plurality of trenches. The stacked layers respectively comprise a plurality of electrically conductive strings and a plurality of insulated strings that are alternately stacked. Next, a plurality of memory layers respectively conformally covering the stacked layers are formed. Next, a conductive material is formed in the trench and on the stacked layer. The electrically conductive material has a top portion that is positioned higher than the stacked layers. One or more holes are formed in the conductive material in each of the trenches. An insulating material can be filled into one or more of the holes. Referring to FIG. 1A, a stacked layer 104, a conductive material 114, and a hole H are shown. In this embodiment, one or more of the holes H in each of the grooves are arranged in a matrix.

【0009】

Next, referring to FIG. 1B, a plurality of predetermined regions 122 for forming a plurality of wires are respectively defined at the top portion of the conductive material 114. The predetermined area 122 includes a first predetermined area 1221 and a second predetermined area 1222, respectively, and the first predetermined area 1221 and the second predetermined area 1222 are connected to each other. The first predetermined region 1221 extends in a direction perpendicular to the extending direction of the stacked layer 104, and the second predetermined region 1222 extends in the extending direction of the stacked layer 104. In this embodiment, the lengths of the first predetermined area 1221 and the second predetermined area 1222 are gradually increased.

[0010]

Thereafter, a portion of the top portion of the conductive material that is not formed in the predetermined region may be removed. Next, a wire is formed on the top portion of the conductive material remaining in the predetermined region. The wire can be formed from a telluride. The conductive string in the stacked layer can be used as a bit line, and the wire can be used as a word line. Alternatively, the conductive traces in the stacked layers can be used as word lines, and the wires can be used as bit lines.

[0011]

Due to the process limitation, the connecting portion formed by the method according to this embodiment may have a curved portion as shown in Fig. 1C. This type does not depart from the scope of the invention as long as the fan-out portion of the wire is functioning properly.

[0012]

The process described in conjunction with Figures 1A through 1C can be replaced by the following processes. Referring to FIG. 2A, a stacked layer 204, a conductive material 214, and a hole H are shown. In this embodiment, the step of defining a predetermined region for forming a wire is performed before the step of forming one or more holes H. In this way, the holes H can be formed only at positions where the wires are separated by a narrow pitch (for example, only about 30 to 40 nm). Thus in this embodiment, one or more of the holes H in each of the grooves are arranged in a triangle.

[0013]

Next, referring to FIG. 2B, a plurality of predetermined regions 222 for forming a plurality of wires are respectively defined at the top portion of the conductive material 214. The predetermined area 222 includes a first predetermined area 2221 and a second predetermined area 2222, respectively, and the first predetermined area 2221 and the second predetermined area 2222 are connected to each other. The first predetermined area 2221 extends in a direction perpendicular to the extending direction of the stacked layer 204, and the second predetermined area 2222 extends in the extending direction of the stacked layer 204. In this embodiment, the lengths of the first predetermined area 2221 and the second predetermined area 2222 are gradually increased.

[0014]

Since the hole is not formed at the position corresponding to the second predetermined area 2222, the strength of the wire manufactured by this embodiment is higher than the strength of the wire manufactured by the embodiment of Figs. 1A to 1C.

[0015]

Alternatively, the above process may be replaced by the following processes. Referring to FIG. 3A, a stacked layer 304, a conductive material 314, and a hole H are shown. In this embodiment, the holes H are formed only at positions where the wires are separated by a narrow pitch and are arranged in a triangle shape.

[0016]

Next, referring to FIG. 3B, a plurality of predetermined regions 322 for forming a plurality of wires are respectively defined at the top portion of the conductive material 314. The predetermined area 322 includes a first predetermined area 3221, a second predetermined area 3222, and an extended portion 322A. The first predetermined area 3221 and the second predetermined area 3222 are connected to each other. The first predetermined region 3221 extends in a direction perpendicular to the extending direction of the stacked layer 304, and the second predetermined region 3222 extends in the extending direction of the stacked layer 304. The first predetermined area 3221 of the adjacent ones of the predetermined areas 322 are connected to each other by the extended portion 322A of the second predetermined area 3222 of one of the adjacent ones of the predetermined areas 322. In this embodiment, the lengths of the first predetermined area 3221 and the second predetermined area 3222 are gradually increased.

[0017]

The step of removing the portion of the top portion of the conductive material 314 that is not formed in the predetermined region 322 includes a cutting step and a removing step. As shown in FIG. 3C, the ablation step includes removing a portion of the top portion of the conductive material 314 and a portion of the memory layer on the stacked layer 304 in a direction perpendicular to the direction in which the stacked layers 304 extend. The cut channel 318 formed by the cutting step is shown. The top portion of conductive material 314 in extension portion 322A is removed by a cutting step. The removing step includes removing portions of the top portion of the conductive material 314 that are not formed in the predetermined region 322.

[0018]

Since an additional ablation step is used to remove the electrically conductive material 314 in the extended portion 322A proximate the connecting portion, the resulting connecting portion can have a shape that is closer to a right angle. Therefore, the wire manufactured by this embodiment has a higher strength than the wire manufactured by the embodiment of Figs. 2A to 2B.

[0019]

Alternatively, the above process may be replaced by the following process. Referring to FIG. 4A, a stacked layer 404, a conductive material 414, and a hole H are shown. In this embodiment, the holes H are formed only at positions where the wires are separated by a narrow pitch and are arranged in a triangle shape.

[0020]

Next, referring to FIG. 4B, a plurality of predetermined regions 422 for forming a plurality of wires are respectively defined at the top portion of the conductive material 414. The predetermined area 422 includes a first predetermined area 4221, a second predetermined area 4222, and a plurality of extended portions 422A, 422B, respectively. The first predetermined area 4221 and the second predetermined area 4222 are connected to each other. The first predetermined region 4221 extends in a direction perpendicular to the extending direction of the stacked layer 404, and the second predetermined region 4222 extends in the extending direction of the stacked layer 404. The first predetermined area 4221 of the adjacent ones of the predetermined areas 422 is the extension part 422A of the second predetermined area 4222 and the other of the predetermined areas 422 by one of the adjacent ones of the predetermined areas 422 The extended portions 422B of the two predetermined areas 4222 are connected to each other. In this embodiment, the lengths of the first predetermined area 4221 and the second predetermined area 4222 are gradually increased.

[0021]

The step of removing the portion of the top portion of the conductive material 414 that is not formed in the predetermined region 422 includes a cutting step and a removing step. As shown in FIG. 4C, the step of removing includes removing a portion of the top portion of the conductive material 414 and a portion of the memory layer on the stacked layer 404 in a direction perpendicular to the direction in which the stacked layers 404 extend. The cut channel 418 formed by the ablation step is shown. In this embodiment, the cutting channel 418 is formed in a region of the triangle substantially corresponding to the hole H. The conductive portion 422A of the second predetermined region 4222 of the one of the adjacent ones in the predetermined region 422 and the conductive material 414 in the extended portion 422B of the second predetermined region 4222 of the other of the predetermined regions 422 The top portion is removed by a cutting step. The removing step includes removing portions of the top portion of the conductive material 414 that are not formed in the predetermined region 422.

[0022]

Since the predetermined region 422 is a more symmetrical design, the step of removing the top portion of the conductive material 414 is simpler than the step of removing the top portion of the conductive material 314. Therefore, according to this embodiment, the process window can be further expanded.

[0023]

Other processes can also be used in place of the processes described in Figures 1A~1C, 2A~2B, 3A~3C or 4A~4C. For example, in one embodiment, the holes may be arranged as shown in the embodiment of Figures 1A-1C, and the predetermined area may be defined as shown in the embodiment of Figures 3A-3C. In another embodiment, the holes may be arranged as shown in the embodiment of Figures 1A-1C, and the predetermined area may be defined as shown in the embodiment of Figures 4A-4C.

[0024]

In order to further understand the manufacturing method of the memory structure, an exemplary embodiment will be given below in conjunction with FIGS. 5A to 12C. The maps indicated by "B" and "C" are the cross-sectional views taken from the lines 1-1' and 2-2' in the figure indicated by "A". This exemplary embodiment relates to the fabrication of a memory structure as shown in Figures 4A-4C.

[0025]

Referring to FIGS. 5A-5C, a plurality of stacked layers 504 are formed on a substrate 500. In one embodiment, a buried layer 502 is formed over the substrate 500, and a stacked layer 504 is formed over the buried layer 502. The buried layer 502 may be formed of an oxide. The stacked layers 504 are separated from each other by a plurality of trenches T. The stacked layers 504 include a plurality of electrically conductive strings 506 and a plurality of insulated strings 508 that are alternately stacked. The conductive string 506 can be formed of polysilicon and the insulated string 508 can be formed of an oxide. The stacked layers 504 may further include an oxide layer 510 on the conductive traces 506 and the insulated traces 508, respectively.

[0026]

Referring to FIGS. 6A-6C, a plurality of memory layers 512 respectively conforming to the stacked layer 504 are formed. The memory layer 512 can be an oxide-nitride-oxide (ONO) structure or the like.

[0027]

Referring to FIGS. 7A-7C, a conductive material 514 is formed in the trench T and on the stacked layer 504. Conductive material 514 has a top portion 514A. Here, the top portion 514A is defined as a portion of the conductive material 514 that is positioned higher than the memory layer 512 on the stacked layer 504 and the stacked layer 504. Conductive material 514 can be polycrystalline germanium.

[0028]

Referring to FIGS. 8A-8C, one or more holes H are formed in the conductive material 514 in each of the trenches T. The step of defining a predetermined region 522 (shown in Figure 11A) for forming wire 524 (shown in Figure 12A) can be performed before, after, or at any suitable point in time to form one or more holes H. Alternatively, several definition steps can be performed. For example, the definition step can be performed at this time. As such, the holes H may be formed only at positions where the wires 524 are separated by a narrow pitch. The hole H can be formed by a lithography and etching process. In the step of forming the holes H, the memory layer 512 on the sidewalls of the stacked layers 504 in the holes H may be removed.

[0029]

Referring to FIGS. 9A-9C, an insulating material 516 may be filled into one or more holes H in each of the trenches T. Insulating material 516 can cover top portion 514A of conductive material 514 as shown in Figures 9B and 9C. Insulation material 516 can be an oxide.

[0030]

Next, the portion of the top portion 514A of the conductive material 514 for forming the wire 524 (shown in FIG. 12A) that is not formed in the predetermined region 522 (shown in FIG. 11A) is removed. The step of removing the portion of the top portion 514A of the conductive material 514 that is not formed in the predetermined region 522 includes a cutting step and a removing step.

[0031]

Referring to FIGS. 10A-10C, the cutting step includes removing a portion of the top portion 514A of the conductive material 514 and a portion of the memory layer 512 of the stacked layer 504 in a direction perpendicular to the direction in which the stacked layers 504 extend. A cut channel 518 is shown. In the case where the insulating material 516 covers the top portion 514A of the conductive material 514, the insulating material 516 in the dicing trench 518 is also removed. The cutting step can be performed by a lithography and etching process. In this embodiment, the cutting channel 518 is formed along the hole H in a region of the triangle substantially corresponding to the hole H.

[0032]

Please refer to pages 11A to 11C for the definition steps. A predetermined region 522 is defined in the top portion 514A of the conductive material 514 for forming a wire. The predetermined area 522 includes a first predetermined area 5221 and a second predetermined area 5222. The first predetermined area 5221 and the second predetermined area 5222 are connected. The first predetermined area 5221 is along a direction perpendicular to the extending direction of the stacked layer 504. The second predetermined region 5222 extends along the extending direction of the stacked layer 504. The removal step is performed as shown in Figs. 11A to 11C. The removing step includes removing portions of the top portion 514A of the conductive material 514 that are not formed in the predetermined region 522. The removal of the channel 520 is shown. Similar to the ablation step, the removal step can be performed by a lithography and etching process.

[0033]

Referring to Figures 12A-12B, a wire 524 is formed on the top portion 514A of the conductive material 514 remaining in the predetermined region 522. Wire 524 can be formed from a telluride. In one embodiment, wire 524 is formed by depositing a layer of tungsten (WSi) on top portion 514A of conductive material 514 remaining in predetermined region 522. In another embodiment, the wire 524 is formed by depositing a metal, such as cobalt (Co), nickel (Ni), or titanium (Ti), etc. on the top portion 514A of the conductive material 514 remaining in the predetermined region 522. This metal is reacted with a conductive material 514 (polysilicon) to form a telluride such as cobalt telluride (CoSi), nickel telluride (NiSi) or titanium telluride (TiSi) or the like. As shown in FIG. 12A, the wires 524 respectively include a first portion 5241 and a second portion 5242. The first portion 5241 and the second portion 5242 are connected to each other, and the first portion 5241 extends in a direction perpendicular to the extending direction of the stacked layer 504. The second portion 5242 extends along the direction in which the stacked layers 504 extend. The length of the first portion 5241 and the second portion 5242 of the wire 524 is gradually increased.

[0034]

The above methods are compatible with the general process of fabricating semiconductor structures, such as memory structures. For example, the concept of a process including a hole-line two-stage patterning of conductive material formed over a stacked layer is employed. Therefore, the structure can be formed in a more regular manner.

[0035]

In the example of a three-dimensional vertical gate NAND memory, conductive traces 506 in stacked layers 504 can be used as bit lines, and wires 524 can be used as word lines. In the example of a three-dimensional vertical channel NAND memory, conductive traces 506 in stacked layers 504 can be used as word lines, and wires 524 can be used as bit lines.

[0036]

The memory structure fabricated by the above method includes a substrate 500, a plurality of stacked layers 504 (or 104/204/304/404), a plurality of memory layers 512, a conductive material 514 (or 114/214/314/414), and A plurality of wires 524. Stacked layers 504 (or 104/204/304/404) are located on substrate 500. The stacked layers 504 (or 104/204/304/404) are separated from each other by a plurality of trenches T. The stacked layers 504 (or 104/204/304/404) respectively include a plurality of electrically conductive strings 506 and a plurality of insulated strings 508 that are alternately stacked. The memory layers 512 conformally cover the stacked layers 504 (or 104/204/304/404), respectively. Conductive material 514 (or 114/214/314/414) is located in trench T and on stacked layer 504 (or 104/204/304/404). Conductive material 514 (or 114/214/314/414) in trench T forms one or more holes H in each of trenches T. In one embodiment, one or more of the holes H in each of the trenches T are arranged in a matrix as shown in FIG. 1A. In another embodiment, one or more of the holes H in each of the trenches T are arranged in a triangular shape as shown in Figures 2A, 3A and 4A.

[0037]

The wires 524 are located on the conductive material 514 (or 114/214/314/414). The wires 524 respectively include a first portion 5241 and a second portion 5242. The first portion 5241 and the second portion 5242 are connected to each other, and the first portion 5241 is perpendicular to The direction in which the stacked layers 504 (or 104/204/304/404) extend is extended, and the second portion 5242 extends in the direction in which the stacked layers 504 (or 104/204/304/404) extend. The length of the first portion 5241 and the second portion 5242 of the wire 524 is gradually increased. Wire 524 can be formed from a telluride. In one embodiment, conductive traces 506 in stacked layers 504 (or 104/204/304/404) are used as bit lines, and wires 524 are used as word lines. In another embodiment, conductive traces 506 in stacked layers 504 (or 104/204/304/404) are used as word lines and wires 524 are used as bit lines.

[0038]

For the sake of brevity, other detailed structural features that have been described in connection with the manufacturing method are omitted here.

[0039]

According to an embodiment, the fan-out portion of the wire (i.e., the first portion and the second portion of the wire are formed on the dummy stacked layer (i.e., the stacked layer in an extended region of the array region). Formed in a relatively regular area, the failure rate can be reduced.

[0040]

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

104‧‧‧Stacking layer

122‧‧‧Predetermined area

1221‧‧‧First scheduled area

1222‧‧‧second booking area

H‧‧‧ Hole

Claims (10)

[Item 1] A method of fabricating a memory structure, comprising:
Forming a plurality of stacked layers on a substrate, wherein the stacked layers are separated from each other by a plurality of trenches, and the stacked layers respectively comprise a plurality of electrically conductive strings and a plurality of insulated strings alternately stacked;
Forming a plurality of memory layers conformally covering the stacked layers respectively;
Forming a conductive material in the trenches and the stacked layers, the conductive material having a top portion;
Forming one or more holes in the conductive material in each of the trenches; and defining, in the top portion of the conductive material, a plurality of predetermined regions for forming a plurality of wires, wherein the predetermined regions respectively include a first a predetermined area and a second predetermined area, wherein the first predetermined area and the second predetermined area are connected to each other, the first predetermined area extending in a direction perpendicular to a direction in which one of the stacked layers extends, the second predetermined The regions extend along the extending direction of the stacked layers. [Item 2] The method of fabricating a memory structure according to claim 1, wherein the one or more holes in each of the trenches are arranged in a matrix or a triangle. [Item 3] The method of fabricating a memory structure according to claim 1, wherein the step of defining the predetermined regions is performed before or after the step of forming the one or more holes. [Item 4] The method for manufacturing a memory structure according to claim 1, wherein the lengths of the first predetermined regions and the second predetermined regions are gradually increased. [Item 5] The method for manufacturing a memory structure according to claim 1, further comprising:
Removing a portion of the top portion of the conductive material that is not formed in the predetermined regions; and forming the wires on the top portion of the conductive material remaining in the predetermined regions. [Item 6] The method for manufacturing a memory structure as described in claim 5, further comprising:
An insulating material is filled into the one or more holes in each of the trenches before the step of removing portions of the top portion of the conductive material that are not formed in the predetermined regions. [Item 7] The method of manufacturing a memory structure according to claim 6, wherein the step of removing the portion of the top portion of the conductive material that is not formed in the predetermined regions comprises a cutting step and a removing step, The removing step includes removing a portion of the top portion of the conductive material and a portion of the memory layers on the stacked layers in a direction perpendicular to the extending direction of the stacked layers, the removing step including moving Other portions of the top portion of the conductive material that are not formed in the predetermined regions. [Item 8] The method of fabricating a memory structure according to claim 5, wherein the first predetermined regions of adjacent ones of the predetermined regions are by one of the adjacent ones of the predetermined regions An extension of the second predetermined area of the person is connected to each other, and the top portion of the conductive material in the extended portion is removed by a cutting step. [Item 9] The method of fabricating a memory structure according to claim 5, wherein the first predetermined regions of adjacent ones of the predetermined regions are by one of the adjacent ones of the predetermined regions An extension of the second predetermined area and an extension of the second predetermined area of the other of the predetermined areas are connected to each other, and the second predetermined one of the adjacent ones The top portion of the electrically conductive material in the extended portion of the region and the extended portion of the second predetermined region of the other is removed by a cutting step. [Item 10] A memory structure that includes:
a substrate;
a plurality of stacked layers on the substrate, wherein the stacked layers are separated from each other by a plurality of trenches, and the stacked layers respectively comprise a plurality of electrically conductive strings and a plurality of insulated strings alternately stacked;
a plurality of memory layers respectively conforming to the stacked layers;
a conductive material disposed in the trenches and the stacked layers, wherein the conductive material in the trenches forms one or more holes in each of the trenches; and a plurality of wires are located at the conductive In the material, the wires respectively comprise a first portion and a second portion, the first portion and the second portion being connected to each other, the first portion extending in a direction perpendicular to a direction in which one of the stacked layers extends, the The second portion extends along the extending direction of the stacked layers.