TWI576585B - Low-power power detector - Google Patents

Description

Low power power detector

The present invention relates to a power detector, and more particularly to a low power power detector.

A power detector is used to detect the resonant frequency of a sensing signal output by a biomedical sensor, and the biomedical sensor can be classified into a belt type or a belt rejection sensor according to the type difference. For example, the characteristic of the spectrum analysis of the Film Bulk Acoustic Resonator (FBAR) is the rejection type, and the frequency of the frequency signal received by the biomedical sensor with the rejection type is closer to the resonance frequency. At the point, the amplitude of the detection signal output by the biomedical sensor is lower. Conversely, the characteristic of the spectrum analysis such as the Flexural Plate Wave (FPW) is the bandpass type. The closer the frequency of the frequency signal received by the biomedical sensor is to the resonance frequency point, the higher the amplitude of the detection signal output by the biomedical sensor, and the power detector can detect The resonance frequency point of the sensing signal of the biomedical sensor is measured to perform frequency drift analysis. The sensing signal output by the biomedical sensor is not a continuous change, but the amplitude of the oscillation is changed every once in a while. Therefore, if the power detector continues to detect, it will be a period of time. The same size signal is output in the middle, resulting in wasted power.

The main purpose of the present invention is to reduce the unnecessary power by continuously turning on and off the voltage detector so that the voltage detector does not continuously detect the signal in the same frequency range of the frequency signal. Consumption. The non-overlapping clock generator and the output stage are arranged to prevent the voltage detector from generating a judgment error on the signal, and the amplitude maximum or minimum value of the frequency sensing signal output by the biomedical sensor can be correctly measured. .

A low power consumption power detector of the present invention comprises an amplitude voltage converter, a non-overlapping clock generator, a voltage detector and an output stage, the amplitude voltage converter receiving a frequency sensing signal and And outputting a voltage signal, wherein the potential of the voltage signal is inversely proportional to the amplitude of the frequency sensing signal, and the non-overlapping clock generator outputs a first clock signal and a second clock signal, wherein the first clock The high-potential sections of the signal and the second clock signal do not overlap each other, and the voltage detector receives the voltage signal and the first clock signal, and the first clock signal is used to turn the voltage detection on or off. The voltage detector is configured to detect a peak value or a bottom value of the voltage signal to output a voltage detection signal, the output stage receives the second clock signal and the voltage detection signal, and the output stage outputs a detection The test signal, the second clock signal and the voltage detection signal determine the potential of the detection signal.

The low power consumption power detector can accurately detect the amplitude minimum value or the maximum value of the frequency sensing signal outputted by the biomedical sensor, thereby knowing the resonance frequency point of the frequency signal, and Different frequency signals are detected to facilitate subsequent frequency offset analysis. And because the low power consumption power detector can be periodically turned off and on by the non-overlapping clock generator, the low power consumption power detector can be prevented from continuously consuming unnecessary power to achieve low The power consumption effect.

Please refer to FIG. 1 , which is a functional block diagram of a biomedical sensing device B according to a first embodiment of the present invention. The biomedical sensing device B includes a low power consumption power detector 100 and a biomedical sensor. 200 and a register 300, the biomedical sensor 200 receives a frequency signal freq_sweep, and the biomedical sensor 200 outputs a frequency sensing signal V _{rf — P} , in the embodiment, the biomedical sensor 200 is a refusal sensor, such as a Film Bulk Acoustic Resonator (FBAR), that is, when the biosensor sensor 200 receives the frequency signal freq_sweep closer to the resonance frequency point, the health The amplitude of the frequency sensing signal V _{rf — P} output by the medical sensor 200 is smaller. The low power consumption of the power detector 100 receives the frequency sense signal _{V rf_P,} detecting the amplitude of the frequency sense signal _V rf_P minimum value to output a detection signal Det_P, the register 300 receives the detection signal Det_P and the frequency signal freq_sweep are used to obtain the resonance frequency of the frequency signal freq_sweep by triggering the detection signal Det_P, and the subsequent frequency drift analysis can be performed.

Referring to FIG. 2, the low power consumption power detector 100 has an amplitude voltage converter 110, a bandgap circuit 120, a non-overlapping clock generator 130, and a voltage detection. 140 and an output stage 150, see FIG. 2, the amplitude of the voltage converter 110 receives the frequency sense signal _V rf_P and outputs a voltage signal V _N, wherein the potential of the voltage signal V _N of the frequency sense signal The amplitude of V _{rf_P} is inversely proportional. The bandgap bias circuit 120 provides a bias voltage V _{ref — P} to the amplitude voltage converter 110. The non-overlapping clock generator 130 outputs a first clock signal SW1 and a second time. Pulse signal SW2. The voltage detector 140 receives the voltage signal V _N and the first clock signal SW1. The first clock signal SW1 is used to turn on or off the voltage detector 140. The voltage detector 140 is configured to detect The peak of the voltage signal V _N is outputted with a voltage detection signal V _{opa — P} , the output stage 150 receives the second clock signal SW2 and the voltage detection signal V _{opa — P} , and the output stage 150 outputs the detection signal Det_P.

Referring to FIGS. 2 and 3, the amplitude-voltage converter 110 has an isolation capacitor 111, an isolation resistor 112, a first transistor 113, and a filter circuit 114. One end of the isolation capacitor 111 receives the frequency sensing signal V. _{rf_P} , the other end of the isolation capacitor 111 is connected to the gate terminal of the first transistor 113, and the isolation capacitor 111 is configured to filter the DC component of the frequency sensing signal _{Vrf_P} , and the gate terminal of the first transistor 113 passes through the gate electrode The isolation capacitor 111 receives the frequency sensing signal V _{rf — P} and receives the bias voltage V _{ref — P} through the isolation resistor 112 . The isolation resistor 112 serves as a driving resistor of the first transistor 113 , and the first output of the first transistor 113 . The voltage signal V _N , the source of the first transistor 113 is grounded, and the filter circuit 114 is connected to the 汲 terminal of the first transistor 113. In this embodiment, the first transistor 113 is N-type MOSFET. transistor, when the amplitude of the frequency sense signal _V rf_P the more hours, then the level of the voltage signal V _N is higher. Therefore, when the biomedical sensor 200 detects the resonant frequency, the amplitude of the frequency sensing signal V _{rf — P} is the smallest, and the voltage signal V _{N has} the highest level, and the voltage detector 140 is detected by the back end. By measuring the peak value of the voltage signal V _N , the resonance frequency time point of the frequency signal freq_sweep can be detected. In addition, the voltage signal V _P outputted by the second transistor 115 and the filter circuit 116 of the amplitude voltage converter 110 is used to calculate the power level of the frequency sensing signal V _{rf — P} .

Referring to FIG. 3 again, the filter circuit 114 has a load transistor 114a and a filter capacitor 114b. The source terminal of the load transistor 114a receives a power source V _cc , and the gate of the load transistor 114 a is grounded. The 汲 terminal of the crystal 114a is connected to the 汲 terminal of the first transistor 113. One end of the filter capacitor 114b is connected to the 汲 terminal of the first transistor 113, and the other end of the filter capacitor 114b is grounded. Replacing the resistance with the load transistor 114a as the impedance of the filter circuit 114 can facilitate the implementation of the circuit in the semiconductor integrated circuit and reduce the layout area of the circuit. Please refer to FIG. 2 and FIG. 3 again. Preferably, the low power consumption power detector 100 has a reset transistor R, and the reset transistor R receives a reset signal rst, and the reset transistor R The voltage signal V _{N is used} to reduce the voltage signal V _N to avoid the initial voltage value of the node and affect the detection of the back end circuit.

Referring to FIGS. 3 and 4, the bandgap bias circuit 120 has a start circuit 121, an output circuit 122, and a compensation circuit 123 for providing a bias voltage to the bandgap bias circuit. The transistors of 120 are biased to a saturation region, the output circuit 122 forms a current proportional to the absolute temperature, and the compensation circuit 123 forms a current that is inversely proportional to the absolute temperature and forms a current with the output circuit 122. The band gap biasing circuit 120 can output the bias voltage V _{ref — P} that is not affected by the temperature drift to the first transistor 113 and the second transistor 115 of the amplitude voltage converter 110 .

Please refer to FIG. 5 , which is a circuit diagram of the non-overlapping clock generator 130. The overlapping clock generator 130 receives a clock signal SW and performs operations through a plurality of logic circuits, and outputs the first overlap. The clock signal SW1 and the second clock signal SW2 are respectively supplied to the voltage detector 140 and the output stage 150 to prevent the voltage detector 140 from generating a signal misjudgment due to circuit delay, wherein the first The high-potential sections of the clock signal SW1 and the second clock signal SW2 do not overlap each other, that is, when the first clock signal SW1 is high, the second clock signal SW2 is low, and When the second clock signal SW2 is at a high potential, the first clock signal SW1 is at a low potential, and the frequency of the first clock signal SW1 is designed to be in a frequency sensing signal V _{rf_P} of the same amplitude. At least one cycle of switching is completed to avoid detection errors of the voltage detector 140.

See FIGS. 1, 2 and 6, because of the biomedical sensor 200 is a band rejection type sensor, such that the amplitude of the voltage level converter 110 outputs the minimum level to the maximum amplitude of the frequency of the sense signal _V rf_P of the voltage signal V _N, and therefore in the present embodiment, the voltage detector 140 is a voltage peak detecting circuit 160, to the measured peak voltage signal V _N, please refer to FIG. 6, the peak voltage detect The measuring circuit 160 has an operational amplifier 161, a switching transistor 162, a charging transistor 163 and a charging capacitor 164. The operational amplifier 161 has a power terminal 161a, a first input terminal 161b, a second input terminal 161c, and an output terminal 161d. The power terminal 161a receives the first clock signal SW1, and the first input terminal 161b receives The voltage signal V _N , the second input terminal 161c is connected to the charging capacitor 164, and the output terminal 161d outputs the voltage detecting signal V _{opa — P} . Referring to FIG. 7 , in the embodiment, the operational amplifier 161 is a track. A current-to-rail amplifier 161e, the power-switching transistor 161e receives the first clock signal SW1, and the first clock signal SW1 determines the power-switching power The turn-on or turn-off of the crystal 161e further controls the operational amplifier 161 to be turned on or off.

Referring to FIG. 6 , the switch transistor 162 of the voltage peak detector 160 receives the first clock signal SW1 and the power source V _cc , and the first clock signal SW1 is used to turn the switch transistor on or off. The charging transistor 163 receives the voltage detecting signal V _{opa — P} , and the voltage detecting signal V _{opa — P is} used to determine whether the charging transistor 163 is turned on or off. When the switching transistor 162 and the charging transistor 163 are both turned on. The power source V _cc charges the charging capacitor 164 via the switching transistor 162 and the charging transistor pair 163.

Referring to FIG. 6, in the embodiment, the voltage peak detector 160 further includes a discharge transistor 165 and a compensation transistor 166. The discharge transistor 165 is connected to the charging capacitor 164, and the discharge transistor 165 is connected. Receiving the reset signal rst to determine whether the discharge transistor 165 is turned on or off. When the discharge transistor 165 is turned on, the potential V _{o21 of} the charging capacitor 164 is discharged to a low potential via the discharge transistor 165 to avoid the charging. Capacitor 164 has accumulated power during initial operation, causing a peak detection error. The compensation transistor 166 is connected to the charging transistor 163 and the charging capacitor 164. The gate of the compensation transistor 166 receives the inverted voltage detection signal V _{opa — P} through an inverter 167 to determine the compensation transistor 166. Turning on or off, the 汲 terminal and the source terminal of the compensation transistor 166 are short-circuited to each other, and the compensation transistor 166 is used to compensate for the charge injection of the charging transistor 163, since the charging transistor 163 is turned off. The compensation transistor 166 is turned on, and can receive the channel charge generated when the charging transistor 163 is turned off. When the charging transistor 163 is turned off, only half of the channel charge is injected toward the compensation transistor 166. Preferably, the compensation transistor 166 has an aspect ratio which is half of the aspect ratio of the charging transistor 163.

Referring to FIGS. 2 and 8, the output stage 150 has an inverter 151 and a gate 152. The gate 152 receives the inverted voltage detection signal V _{opa — P} via the inverter 151, and the gate is 152. The second clock signal SW2 is received. The gate 152 outputs the detection signal Det_P. The second clock signal SW2 and the voltage detection signal V _{opa_P} determine the potential of the detection signal Det_P. In this embodiment, When the second clock signal SW2 is high and the voltage detection signal V _{opa_P} is low, the potential of the detection signal Det_P rises to a high level, which also means that the voltage detector 140 has a detect The peak value is measured. Referring to FIG. 9, the inverter 151 is a high-shear inverter. The inverter 151 has a P-type transistor 151a and an N-type transistor. 151b, wherein the aspect ratio of the P-type transistor 151 is greater than the aspect ratio of the N-type transistor 151b, so that the inverted voltage detection signal V _{opa_p} rises to a high potential faster to prevent the output signal from being unstable. Or noise interference causes error signal output.

Referring to FIGS. 1-9, the circuit of the first embodiment is activated by the amplitude voltage converter 110 receiving the frequency sensing signal _{Vrf_P} by the biomedical sensor 200, and the frequency sensing signal _{Vrf_P} The smaller the amplitude (the closer the frequency signal freq_sweep received by the biomedical sensor 200 is to the resonance frequency), the higher the voltage signal V _N level output by the amplitude voltage converter 110 is, the higher the voltage detector 140 receives The voltage signal V _N is detected by a peak, and the operational amplifier 161 and the switching transistor 162 of the voltage peak detector 160 are controlled by the first clock signal SW1 when the first clock signal SW1 is When the potential is low, the operational amplifier 161 and the switching transistor 162 are turned on, and the operational amplifier 161 receives the voltage signal V _N and compares with the potential V _{o21 of} the charging capacitor 164. When the voltage signal V _N continues to rise, the The voltage signal V _{N is} greater than the potential V _{o21 of} the charging capacitor 164. Therefore, the voltage detecting signal V _{opa — P} outputted by the operational amplifier 161 is low, and the charging transistor 163 is turned on, and since the switching transistor 162 is also turned on at this time. ,therefore, A charging power supply V _CC via the switching transistor 162 and the transistor 163 charging capacitor 164 to the charging capacitor 164 so that the charging potential V voltage signal V _{N o21} value of the recovery until the voltage stops rising when the signal V _N, The potential V _{o21 of} the charging capacitor 164 is not less than the voltage signal V _N , and the voltage detecting signal V _{opa —P} outputted by the operational amplifier 161 rises to a high potential to turn off the charging transistor 163. At this time, the potential V of the charging capacitor 164 _{O21 is} the peak value of the voltage signal V _N , and the channel charge generated by the charging transistor 163 is received by the compensation transistor 166 without affecting the potential V _{o21 of} the charging capacitor 164 , so that the voltage detector The peak of the 140 can be accurately detected. The output stage 150 receives the voltage detection signal V _{opa_P} and the second clock signal SW2 when the voltage detection signal V _{opa_P} is low and the second clock signal SW2 is high. when the potential of the detection signal output 150 of Det_P will rise to a high potential of the output stage, and the last signal of the high potential of the detection signal Det_P time point may correspond to the minimum oscillation frequency of the sensing signal _V rf_P Corresponding to the resonance frequency point of the frequency signal freq_sweep, the buffer 300 receives the detection signal Det_P and the frequency signal freq_sweep, and the frequency signal is captured by the trigger of the detection signal Det_P. Freq_sweep's resonant frequency for frequency offset analysis.

Please refer to FIGS. 10 and 11 , which are second embodiments of the present invention, which differ from the first embodiment in that the biomedical sensor 200 is a belt-type sensor, such as a curved flat wave sensor ( Flexural Plate Wave (FPW), that is, the closer the frequency signal freq_sweep received by the biomedical sensor 200 is to the resonance frequency, the greater the amplitude of the frequency sensing signal V _{rf —} V output by the biomedical sensor 200. The low-power power detector 100 receives the frequency sensing signal V _{rf —} V and detects the maximum amplitude of the frequency sensing signal V _{rf —} V to output the detecting signal Det_V, and further knows the resonance of the frequency signal freq_sweep. frequency. Referring to FIG. 11 , since the potential of the voltage signal V _N output by the amplitude voltage converter 110 of the low power consumption power detector 100 is inversely proportional to the amplitude of the frequency sensing signal V _{rf —} V, The maximum amplitude of the frequency sensing signal V _{rf_V} is obtained, that is, the minimum value of the voltage signal V _N outputted by the amplitude voltage converter 110 is required. Please refer to FIGS. 12 and 13 for the first embodiment. Another difference is that the voltage detector 140 is a voltage valley detecting circuit 170, and the output stage 150 has a first inverter 153, an inverse gate 154 and a second inverter 155. In addition, the circuit structure and the operation of the amplitude voltage converter 110, the bandgap bias circuit 120, and the non-overlapping clock generator 130 of the low power consumption power detector 100 of the embodiment are the same as the first The embodiments are the same and therefore will not be described again.

Referring to FIG. 12 , the voltage valley detecting circuit 170 has an operational amplifier 171 , a switching transistor 172 , a discharge transistor 173 , a discharge capacitor 174 , an inverter 175 , and a charging transistor 176 . The operational amplifier 171 has a power terminal 171a, a first input terminal 171b, a second input terminal 171c, and an output terminal 171d. The power terminal 171a receives the first clock signal SW1, and the first input terminal 171b receives the voltage. signal V _N, the second input terminal 171c connected to the capacitor 174 discharges, the output terminal 171d outputs the voltage detection signal _V opa_V, in the present embodiment, the operational amplifier 171 is the same as the first embodiment of the rail The rail amplifier is controlled to be turned on or off by the first clock signal SW1.

Referring to FIG. 12 again, the switch transistor 172 receives the inverted first clock signal SW1 via the inverter 175, and the inverted first clock signal SW1 is used to turn the switch transistor 172 on or off. The discharge transistor 173 receives the voltage detection signal V _{opa —} V , and the voltage detection signal V _{opa —} V is used to turn on or off the discharge transistor 173 , and one end of the discharge capacitor 174 is connected to the power source V _cc when the switch transistor is When the 172 and the discharge transistor 173 are both turned on, the discharge capacitor 174 is discharged through the discharge transistor 173 and the switch transistor 172. The charging transistor 176 is connected to the discharging capacitor 174, and the charging transistor 176 receives the reset signal rst, and the reset signal rst is used to determine whether the charging transistor 176 is turned on or off. When the charging transistor 176 is turned on, The discharge capacitor 174 is charged to a high potential via the charging transistor 176 to prevent the discharge capacitor 174 from being charged at the initial operation, thereby causing a detection error of the valley value.

Referring to FIG. 12, the voltage valley detecting circuit 170 further has a compensation transistor 177. The compensation transistor 177 is connected to the discharge transistor 173 and the discharge capacitor 174. The gate of the compensation transistor 177 The voltage detection signal V _{opa —} V is inverted by an inverter 178 to determine whether the compensation transistor 177 is turned on or off, and the terminal and source terminals of the compensation transistor 177 are short-circuited to each other. The compensation transistor 177 is used to compensate for the charge injection of the discharge transistor 173. When the discharge transistor 173 is turned off, the compensation transistor 177 is turned on, and the discharge transistor 173 can be received when the discharge transistor 173 is turned off. The generated channel charge, when the discharge transistor 173 is turned off, only half of the channel charge is injected toward the compensation transistor 177. Therefore, preferably, the aspect ratio of the compensation transistor 177 is the discharge transistor 173. Half of the aspect ratio.

Referring to FIG. 13 , the first inverter 153 of the output stage 150 receives the voltage detection signal V _{opa —} V , and the second inverter 155 receives the second clock signal SW2 , and the reverse gate 154 passes the The first inverter 153 and the second inverter 155 receive the inverted voltage detection signal V _{opa —} V and the inverted second clock signal SW2 , and the inverse gate 154 outputs the detection signal Det_V. When the voltage detection signal V _{opa_V} and the second clock signal SW2 are both high, the detection signal Det_V outputted by the gate 152 rises to a high level, which also means that the voltage detector 140 has A valley value was detected.

Referring to FIG. 14, the first inverter 153 is a low skew inverter having a P-type transistor 153a and an N-type transistor 153b. The aspect ratio of the N-type transistor 153b is greater than the aspect ratio of the P-type transistor 153a, so that the reversed voltage detection signal V _{opa_V} falls to a low potential faster to prevent the output signal from being unstable or It is noise interference and causes error signal output.

Referring to the figures 11, 12 and 13, in the embodiment, the circuit of the voltage detector 140 and the output stage 150 is activated: the voltage detector 140 receives the voltage signal V _N and performs valley detection. The operational amplifier 171 and the switching transistor 172 of the voltage valley detector 170 are controlled by the first clock signal SW1. When the first clock signal SW1 is low, the operational amplifier 171 and The switching transistor 172 is turned on, and the operational amplifier 171 receives the voltage signal V _N and compares it with the potential V _{o24 of} the discharging capacitor 174 . When the voltage signal V _N continues to decrease, the voltage signal V _{N is} smaller than the discharging capacitor 174 . The potential V _o24 , so that the voltage detection signal V _{opa —} V outputted by the operational amplifier 171 is high, and the discharge transistor 173 is turned on, and since the switch transistor 172 is also turned on at this time, the discharge capacitor 174 passes through the The switching transistor 172 and the discharge transistor 173 are discharged to the ground, so that the potential V _{o24 of} the discharge capacitor 174 is _valued by the voltage signal V _N until the voltage signal V _N stops falling, and the potential V _{o24 of} the discharge capacitor 174 Not greater than the voltage No. V _N , the voltage detection signal V _{opa —} V _outputted by the operational amplifier 171 falls to a low potential to turn off the discharge transistor 173. At this time, the potential V _{o24 of} the discharge capacitor 174 is the valley value of the voltage signal V _N . and the discharge transistor 173 to close the channel charges generated by the compensation transistor 177 received, without affecting the potential V _o24 discharge capacitor 174, so that the valley voltage detector 140 can be accurately detected, please Referring to FIG. 13 , the output stage 150 receives the voltage detection signal V _{opa —} V and the second clock signal SW2 , and when the voltage detection signal V _{opa —} V and the second clock signal SW2 are high, the output is The detection signal Det_V outputted by the stage 150 will rise to a high level, and the time point of the last high-potential signal of the detection signal Det_V may correspond to the maximum amplitude of the frequency sensing signal V _{rf_V} , or may correspond to The resonant frequency of the frequency signal freq_sweep, the buffer 300 receives the detection signal Det_V and the frequency signal freq_sweep, and the resonance frequency of the frequency signal freq_sweep is captured by the trigger of the detection signal Det_V, Perform an analysis of the frequency offset.

The power consumption detector 100 of the present invention can accurately detect the amplitude minimum or maximum value of the frequency sensing signal output by the biomedical sensor 200, thereby obtaining the resonance frequency point of the frequency signal. Different frequency signals can be detected to facilitate subsequent frequency offset analysis. Moreover, since the low power consumption power detector 100 can be periodically turned off and on by the non-overlapping clock generator 130, the low power consumption of the power detector 100 can be prevented from being continuously detected and consumed. The power to achieve low power consumption.

The scope of the present invention is defined by the scope of the appended claims, and any changes and modifications made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the present invention. .

100‧‧‧Low power power detector
110‧‧‧Amplitude voltage converter
111‧‧‧Isolation capacitor
112‧‧‧Isolation resistance
113‧‧‧First transistor
114‧‧‧Filter circuit
114a‧‧‧Loading transistor
114b‧‧‧Filter Capacitor
115‧‧‧Second transistor
116‧‧‧Filter circuit
120‧‧‧Band-gap bias circuit
121‧‧‧ starting circuit
122‧‧‧Output circuit
123‧‧‧Compensation circuit
130‧‧‧ Non-overlapping clock generator
140‧‧‧Voltage Detector
150‧‧‧Output
151‧‧‧Inverter
151a‧‧‧P type transistor
151b‧‧‧N type transistor
152‧‧‧ and gate
153‧‧‧First Inverter
153a‧‧‧P type transistor
153b‧‧‧N type transistor
154‧‧‧Anti-gate
155‧‧‧Second inverter
160‧‧‧Voltage peak detection circuit
161‧‧‧Operational Amplifier
161a‧‧‧Power terminal
161b‧‧‧ first input
161c‧‧‧second input
161d‧‧‧output
161e‧‧‧Power Switch Transistor
162‧‧‧Switching transistor
163‧‧‧Charging transistor
164‧‧‧Charging capacitor
165‧‧‧discharge transistor
166‧‧‧Compensated transistor
167‧‧‧Inverter
170‧‧‧Voltage Valley Detection Circuit
171‧‧‧Operational Amplifier
171a‧‧‧Power terminal
171b‧‧‧ first input
171c‧‧‧ second input
171d‧‧‧output
172‧‧‧Switching transistor
173‧‧‧discharge transistor
174‧‧‧discharge capacitor
175‧‧‧Inverter
176‧‧‧Charging transistor
177‧‧‧Compensated transistor
178‧‧‧Inverter
200‧‧‧ biomedical sensor
300‧‧‧ register
B‧‧‧ biomedical sensing device
R‧‧‧Reset transistor
V _{rf_P} ‧‧‧ frequency sensing signal
V _{opa_P ‧‧‧voltage} detection signal
V _{rf_V} ‧‧‧ frequency sensing signal
V _{opa_V ‧‧‧voltage} detection signal
V _N ‧‧‧Voltage signal
Rst‧‧‧Reset signal
Det_P‧‧‧Detection signal
Det_V‧‧‧Detection signal
SW‧‧‧ clock signal
SW1‧‧‧ first clock signal
SW2‧‧‧ second clock signal
V _P ‧‧‧Voltage signal
Freq_sweep‧‧‧frequency signal
V _{ref_P ‧‧‧bias}
V _{ref_V ‧‧‧bias}
V _cc ‧‧‧ power supply
V _{o21 ‧‧‧The} potential of the charging capacitor
V _{o24 ‧‧‧The} potential of the discharge capacitor
VNCS‧‧‧ bias

Figure 1 is a functional block diagram of a biomedical sensing device in accordance with a first embodiment of the present invention. Figure 2 is a functional block diagram of a low power power detector in accordance with a first embodiment of the present invention. Figure 3 is a circuit diagram of an amplitude voltage converter in accordance with a first embodiment of the present invention. Figure 4 is a circuit diagram of a bandgap bias circuit in accordance with a first embodiment of the present invention. Figure 5 is a circuit diagram of a non-overlapping clock generator in accordance with a first embodiment of the present invention. Figure 6 is a circuit diagram of a voltage peak detecting circuit in accordance with a first embodiment of the present invention. Figure 7 is a circuit diagram of an operational amplifier in accordance with a first embodiment of the present invention. Figure 8 is a circuit diagram of an output stage in accordance with a first embodiment of the present invention. Figure 9 is a circuit diagram of a high-torque inverter in accordance with a first embodiment of the present invention. Figure 10 is a functional block diagram of a biomedical sensing device in accordance with a second embodiment of the present invention. Figure 11 is a functional block diagram of a low power power detector in accordance with a second embodiment of the present invention. Figure 12 is a circuit diagram of a voltage valley detecting circuit in accordance with a second embodiment of the present invention. Figure 13 is a circuit diagram of an output stage in accordance with a second embodiment of the present invention. Figure 14 is a circuit diagram of a low twisting inverter in accordance with a first embodiment of the present invention.

100‧‧‧Low power power detector

110‧‧‧Amplitude voltage converter

120‧‧‧Band-gap bias circuit

130‧‧‧ Non-overlapping clock generator

140‧‧‧Voltage Detector

150‧‧‧Output

SW‧‧‧ clock signal

SW1‧‧‧ first clock signal

SW2‧‧‧ second clock signal

V _{rf_P} ‧‧‧ frequency sensing signal

V _{ref_P ‧‧‧bias}

V _P ‧‧‧Voltage signal

V _N ‧‧‧Voltage signal

Rst‧‧‧Reset signal

V _{opa_P ‧‧‧voltage} detection signal

Det_P‧‧‧Detection signal

R‧‧‧Reset transistor

Claims (19)

A low power consumption power detector, comprising: an amplitude voltage converter, receiving a frequency sensing signal and outputting a voltage signal, wherein a potential of the voltage signal is inversely proportional to an amplitude of the frequency sensing signal; An overlap clock generator outputs a first clock signal and a second clock signal, wherein the first clock signal and the high voltage section of the second clock signal do not overlap each other; Receiving the voltage signal and the first clock signal, the first clock signal is used to turn on or off the voltage detector, and the voltage detector is configured to detect the peak or valley value of the voltage signal to output a a voltage detection signal; and an output stage that receives the second clock signal and the voltage detection signal, and the output stage outputs a detection signal, the second clock signal and the voltage detection signal determine the detection The potential of the signal. The low power consumption power detector of claim 1, wherein the amplitude voltage converter has an isolation capacitor, an isolation resistor, a first transistor, and a filter circuit, and the one end of the isolation capacitor receives the a frequency sensing signal, the other end of the isolation capacitor is connected to the gate terminal of the first transistor, and the gate terminal of the first transistor receives a bias voltage through the isolation resistor, and the voltage of the first transistor outputs the voltage The signal, the source of the first transistor is extremely grounded, and the filter circuit is connected to the 汲 terminal of the first transistor. The low power consumption power detector of claim 2, wherein the filter circuit has a load transistor and a filter capacitor, and the source terminal of the load transistor receives a power source, and the gate of the load transistor Extremely grounded, the 电 terminal of the load transistor is connected to the 汲 terminal of the first transistor, one end of the filter capacitor is connected to the 汲 terminal of the first transistor, and the other end of the filter capacitor is grounded. A low power consumption power detector as described in claim 2, comprising a bandgap circuit for providing the bias voltage to the amplitude voltage conversion The first transistor of the device. The low power consumption power detector of claim 1, wherein the voltage detector is a voltage peak detection circuit. The low power consumption power detector of claim 5, wherein the voltage peak detecting circuit has an operational amplifier, a switching transistor, a charging transistor and a charging capacitor, the operational amplifier having a a power supply terminal, a first input terminal, a second input terminal, and an output terminal, wherein the power terminal receives the first clock signal, the first input terminal receives the voltage signal, and the second input terminal is connected to the charging capacitor. The output terminal outputs the voltage detection signal, the switch transistor receives the first clock signal and a power source, and the first clock signal is used to turn on or off the operational amplifier and the switch transistor, and the charging transistor receives The voltage detecting signal determines whether the charging transistor is turned on or off. When the switching transistor and the charging transistor are both turned on, the power source charges the charging capacitor via the switching transistor and the charging transistor. The low power consumption power detector of claim 6, wherein the voltage peak detecting circuit has a discharge transistor, the discharge transistor is connected to the charging capacitor, and the discharging transistor receives a reset a signal to determine whether the discharge transistor is turned on or off. When the discharge transistor is turned on, the charge capacitor is discharged to a low potential via the discharge transistor. The low power consumption power detector of claim 6 or 7, wherein the voltage peak detecting circuit has a compensation transistor connected to the charging transistor and the charging capacitor, the compensation The gate of the transistor receives the inverted voltage detection signal through an inverter to determine whether the compensation transistor is turned on or off, and the terminal and source terminals of the compensation transistor are short-circuited to each other. The low power consumption power detector of claim 8, wherein the compensation transistor has an aspect ratio that is half of an aspect ratio of the charging transistor. The low power consumption power detector of claim 1, wherein the voltage detector is a voltage valley detecting circuit. The low power consumption power detector of claim 10, wherein the voltage valley detecting circuit has an operational amplifier, a switching transistor, a discharge transistor and a discharge capacitor, the operational amplifier having a power terminal, a first input terminal, a second input terminal and an output terminal, the power terminal receives the first clock signal, the first input terminal receives the voltage signal, and the second input terminal is connected to the discharge capacitor The output terminal outputs the voltage detection signal, and the switch transistor receives the inverted first clock signal via an inverter, and the first clock signal is used to turn on or off the operational amplifier and the switch transistor. The discharge transistor receives the voltage detection signal to determine whether to turn on or off the discharge transistor, and one end of the discharge capacitor is connected to a power source. When the switch transistor and the discharge transistor are both turned on, the discharge capacitor passes the discharge. The transistor and the switching transistor are discharged. The low power consumption power detector of claim 11, wherein the voltage valley detecting circuit has a charging transistor, the charging transistor is connected to the discharging capacitor, and the charging transistor receives a reset. a signal to determine whether the charging transistor is turned on or off, and when the charging transistor is turned on, the discharging capacitor is charged to a high potential via the charging transistor. The low power consumption power detector of claim 11 or 12, wherein the voltage valley detecting circuit has a compensation transistor connected to the discharge transistor and the discharge capacitor, The gate terminal of the compensation transistor receives the inverted voltage detection signal through an inverter to determine whether the compensation transistor is turned on or off, and the terminal and source terminals of the compensation transistor are short-circuited to each other. The low power consumption power detector of claim 13, wherein the compensation transistor has an aspect ratio which is half of an aspect ratio of the discharge transistor. A low power consumption power detector as described in claim 6 or 11, wherein the operational amplifier is a rail to rail amplifier. The low power consumption power detector according to claim 5 or 6, wherein the output stage has an inverter and a gate, and the gate receives the voltage detection through the inverter. a test signal, and the gate receives the second clock signal, and the gate outputs the detection signal. The low power consumption power detector of claim 16, wherein the inverter is a high skew inverter, the high twist inverter has a P-type transistor and a An N-type transistor, wherein an aspect ratio of the P-type transistor is greater than an aspect ratio of the N-type transistor. The low power consumption power detector of claim 10 or 11, wherein the output stage has a first inverter, an inverse thyristor and a second inverter, the first inversion Receiving the voltage detection signal, the second inverter receiving the second clock signal, and the inverse thyristor receives the inverted voltage detection signal via the first inverter and the second inverter Inverting the second clock signal, the inverse gate outputs the detection signal. The low power consumption power detector of claim 18, wherein the first inverter is a low skew inverter, and the low twisted inverter has a P type transistor. And an N-type transistor, wherein the N-type transistor has an aspect ratio greater than an aspect ratio of the P-type transistor.