TWI573121B - Source driver - Google Patents

Description

Source driver

This invention relates to a source driver and, more particularly, to a source driver that can set a channel mode.

A liquid crystal display (LCD) includes a timing controller, a display panel, a gate driver, and a source driver. The display panel includes a plurality of pixels arranged in an array. The timing controller controls the source driver to output a plurality of pixel voltages to the display panel, and the timing controller controls the gate driver to output the plurality of scan signals sequentially enabled to the display panel to drive the pixels on a column by column basis. Then, the driven pixel receives the pixel voltage supplied from the source driver, thereby displaying the picture.

In general, the source driver includes a plurality of data channels, each of which provides a pixel voltage. In order to improve the versatility of the source driver, the number of data channels used in the source driver will be adjusted according to the resolution of the display panel. However, considering the convenience of setting the source driver, the source driver will provide several A common channel mode. Therefore, how to maintain the convenience of setting and increase the channel mode is an important point in designing the source driver.

The invention provides a source driver, which can increase the channel mode that can be set by the source driver without increasing the setting complexity.

The invention provides a source driver comprising a plurality of data channels and a data control unit. These data channels are used to provide multiple pixel voltages. The data control unit is coupled to the data channels and receives a setting command having a plurality of first bits for setting a channel mode through a serial interface. The data control unit sets the number used in the data channels according to the channel modes corresponding to the first bits.

In an embodiment of the present invention, the data control unit further receives a mode voltage, and the data control unit sets the data channel according to the channel mode corresponding to the first bit when the mode voltage is a first voltage level. quantity.

In an embodiment of the present invention, the data control unit further receives at least one set voltage, and the data control unit sets the data channels used in the data channels according to the channel mode corresponding to the set voltage when the mode voltage is a second voltage level. Quantity.

In an embodiment of the invention, the first voltage level and the second voltage level are respectively a high voltage level and a low voltage level.

In an embodiment of the invention, the data control unit further provides a data latching signal to the data channels to control the data channels to provide the pixel voltages.

In an embodiment of the invention, the setting command further includes a plurality of second bits for setting a pulse width of the data latch signal, and the data control unit sets the pulse width of the data latch signal according to the second bits. .

In an embodiment of the invention, the setting instruction further includes setting data A plurality of third bits of the enable start time of the latch signal, and the data control unit sets the enable start time of the data latch signal according to the third bits.

In an embodiment of the invention, the enable start time of the data latch signal is a fixed time point.

In an embodiment of the invention, the data start-up time of the data latching signal is located after a data receiving period, and during the data receiving period, the data control unit receives the plurality of display materials through the serial interface.

In one embodiment of the invention, the set command is provided by a timing controller of a display.

Based on the above, in the source driver of the embodiment of the present invention, the data control unit receives the setting command through the serial interface, and sets the plurality of data channels to be used according to the plurality of first bits used to set the channel mode in the setting instruction. The number of data channels. Therefore, the complexity of setting the source driver is not increased, and the channel mode that the source driver can support can be improved.

The above described features and advantages of the invention will be apparent from the following description.

100,400‧‧‧ display

110‧‧‧Sequence Controller

120‧‧‧gate driver

130, 430‧‧‧ source driver

131, 431‧‧‧ data control unit

133_1~133_n‧‧‧ data channel

140‧‧‧ display panel

CM1, CM2‧‧‧ setting instructions

CST‧‧‧ instruction start signal

DP‧‧‧ Display data packet

DST‧‧‧ data start signal

EST‧‧‧Enable start time

LD‧‧‧ data latching signal

During P1, P2, P2a, P3‧‧

SC‧‧‧ scan signal

SSD‧‧‧Listed data

T1‧‧‧ time

TP‧‧‧ training package

VMD‧‧‧ mode voltage

VP_1~VP_n‧‧‧Pixel voltage

VS1, VS2‧‧‧ set voltage

W1‧‧‧ pulse width

1 is a system diagram of a display in accordance with an embodiment of the present invention.

FIG. 2 is a timing diagram of the serial data according to FIG. 1 according to an embodiment of the invention.

FIG. 3 is a timing diagram of the serial data according to another embodiment of the present invention.

4 is a system diagram of a display in accordance with another embodiment of the present invention.

1 is a system diagram of a display in accordance with an embodiment of the present invention. Referring to FIG. 1 , in the embodiment, the display 100 includes a timing controller 110 , a gate driver 120 , a source driver 130 , and a display panel 140 . The timing controller 110 is coupled to the source driver 130 to provide the serial data SSD to the source driver 130. The gate driver 120 is coupled to the timing controller 110 and the display panel 140, and is controlled by the timing controller 110 to provide a plurality of scan signals SC to the display panel 140, wherein the scan signals SC are used to drive the display panel 140. The source driver 130 is coupled to the display panel 140 to provide a plurality of pixel voltages (eg, VP_1 VP_n) to the display panel 140 according to the serial data SSD to determine an image displayed by the display panel 140, where n is a positive integer.

In this embodiment, the source driver 130 includes a data control unit 131 and a plurality of data channels 133_1 ～ 133_n. The data channels 133_1~133_n are used to provide pixel voltages VP_1~VP_n, wherein the data channel 133_1 is used to provide the pixel voltage VP_1, the data channel 133_2 is used to provide the pixel voltage VP_2, and so on. The data control unit 131 is coupled to the timing controller 110 to receive the serial data SSD, and is coupled to the data channels 133_1 ～ 133_n to control the data channels 133_1 ～ 133_n. Further, the data control unit 131 controls the number of data channels used in the data channels 133_1~133_n, controls the pixel voltages VP_1~VP_n output by the data channels 133_1~133_n, and outputs the data latch signal LD to the data channel. 133_1~133_n provide pixel data by controlling data channel data channels 133_1~133_n The time point of pressing VP_1~VP_n. The number of data channels used in the data channels 133_1~133_n corresponds to the resolution of the display panel 140.

For example, if n=1024 and the resolution of the display panel 140 is 800×600, the number of data channels used in the data channels 133_1~133_n can be controlled by the serial data SSD provided by the timing controller 110. 800, while unused data channels can be closed or bypassed. In addition, if the resolution of the display panel 140 is 1024×768, the number of data channels used in the data channel 133_1~133_n that can be transmitted through the serial data SSD provided by the timing controller 110 is 1024. The channel mode (that is, the number of data channels that can be selected) that the source driver 130 can use depends on the number of bits used to set the channel mode in the serial data SSD, which may be based on circuit design and the usual The knowledge is designed by the individual.

According to the above, since the data control unit 131 of the source driver 130 sets the number of data channels used in the data channels 133_1 ～ 133_n according to the serial data SSD, the setting complexity is not increased, and the source driver 130 can be improved. Supportable channel mode.

FIG. 2 is a timing diagram of the serial data according to FIG. 1 according to an embodiment of the invention. Referring to FIG. 1 and FIG. 2, in the period P1, the timing controller 110 transmits a plurality of training packets TP to the data control unit 131 of the source driver 130 through the serial interface, so that the data control unit 131 can lock the timing controller. The clock of 110 operates in synchronization with timing controller 110, where period P1 can be considered as the clock training period of source driver 130.

In the period P2, the timing controller 110 transmits the finger through the serial interface. The start signal CST is commanded to inform the data control unit 131 to start transmitting the setting command (here, two setting commands CM1 and CM2 are taken as an example). Then, the timing controller 110 sequentially transmits the setting commands CM1 and CM2 through the serial interface to set the operation mode of the source driver 130, for example, the enabling period of the data latch signal LD (here, at the high voltage level) The period is, for example, the time T1 between the period P3, the pulse width W1 of the data latch signal LD, or the number of data channels used for setting the data channels 133_1 to 133_n. After setting the command CM2, the timing controller 110 transmits the data start signal DST through the serial interface to inform the data control unit 131 to start transmitting the display data packet DP. The period P2 can be regarded as the instruction receiving period of the source driver 130.

In the period P3, the timing controller 110 transmits the plurality of display data packets DP according to the serial interface to set the pixel voltages VP_1 VP VP_n provided by the data channels 133_1 ～ 133_n, wherein the number of data packets DP is displayed corresponding to the data channel. The number of data channels used in 133_1~133_n, and period P3 can be regarded as the data reception period of the source driver 130.

After the period P3, the data control unit 131 has received the data required for the operation, but the data control unit 131 needs a period of time to control the data channels 133_1~133_n to prepare the output pixel voltages VP_1~VP_n, where the time T1 is taken as an example. Therefore, after the time T1, the data control unit 131 sets the data latch signal LD to the enable level (here, taking the high voltage level as an example) to control the data channels 133_1~133_n to output the pixel voltages VP_1~VP_n. That is, the enable start time EST of the data latch signal LD is located after the data reception period (ie, period P3). among them, The pulse width W1 of the data latch signal LD is greater than or equal to the time required for the display panel 140 to react to the pixel voltages VP_1 VP VP_n.

In an embodiment of the present invention, the setting command CM1 can be set to set the time T1 (that is, the enable start time EST of the data latch signal LD), the pulse width W1 of the data latch signal LD, and the setting. The number of data channels used in the data channels 133_1~133_n, and it is assumed that the setting command CM1 is a 24-bit packet (here denoted by B0 to B23). Wherein, the bit B0~B7 (corresponding to the third bit) can be assumed to be used to set the time T1, and the bit B8~B17 (corresponding to the second bit) can be assumed to set the pulse width W1, the bit B18~ B23 (corresponding to the first bit) can be assumed to be used to set the channel mode of the source driver 130 (that is, the number of data channels selectable by the source driver 130), that is, the source driver 130 can select 64 (ie, 2 ⁶ ). A channel mode, and the unit of the above time is exemplified by the time required to transmit a packet.

For example, suppose the minimum value of time T1 is corresponding to 5 packets. If bit B0~B7 is "0000001", time T1 is set to correspond to 6 packets; if bits B0~B7 are "0000010", then Time T1 will be set to correspond to 7 packets, and the rest will be deduced by analogy. Assume that the minimum value of the pulse width W1 is corresponding to four packets. If the bits B8 to B17 are "0000000001", the pulse width W1 is set to correspond to five packets; if the bits B8 to B17 are "0000000010", then The pulse width W1 will be set to correspond to 6 packets, and the rest will be deduced by analogy.

According to the above setting, the data control unit 131 sets the data channels 133_1~133_n according to the channel mode corresponding to the bits B18~B23 of the setting command CM1. The data control unit 131 sets the pulse width W1 of the data latch signal LD according to the bits B8~B17, and the data control unit 131 sets the time T1 according to the bits B0~B7 (that is, the data latch signal LD is set). Can start time EST).

In another embodiment of the present invention, it can be assumed that the time T1 is a fixed value (that is, the enable start time EST of the data latch signal LD is a fixed time point), and it is assumed that the setting command CM1 is used to set the data pin. The pulse width W1 of the lock signal LD and the number of data channels used in the set data channels 133_1~133_n. Here, it is also assumed that the setting command CM1 is a 24-bit packet (here, still represented by B0 to B23). Wherein, the bit B0~B8 (corresponding to the first bit) can be assumed to be used to set the channel mode of the source driver 130 (that is, the number of data channels selectable by the source driver 130), that is, the source driver 130 can be selected. 512 (ie 2 ⁹ ) channel modes, bits B9~B18 (corresponding to the second bit) can be assumed to be used to set the pulse width W1, bits B19~B23 are spare bits, and the units of the above time are transmitted The time required for a packet is an example. The method of estimating the pulse width W1 can be referred to the above, and will not be described again here.

According to the above setting, the data control unit 131 sets the quantity used in the data channels 133_1~133_n according to the channel mode corresponding to the bits B0~B8 of the setting command CM1, and the data control unit 131 sets the data latching signal according to the bit B9~B18. The pulse width of the LD is W1.

FIG. 3 is a timing diagram of the serial data according to another embodiment of the present invention. Referring to FIG. 2 and FIG. 3, the timing of the serial data shown in FIG. 3 is substantially the same as the timing of the serial data shown in FIG. 2, and the difference is in the period P2a, in which the same or phase The same parts are given the same or similar reference numerals.

In the period P2a, the timing controller 110 transmits the command start signal CST through the serial interface to inform the data control unit 131 to start transmitting the set command (here, the two set commands CM1 and CM2 are also taken as an example). Then, the timing controller 110 sequentially transmits the setting commands CM1 and CM2 through the serial interface to set the operation mode of the source driver 130. After setting the command CM2, the timing controller 110 transmits the plurality of training packets TP to the data control unit 131 of the source driver 130 again through the serial interface, so that the data control unit 131 can reconfirm whether it is synchronous with the timing controller 110. . After the data control unit 131 can confirm that the operation is synchronized with the timing controller 110, the timing controller 110 transmits the data start signal DST through the serial interface to inform the data control unit 131 to start transmitting the display data packet DP. The period P2a can be regarded as the instruction receiving period of the source driver 130.

4 is a system diagram of a display in accordance with another embodiment of the present invention. Referring to Figures 1 and 4, display 400 is substantially identical to display 200, except that source driver 430, wherein the same or similar parts are given the same or similar reference numerals. In this embodiment, the data control unit 431 further receives the mode voltage VMD, the set voltages VS1 and VS2, wherein the data control unit 431 determines the data channels 133_1~133_n according to the serial data SSD or the set voltages VS1 and VS2 according to the mode voltage VMD. The quantity used in .

Further, when the mode voltage VMD is at the first voltage level (for example, a high voltage level), the data control unit 431 sets the number used in the data channels 133_1 ～ 133_n according to the serial data SSD. In other words, according to the embodiment of Fig. 2 The data control unit 431 sets the data channels 133_1~133_n used in the channel mode corresponding to the plurality of bits (such as the bits B18~B23) of the setting command (such as CM1 or CM2) for setting the channel mode. Quantity.

When the mode voltage VMD is at the second voltage level (for example, a low voltage level), the data control unit 431 sets the number used in the data channels 133_1 ～ 133_n according to the set voltages VS1 and VS2. For example, when the set voltages VS1 and VS2 are both high voltage levels, the data control unit 431 sets the number used in the data channels 133_1~133_n to be 966; when the set voltage VS1 is the low voltage level and the set voltage VS2 is the high voltage. When the level is set, the data control unit 431 sets the number used in the data channels 133_1~133_n to be 960; when the set voltage VS1 is the high voltage level and the set voltage VS2 is the low voltage level, the data control unit 431 sets the data channel 133_1. The number used in ~133_n is 726; when the set voltages VS1 and VS2 are both low voltage levels, the data control unit 431 sets the number used in the data channels 133_1~133_n to be 720.

In this embodiment, the two set voltages are taken as an example, but in other embodiments, the set voltage may be one or two or more, which may be designed by a person skilled in the art, and the embodiment of the present invention does not Limited. Moreover, the embodiment of the present invention can set the number used in the data channels 133_1 ～ 133_n in two ways to improve the fault tolerance of the source driver 400.

In summary, in the source driver of the embodiment of the present invention, the data control unit sets the number of data channels used in the plurality of data channels according to the serial data, so the setting complexity is not increased, and the source can be improved. Extreme drive support Channel mode. Moreover, the data control unit can further set the number of data channels used in the data channels according to at least one set voltage to improve the fault tolerance of the source driver.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100‧‧‧ display

110‧‧‧Sequence Controller

120‧‧‧gate driver

130‧‧‧Source Driver

131‧‧‧Data Control Unit

133_1~133_n‧‧‧ data channel

140‧‧‧ display panel

LD‧‧‧ data latching signal

SC‧‧‧ scan signal

SSD‧‧‧Listed data

VP_1~VP_n‧‧‧Pixel voltage

Claims (10)

A source driver includes: a plurality of data channels for providing a plurality of pixel voltages; and a data control unit coupled to the data channels and receiving a plurality of numbers for setting a channel mode through a serial interface a data setting unit of the one-bit, the data control unit sets the quantity used in the data channels according to the channel mode corresponding to the first bits, and closes unused portions of the data channels. The source driver of claim 1, wherein the data control unit further receives a mode voltage, and the data control unit corresponds to the first bit according to the mode voltage being a first voltage level. The channel mode sets the number used in these data channels. The source driver of claim 2, wherein the data control unit further receives at least one set voltage, and the data control unit is configured according to the channel corresponding to the set voltage when the mode voltage is a second voltage level The mode sets the number used in these data channels. The source driver of claim 3, wherein the first voltage level and the second voltage level are respectively a high voltage level and a low voltage level. The source driver of claim 1, wherein the data control unit further provides a data latch signal to the data channels to control the data channels to provide the pixel voltages. The source driver of claim 5, wherein the setting command further comprises a plurality of second bits for setting a pulse width of the data latch signal, The data control unit sets the pulse width of the data latch signal according to the second bits. The source driver of claim 5, wherein the setting command further comprises a plurality of third bits for setting an enable start time of the data latch signal, and the data control unit is configured according to the The three bits set the enable start time of the data latch signal. The source driver of claim 5, wherein the enable start time of the data latch signal is a fixed time point. The source driver of claim 5, wherein the data start time of the data latch signal is after a data receiving period, and the data control unit receives the plurality of serial interfaces through the serial interface. Display data. The source driver of claim 1, wherein the setting command is provided by a timing controller of a display.