TWI572038B - High voltage metal-oxide-semiconductor field-effect transistor device - Google Patents

Description

High voltage gold oxide half field effect transistor

The present invention relates to a structure of a high voltage MOS field device, and more particularly to a structure of a high voltage MOSFET that can raise the breakdown voltage of a device.

The high voltage metal-Oxide-Semiconductor Field-Effect Transistor (HV MOSFET) component layout is usually designed to be circular, from the top view of the circular HV MOSFET component. The center of the circle is the drain (Drain), and the outer part of the ring around the drain is the source. In addition, the channel width of the circular HV MOSFET is determined by the circumference of the region between the drain and the source. Therefore, if the on-current of the HV MOSFET device is to be increased, the radius of the circular HV MOSFET component needs to be increased, but also The area of the HV MOSFET component is relatively increased.

In order to simultaneously increase the on-current of the HV MOSFET component and minimize the area of the HV MOSFET component, a racetrack-shaped HV MOSFET component and an M-shaped HV MOSFET component have been developed. However, for larger on-state currents, M-shaped HV MOSFET components are currently the preferred choice.

However, the breakdown voltage (Breakdown Voltage, BDV) of the M-shaped HV MOSFET component completed by the conventional process is smaller than the breakdown voltage of the circular and racetrack-shaped HV MOSFET components, respectively, so if the three shapes are integrated at the same time, When the HV MOSFET device is in the same integrated circuit chip, it is limited by the breakdown voltage of the M-shaped HV MOSFET device, resulting in a decrease in the withstand voltage capability of the entire bulk circuit chip.

However, according to research by the inventors, the conventional M-shaped HV MOSFET component has a higher electric field and a larger current in a part of the component due to the shape of a special component having a plurality of corners, and relatively reduces the withstand voltage capability of the region. In order to improve the breakdown voltage of the overall M-shaped HV MOSFET device, the inventor has previously applied the "high-voltage MOS transistor device and its fabrication method" of the application number 100130576 to improve this deficiency, but still has not completed Ideal.

In view of this, how to further improve the breakdown voltage of M-shaped HV MOSFET components to achieve the goal of integrating various shapes of HV MOSFET components is to develop the main purpose of the case.

It is an object of the present invention to provide a high voltage gold oxide half field effect transistor device comprising: a substrate having a first conductivity type; a deep well region disposed in the substrate and having a second conductivity different from the first conductivity type Type, and the deep well zone has an edge portion and an intermediate portion, the edge portion is located around the intermediate portion and surrounds the intermediate portion; a source/base region is disposed in the deep well region, wherein a channel region is defined; a drain region Provided in the deep well region; a gate structure disposed between the source/base region and the drain region, comprising an insulating layer; and a first doped region disposed in the region and located in the insulating layer Bottom, and the first doped region has a first conductivity type, and the doping concentration of the first doped region in the edge portion has a first ratio between the doping concentration of the edge portion of the deep well region, and is located in the middle portion There is a first between the doping concentration of the first doping region and the doping concentration of the middle portion of the deep well region Two ratios, and the variability of the first ratio and the second ratio is less than or equal to 5%.

In a preferred embodiment of the invention, the substrate is a germanium substrate.

In a preferred embodiment of the present invention, the source/substrate region comprises: a high-voltage well region disposed in the deep well region and having the first conductivity type; a substrate contact region disposed in the high-voltage well region, The first conductivity type has a higher dopant concentration than the high voltage well region; and a source contact region is disposed in the high voltage well region and has the second conductivity type.

In a preferred embodiment of the present invention, the drain region includes: a drift region (DRIFT) disposed in the deep well region and having the second conductivity type; and a drain contact region disposed in the drift region And having the above second conductivity type, the dopant concentration being higher than the drift region.

In a preferred embodiment of the present invention, the gate structure further includes: a gate dielectric layer disposed over the channel region; a gate conductor layer disposed on the surface of the gate dielectric layer; and a field The electrode structure is disposed on the surface of the insulating layer.

In a preferred embodiment of the invention, the first doped region is a falling field layer.

In a preferred embodiment of the invention, the high voltage MOS field device is an M type high voltage MOSFET.

In a preferred embodiment of the invention, the first conductivity type is a P type, and the second conductivity type is an N type.

In a preferred embodiment of the invention, the first conductivity type is N-type and the second conductivity type is P-type.

Please refer to FIG. 1 , which is a schematic cross-sectional view of an HV MOSFET device, wherein A substrate 1 is provided having a first conductivity type; and a deep well region 11 is disposed in the substrate 1 having a second conductivity type different from the first conductivity type. The source/base region 12 and the drain region 13 are both disposed in the deep well region 11, and the source/base region 12 has the high conductivity well region 17 of the first conductivity type, and the high voltage well region 17 defines a channel. The gate structure 15 is disposed above the channel region 14, and the insulating layer 19 is disposed between the channel region 14 and the drain region 13, and can be completed by a structure such as a field oxide. The first doped region 16 is disposed in the deep well region 11 and below the field oxide layer, and the first doped region 16 has the first conductivity type. The following is exemplified by the first conductivity type being P-type and the second conductivity type being N-type, but the practical application is not limited thereto, and the first conductivity type is N-type and the second conductivity type is P-type.

According to the research by the inventors, it is found that the HV MOSFET component undergoes a high temperature and a long time after the thermal process, due to the thermal diffusion effect caused by the high temperature in the thermal process, the dopant in the M-shaped HV MOSFET component is distributed. The variation causes the concentration ratio of the P-type dopant in the first doped region 16 to complete the P-type p-top layer to the N-type dopant in the deep well region 11 to be uneven, resulting in a partial region. The concentration ratio of the P-type dopant in the first doped region 16 to the N-type dopant in the deep well region 11 has deviated too far from the preset value to induce a drop in the breakdown voltage. In particular, the N-type dopant in the edge portion 111 of the deep well region 11 is greatly reduced in concentration due to its easy diffusion to the outside of the deep well region 11, resulting in the N-type dopant concentration in the edge portion 111 and the intermediate portion 112 of the deep well region 11. The unevenness as shown in Fig. 2 will be produced. In Fig. 2, the upper view of the deep well region 11 is shown, which is formed by the concentration of the N-type dopant which is originally uniformly distributed after the thermal diffusion effect caused by the long-time thermal process. The concentration distribution diagram is such that the N-type dopant concentration of the edge portion 111 of the deep well region 11 is lower than the N-type dopant concentration of the intermediate portion 112.

In view of this, the present invention proposes a technical solution in FIGS. 3A to 3C. To solve such a problem, first, FIG. 3A shows that an N-type deep well region 31 is formed in a P-type substrate 3, and the N-type dopant concentration and the intermediate portion 312 of the edge portion 311 in the N-type deep well region 31 are controlled. The N-type dopant concentration is different when the doping is completed, mainly because the N-type dopant concentration of the edge portion 311 is greater than the N-type dopant concentration of the intermediate portion 312. Then, as shown in FIG. 3B, a source/body region 32 and a drain region 33 and a first doping region 36 are formed in the N-type deep well region 31, and then other structures such as the gate structure 35 are completed. A cross-sectional view of the high voltage MOS semi-transistor element as shown in Fig. 3C is formed. The P-type substrate 3 may be a P-type germanium substrate, and the source/body region 32 includes a P-type high-pressure well region 320 and a P+ substrate contact region 321 having a higher dopant concentration than the P-type high-pressure well region 320. And an N+ source contact region 322. The drain region 33 includes an N-type drift region (N-DRIFT) 330 and an N+ drain contact region 331 having a higher dopant concentration than the N-type drift region 330. The gate structure 35 includes a gate dielectric layer 350 disposed above the channel 34, the N-type deep well region 31 and the first doped region 36, and an insulator layer 352, and is disposed on the gate layer The gate dielectric layer 350 and the gate conductor layer 351 on the surface of the insulating layer 352 and the field electrode structure 353.

As a result, since the N-type dopant concentration of the edge portion 311 in the N-type deep well region 31 is controlled to be greater than the N-type dopant concentration concentration of the intermediate portion 312 at the completion of doping, it is caused by a long heat process. After the thermal diffusion effect, the N-type dopant concentration of the edge portion 311 of the deep well region 31 may be lowered by diffusion to a level corresponding to the N-type dopant concentration of the intermediate portion 312, preferably the first doped region 36 The concentration ratio of the P-type dopant to the N-type dopant of the deep well region 31 is less than or equal to 5% of the relative difference between the edge portion 311 and the intermediate portion 312. In this way, the lack of conventional means can be effectively improved, and the effect of improving the breakdown voltage can be improved, and the application number can also be matched. The technical means of the "high-voltage MOS transistor crystal element and its manufacturing method" of 100130576 are used together, so that a better effect can be achieved.

How to control the N-type dopant concentration of the edge portion 311 in the N-type deep well region 31 to be greater than the N-type dopant concentration in the intermediate portion 312 when the doping is completed, the following several methods are proposed in the present case: the first method, That is, the implantation of the N-type dopant can be performed by using two masks, wherein the first mask has an opening for N-type dopant implantation to define the deep well region 31, and then the second mask is used. The opening is exposed to expose the edge portion 311 for the second N-type dopant implantation, such that the N-type dopant concentration of the edge portion 311 is greater than the N-type dopant concentration of the intermediate portion 312. The second method is to perform an N-type dopant implantation using the mask 40 as shown in FIG. 4, wherein the opening 41 of the mask completely exposes the edge portion 311 but the intermediate portion 312 is provided with a fence shape. The strip 42 is such that after the N-type dopant implantation is completed, a portion of the intermediate portion 312 is not implanted with the N-type dopant, so that the N-type dopant of the edge portion 311 can also be made. The concentration is greater than the N-type dopant concentration of the intermediate portion 312. As for the third method, an N-type dopant implantation is performed with a gradient mask, wherein the density of the dots of the gradient mask edge is lower, and the density of the dots toward the middle is higher. In this way, after the N-type dopant implantation is performed, the N-type dopant concentration of the edge portion 311 can be made larger than the N-type dopant concentration of the intermediate portion 312.

In addition, the ratio of the concentration ratio of the P-type dopant of the first doping region 36 to the N-type dopant of the deep well region 31 between the edge portion 311 and the intermediate portion 312 is controlled to be less than or equal to 5%. method. The adjustment is mainly performed on the P-type dopant concentration in the first doping region 36 without adjusting the concentration of the N-type dopant in the edge portion 311 of the N-type deep well region 31, that is, it belongs to the edge portion. The P-type dopant concentration of the first doped region 36 in the range of 311 is lowered, and the P-type dopant concentration of the first doped region 36 belonging to the intermediate portion 312 is increased. The method also has the following changes: In the first method, the implantation of the P-type dopant of the first doping region 36 can be performed by using two masks, wherein the first mask has an opening to expose all of the The first doped region 36 is implanted with a P-type dopant, and then the opening of the second mask is used to expose the intermediate portion 312 for a second P-type dopant implantation, such that the intermediate portion 312 can be made The P-type dopant concentration of the first doped region 36 within the range is greater than the P-type dopant concentration of the first doped region 36 within the range of the edge portion 311. In the second method, a P-type dopant is implanted by using the mask 50 as shown in FIG. 5, and the opening 51 in the mask belonging to the middle portion 312 completely exposes the first doping region 36. However, the opening 52 in the range of the edge portion 311 is a fence shape, so that the P-type dopant concentration of the first doping region 36 in the range of the intermediate portion 312 is greater than the first doping region 36 in the range of the edge portion 311. P-type dopant concentration. As for the third method, a P-type dopant implantation is performed with a gradient mask, wherein the density of the dots in the opening of the intermediate layer of the gradient mask is lower, and the edge is higher. The dot density in the opening is relatively high, so that the P-type dopant concentration of the first doping region 36 in the range of the intermediate portion 312 can be made larger than the edge portion 311 after the P-type dopant implantation is performed. The P-type dopant concentration of the first doped region 36. However, since the first doping region 36 which is doped is not like the N-type dopant in the deep well region 31, it is more likely to diffuse and escape due to the thermal process, so after the thermal diffusion effect caused by the long-time thermal process, the deep well region The N-type dopant concentration of the edge portion 311 of 31 will be lowered by diffusion, just matching the P-type dopant having a lower concentration in the first doping region 36 in the range of the edge portion 311, and thus the concentration ratio is at the edge portion 311. The degree of variability with the intermediate portion 312 can still be controlled to be less than or equal to 5%.

In summary, the present invention utilizes the adjustment of the doping concentration to reduce the unevenness of the concentration ratio after the completion of the component, thereby improving the phenomenon of insufficient breakdown voltage of the M-shaped HV MOSFET device in the conventional device.

While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application.

1‧‧‧Base

11‧‧‧Shenjing District

111‧‧‧The edge of the deep well area

112‧‧‧The middle part of the deep well area

12‧‧‧Source/base area

13‧‧‧Bungee Area

14‧‧‧Channel area

15‧‧‧ gate structure

16‧‧‧First doped area

17‧‧‧High-pressure well area

19‧‧‧Insulation

3‧‧‧Base

31‧‧‧Shenjing District

311‧‧‧The edge of the deep well area

312‧‧‧The middle part of the Sham Tseng District

32‧‧‧Source/base area

320‧‧‧High-pressure well area

321‧‧‧Body contact area

322‧‧‧Source contact area

33‧‧‧Bungee Area

330‧‧‧Drift area

331‧‧‧汲polar contact area

34‧‧‧Channel area

35‧‧‧ gate structure

350‧‧ ‧ gate dielectric layer

351‧‧‧ gate conductor layer

352‧‧‧Insulation

353‧‧‧Field electrode structure

36‧‧‧First doped area

40‧‧‧ mask

41‧‧‧ openings

42‧‧‧Fence bars

50‧‧‧ mask

51‧‧‧ openings

52‧‧‧Fenced opening

Figure 1: Schematic diagram of a HV MOSFET component.

Figure 2: It is a schematic diagram showing the concentration distribution formed by the concentration of the N-type dopant in the deep well area after a long-term thermal process.

3A to 3C are schematic views showing a method of forming an HV MOSFET device developed in the present invention.

Figure 4 shows a schematic view of a mask applied to the present case.

Figure 5 shows a schematic view of another mask applied to the present case.

3‧‧‧Base

31‧‧‧Shenjing District

32‧‧‧Source/base area

320‧‧‧High-pressure well area

321‧‧‧Source contact area

322‧‧‧Body contact area

33‧‧‧Bungee Area

330‧‧‧Drift area

331‧‧‧汲polar contact area

34‧‧‧Channel area

35‧‧‧ gate structure

350‧‧ ‧ gate dielectric layer

351‧‧‧ gate conductor layer

352‧‧‧Insulation

353‧‧‧Field electrode structure

36‧‧‧First doped area

Claims (14)

A high voltage MOS field device (HV MOSFET) comprising: a substrate having a first conductivity type; a deep well region disposed in the substrate and having a second conductivity type different from the first conductivity type And the deep well region has an edge portion and an intermediate portion, the edge portion is located around the intermediate portion and surrounds the intermediate portion; a source/substrate region is disposed in the deep well region, wherein a channel region is defined; a drain region disposed in the deep well region; a gate structure disposed between the source/base region and the drain region, including an insulating layer; and a first doped region disposed at the gate region The deep well region is located under the insulating layer of the gate structure, and the first doped region has the first conductivity type, and the doping concentration of the first doped region in the edge portion and the deep well region The doping concentration of the edge portion has a first ratio, and a doping concentration of the first doping region in the intermediate portion has a second ratio between a doping concentration of the intermediate portion of the deep well region, And the change of the first ratio and the second ratio The degree of heterogeneity is less than or equal to 5%, wherein the first conductivity type is a P type, and the second conductivity type is an N type. The high voltage MOS field device according to claim 1, wherein the substrate is a ruthenium substrate. The high voltage MOS field device according to claim 1, wherein the source/substrate region comprises: a high pressure well region disposed in the deep well region and having the first conductivity type; a substrate contact region disposed in the high voltage well region, having the first conductivity type, the dopant concentration is higher than the high voltage well region; and a source contact region disposed in the high voltage well region, having the first Two conductivity types. The high voltage MOS field device according to claim 1, wherein the drain region comprises: a drift region (DRIFT) disposed in the deep well region and having the second conductivity type; The pole contact region is disposed in the drift region and has the second conductivity type, and the dopant concentration is higher than the drift region. The high voltage MOS field device according to claim 1, wherein the gate structure further comprises: a gate dielectric layer disposed above the channel region; and a gate conductor layer disposed on the gate electrode layer a surface of the gate dielectric layer; and a field electrode structure disposed on the surface of the insulating layer. The high voltage MOS field device according to claim 1, wherein the first doped region is a falling field layer. The high-voltage gold-oxygen half-field effect transistor component described in claim 1 is an M-type high-voltage gold-oxygen half-field effect transistor component. A high voltage MOS field device (HV MOSFET) comprising: a substrate having a first conductivity type; a deep well region disposed in the substrate, having a second conductivity type different from the first conductivity type, and the deep well region has an edge portion and an intermediate portion, the edge portion being located around the intermediate portion and surrounding the a middle portion; a source/substrate region disposed in the deep well region, wherein a channel region is defined; a drain region is disposed in the deep well region; and a gate structure is disposed in the source/base region Between the drain regions, including an insulating layer; and a first doped region disposed in the deep well region and below the insulating layer of the gate structure, and the first doped region has the first a conductivity type, and a doping concentration of the first doping region in the edge portion and a doping concentration of the edge portion of the deep well region have a first ratio, the first doping in the middle portion The doping concentration of the region has a second ratio between the doping concentration of the intermediate portion of the deep well region, and the variability of the first ratio and the second ratio is less than or equal to 5%, wherein the first conductivity type is N type, the second conductivity type is P type. The high voltage gold oxide half field effect transistor device of claim 8, wherein the substrate is a germanium substrate. The high voltage MOS field device according to claim 8, wherein the source/substrate region comprises: a high voltage well region disposed in the deep well region and having the first conductivity type; a substrate contact a region, disposed in the high voltage well region, having the first conductivity type, the dopant concentration being higher than the high voltage well region; and a source contact region disposed in the high voltage well region having the second conductivity type . The high voltage MOS field device according to claim 8, wherein the drain region comprises: a drift region (DRIFT) disposed in the deep well region and having the second conductivity type; The pole contact region is disposed in the drift region and has the second conductivity type, and the dopant concentration is higher than the drift region. The high voltage MOS field device according to claim 8, wherein the gate structure further comprises: a gate dielectric layer disposed above the channel region; and a gate conductor layer disposed on the gate electrode layer a surface of the gate dielectric layer; and a field electrode structure disposed on the surface of the insulating layer. The high voltage MOS field device according to claim 8, wherein the first doped region is a falling field layer. For example, the high-voltage gold-oxygen half-field effect transistor component described in claim 8 is an M-type high-voltage gold-oxygen half-field effect transistor component.