TWI571973B - Method of manufacturing non-volatile memory - Google Patents

Description

Non-volatile memory manufacturing method

The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a non-volatile memory.

As the semiconductor enters the Deep Sub-Micron process, the size of the component is gradually reduced, and for the memory component, it means that the memory cell size is getting smaller and smaller. On the other hand, as information electronics (such as computers, mobile phones, digital cameras, or personal digital assistants (PDAs)) need to process and store more and more data, the memory required in these information electronics The capacity is getting bigger and bigger. In the case where the size is small and the memory capacity needs to be increased, how to manufacture a memory element having a reduced size, a high degree of integration, and a quality can be a consistent goal of the industry.

Since the non-volatile memory element has the advantage that the stored data does not disappear after the power is turned off, it has become a memory element widely used in personal computers and electronic devices.

A conventional non-volatile memory consisting of two MOS semiconductors connected in series The transistors are respectively formed as a selection transistor and a floating gate transistor. The selection gate of the selected transistor and the floating gate of the floating gate transistor are formed by photolithographic etching using the same layer of polysilicon.

However, when the selective gate and the floating gate are formed by photolithography etching, they are limited by the lithography process, and the minimum pattern width of the formed pattern and the minimum interval between the patterns have their limits. Therefore, the spacing between the selected gate and the floating gate cannot be further reduced.

The invention provides a method for manufacturing a non-volatile memory, which can reduce the spacing between the control gate and the floating gate and increase the accumulation degree of the components.

A method of manufacturing a non-volatile memory of the present invention comprises the following steps. A substrate is provided on which a dielectric layer, a first conductor layer, a second conductor layer, and a cap layer are sequentially formed. The cap layer and the second conductor layer are patterned to form a stacked structure and expose the first conductor layer. A spacer is formed on the sidewall of the stacked structure, and a patterned mask layer is formed on the first conductor layer on one side of the stacked structure. After the spacer is removed, a patterned cap layer and a patterned mask layer are used as a mask to remove a portion of the first conductor layer and a portion of the dielectric layer to form a select gate and a floating gate.

In an embodiment of the invention, the step of forming a spacer on the sidewall of the stacked structure includes: forming an insulating layer on the substrate, and performing an anisotropic etching process to remove a portion of the insulating layer.

In an embodiment of the invention, the material of the spacer includes tantalum nitride.

In an embodiment of the invention, the material of the cap layer is one selected from the group consisting of cerium oxide, cerium nitride, and combinations thereof.

In an embodiment of the invention, the step of forming the patterned mask layer on the first conductor layer on one side of the stacked structure is as follows. A mask material layer is formed on the first conductor layer, and a patterned photoresist layer is formed to cover the partial stack structure and the mask material layer. The patterned photoresist layer is used as a mask to remove a portion of the mask material layer. The patterned photoresist layer is removed.

In an embodiment of the invention, the step of forming a patterned mask material layer on the first conductor layer comprises performing a thermal oxidation process.

A method of manufacturing a non-volatile memory of the present invention comprises the following steps. A substrate is provided on which a dielectric layer, a first conductor layer, and an etch stop layer are sequentially formed. The etch stop layer is patterned to form an opening. A second conductor layer is formed on the substrate, and the second conductor layer fills the opening. A cap layer is formed on the second conductor layer. The cap layer, the second conductor layer, and the etch stop layer are patterned to form a stacked structure and expose the first conductor layer, wherein the openings are in the stacked structure. A spacer is formed on the sidewall of the stacked structure. A patterned mask layer is formed on the first conductor layer on one side of the stacked structure. After the spacer is removed, a patterned cap layer and a patterned mask layer are used as a mask to remove a portion of the first conductor layer and a portion of the dielectric layer to form a select gate and a floating gate.

In an embodiment of the invention, the material of the etch stop layer is one selected from the group consisting of ruthenium oxide, tantalum nitride, and combinations thereof.

In an embodiment of the invention, the sidewalls of the stacked structure are formed The step of forming a spacer includes: forming an insulating layer on the substrate, and performing an anisotropic etching process to remove a portion of the insulating layer.

In an embodiment of the invention, the material of the spacer includes tantalum nitride.

In an embodiment of the invention, the material of the cap layer is one selected from the group consisting of cerium oxide, cerium nitride, and combinations thereof.

In an embodiment of the invention, the step of forming the patterned mask layer on the first conductor layer on one side of the stacked structure is as follows. A mask material layer is formed on the first conductor layer to form a patterned photoresist layer covering a portion of the stacked structure and the mask material layer. The patterned photoresist layer is used as a mask to remove a portion of the mask material layer. The patterned photoresist layer is removed.

In an embodiment of the invention, the step of forming a mask material layer on the first conductor layer comprises performing a thermal oxidation process.

In an embodiment of the present invention, the step of patterning the cap layer, the second conductor layer, and the etch stop layer comprises: performing a first etching process by using the patterned cap layer as a mask The second conductor layer is exposed to the etch stop layer; and the patterned cap layer is used as a mask, and a second etching process is performed to remove the etch stop layer until the first conductor layer is exposed.

Based on the above, in the method of manufacturing a non-volatile memory of the present invention, an etch stop layer is formed between the first conductor layer and the second conductor layer, so that a process of depositing the doped polysilicon twice is performed. If the etch stop layer is not formed, the first conductor layer and the second conductor layer can be regarded as a single film layer, and a deposition process of doping polysilicon once is performed.

In the method for producing a non-volatile memory of the present invention, an etch stop layer is formed between the first conductor layer and the second conductor layer, and three photomasks are used in comparison with the conventional logic circuit process. In another embodiment, an etch stop layer is not formed between the first conductor layer and the second conductor layer, and only two masks are used in comparison to conventional logic circuit processes.

In the method for manufacturing a non-volatile memory of the present invention, the pitch between the gate and the floating gate is selected, and the thickness of the spacer is determined, so that the spacing between the gate and the floating gate can be further narrowed. Improve the accumulation of components.

The features and advantages of the present invention will become more apparent from the following description.

100‧‧‧Base

102a, 102b, 102c‧‧‧ doped areas

104‧‧‧ dielectric layer

104a‧‧‧Selecting the gate dielectric layer

104b‧‧‧Tunnel dielectric layer

110, 110a, 110b‧‧‧ conductor layer

111, 111a, 111b‧‧‧ etch stop layer

112‧‧‧ openings

114‧‧‧Conductor layer

116‧‧‧Top cover

120, 120a‧‧ ‧ cover layer

122‧‧‧ spacer

124‧‧‧ patterned photoresist layer

D‧‧‧汲

FG‧‧‧Floating gate

FT‧‧‧Floating gate transistor

S‧‧‧ source

SG‧‧‧Selected gate

ST‧‧‧Selecting a crystal

1 is a cross-sectional view of a non-volatile memory in accordance with an embodiment of the present invention.

FIG. 2A is a schematic diagram showing a stylized operation mode of a non-volatile memory according to an embodiment of the present invention.

FIG. 2B is a schematic diagram showing a mode of erasing operation of a non-volatile memory according to an embodiment of the present invention.

FIG. 2C is a schematic diagram showing a read operation mode of a non-volatile memory according to an embodiment of the present invention.

3A to 3F are cross-sectional views showing a manufacturing process of a non-volatile memory according to an embodiment of the present invention.

1 is a cross-sectional view of a non-volatile memory in accordance with an embodiment of the present invention.

First, please refer to Fig. 1 to illustrate the non-volatile memory of the present invention. The non-volatile memory is disposed on the substrate 100, and includes a selection transistor ST and a floating gate transistor FT arranged in series.

Selecting the transistor ST includes selecting a gate dielectric layer 104a, selecting a gate (including the conductor layer 110a and the conductor layer 114), a doping region 102a, and a doping region 102b. The doped region 102a and the doped region 102b are disposed in the substrate 100 on both sides of the selection gate. An etch stop layer 111 is selectively disposed between the conductor layer 110a and the conductor layer 114, wherein the etch stop layer 111 has an opening 112 therein, and the conductor layer 114 is electrically connected to the conductor layer 110a via the opening 112. The etch stop layer 111 is composed of, for example, an etch stop layer 111a and an etch stop layer 111b. A cap layer 116 is selectively disposed on the conductor layer 114.

The floating gate transistor FT includes a tunneling dielectric layer 104b, a floating gate (conductor layer 110b), a doping region 102b, and a doping region 102c. A mask layer 120a is selectively disposed on the conductor layer 110b. The selected transistor ST and the floating gate transistor FT share the doped region 102b.

2A, FIG. 2B and FIG. 2C, the operation mode of the non-volatile memory according to the preferred embodiment of the present invention is included, which includes program (Program, FIG. 2A) and erase (Erase, FIG. 2B). ) and read (Read, Figure 2C) and other operating modes.

As shown in FIG. 2A, when the memory cell is programmed, the voltage Vp1 is applied to the selection gate SG to open the channel below the selection gate SG, Vp1. For example, a voltage of about 1 to Vcc volts is applied; a voltage Vp2 is applied to the drain region D, which is, for example, about 8 to 12 volts; and the source region S is, for example, a voltage of about 0 volts. Thus, during stylization, electrons move from the source region to the drain region, and are accelerated by the high-channel electric field at the end of the drain region to generate hot electrons, and the kinetic energy is sufficient to overcome the energy barrier of the tunnel oxide layer, so that the heat The electrons are injected into the floating gate FG from the 汲 extreme, and the memory cells are programmed.

As shown in FIG. 2B, when the memory cell is erased, a voltage Ve1 is applied to the drain region D, which is, for example, about 8 volts to 12 volts; the source region S, the selection gate SG is floating or 0 volts. . Thus, a large electric field can be established between the floating gate FG and the drain region D, and the electrons can be pulled out from the floating gate FG to the drain region D by the F-N tunneling effect.

As shown in FIG. 2C, when the memory cell is read, the voltage is applied to the gate SG, which is, for example, 1 volt to Vcc; and the voltage Vr2 is applied to the drain region D, which is, for example, 1 volt to Vcc. . Since the channel of the memory cell in which the total amount of charge in the floating gate FG is negative is closed and the current is small, and the channel of the memory cell in which the total charge amount of the floating gate FG is slightly positive is open and the current is large, it can be borrowed It is judged by the channel switch/channel current of the memory cell whether the digital information stored in the memory cell is "1" or "0".

3A-3H are flow diagrams showing the manufacture of a non-volatile memory cell according to a preferred embodiment of the present invention for explaining a method of fabricating the non-volatile memory of the present invention.

First, referring to FIG. 3A, a substrate 100 is provided. Material of the substrate 100 For example, it is a base. A dielectric layer 104 and a conductor layer 110 are formed on the substrate 100. The material of the dielectric layer 104 is, for example, ruthenium oxide. The method of forming the dielectric layer 104 is, for example, a thermal oxidation process of the germanium substrate. The material of the conductor layer 110 is, for example, a doped polysilicon, which is formed by, for example, forming an undoped polysilicon layer by chemical vapor deposition, and performing an ion implantation step to form it; or it may be used in the field (in-situ). The method of implanting the dopant is formed by chemical vapor deposition.

Referring to FIG. 3B, an etch stop layer 111 may be selectively formed on the conductor layer 110. The etch stop layer 111 may be a single layer structure or a multilayer structure. The material of the etch stop layer 111 is one selected from the group consisting of ruthenium oxide, tantalum nitride, and combinations thereof. In the present embodiment, the etch stop layer 111 is composed of, for example, an etch stop layer 111a and an etch stop layer 111b. The material of the etch stop layer 111a is, for example, ruthenium oxide. The material of the etch stop layer 111b is, for example, tantalum nitride.

The etch stop layer 111 is patterned to form the opening 112. The method of patterning the etch stop layer 111 is, for example, a photolithography process. Then, a conductor layer 114 is formed on the etch stop layer 111, and the conductor layer 114 fills the opening 112. The material of the conductor layer 114 is, for example, a doped polysilicon, which is formed by, for example, forming an undoped polysilicon layer by chemical vapor deposition, and performing an ion implantation step to form it; or it may be used in the field (in-situ). The method of implanting the dopant is formed by chemical vapor deposition. The etch stop layer 111 is, for example, an etch stop layer of polysilicon.

Referring to FIG. 3C, a cap layer 116 is formed on the conductor layer 114. The material of the cap layer 116 is, for example, yttria/tantalum nitride/yttria ("ONO"). The method for forming the cap layer 116 is, for example, first forming a layer of ruthenium oxide by thermal oxidation, followed by chemistry. A layer of tantalum nitride is formed by vapor deposition, and then a top yttrium oxide layer is formed on the tantalum nitride layer.

Then, the cap layer 116, the conductor layer 114, the etch stop layer 111 are patterned, and the conductor layer 110 is exposed to form a plurality of stacked structures in which the openings 112 are located in the stacked structure. The method of patterning the cap layer 116, the conductor layer 114, and the etch stop layer 111 includes the following steps. The cap layer 116 is first patterned. The method of patterning the cap layer 116 is, for example, a photolithography process. Then, with the patterned cap layer 116 as a mask, an etching process is performed to remove the conductor layer 114 until the etch stop layer 111 is exposed. Then, with the patterned cap layer 116 as a mask, another etching process is performed to remove the etch stop layer 111 until the conductor layer 110 is exposed.

In another embodiment, when the etch stop layer 111 is not formed between the conductor layer 110 and the conductor layer 114, the cap layer 116 and the conductor layer 114 are directly patterned to form a stacked structure, and the conductor layer 110 is exposed. .

Referring to FIG. 3D, a spacer 122 is formed on the sidewall of the stacked structure. The method of forming the spacers 122 on the sidewalls of the stacked structure is, for example, first covering the insulating layer on the substrate 100, and then removing a portion of the insulating layer to form the spacers 122 on the sidewalls of the stacked structure. The material of the insulating layer is, for example, tantalum nitride. The method of forming the insulating layer is, for example, a chemical vapor deposition method. A method of removing a portion of the insulating layer is, for example, an anisotropic etching method.

Then, a mask layer 120 is formed on the substrate 100. The material of the mask layer 120 is, for example, ruthenium oxide, and the method of forming the mask layer 120 is, for example, a thermal oxidation process.

Referring to FIG. 3E, a patterned photoresist layer 124 is formed on the substrate 100. this The patterned photoresist layer 124 covers a portion of the stacked structure and a portion of the mask layer 120. The patterned photoresist layer 124 is formed, for example, by applying a photoresist material, exposing and developing. With the patterned photoresist layer 124 as a mask, a portion of the mask layer 120 is removed, and the mask layer 120 is patterned to form a mask layer 120a.

Referring to FIG. 3F, the patterned photoresist layer 124 is removed. The method of removing the patterned photoresist layer 124 is, for example, a wet de-resisting method or a dry de-resisting method. Then, the spacers 122 on the sidewalls of the stacked structure are removed, and the removal method uses, for example, hot phosphoric acid as an etchant.

Next, the patterned cap layer 116 and the mask layer 120a are used as a mask to remove a portion of the conductor layer 110 to form a selective gate (including the conductor layer 112 and the conductor layer 110b) and a floating gate (the conductor layer 110b). ). Then, a portion of the dielectric layer 104 is further removed to form the selective gate dielectric layer 104a and the tunneling dielectric layer 104b. In the above embodiment, the gate dielectric layer 104a is selected to have the same thickness as the tunnel dielectric layer 104b. Of course, the thickness of the gate dielectric layer 104a and the tunnel dielectric layer 104b may be different.

Doping regions 102a (source/drain regions) and doping regions 102c (source/drain regions) are formed in the substrate 100 on both sides of the selection gate and the floating gate, and the gate and the floating gate are selected. A doped region 102b is formed in the substrate 100 between the gates. A method of forming the doping region 102a (source/drain region), the doping region 102b, and the doping region 102c (source/drain region) is, for example, an ion implantation method. The subsequent completion of the process of non-volatile memory is well known to those skilled in the art and will not be described herein.

In the above embodiment, the etch stop layer 111 is formed between the conductor layer 110 and the conductor layer 114 as an example, and thus the doping polysilicon is performed twice. Deposition process. In another embodiment, the etch stop layer 111 is not formed between the conductor layer 110 and the conductor layer 114, and the conductor layer 110 and the conductor layer 114 can be regarded as a single film layer, as long as the doping process of the doped polysilicon is performed once.

In the above embodiment, three masks were used in comparison with the conventional logic circuit process. In another embodiment, the etch stop layer 111 is not formed between the conductor layer 110 and the conductor layer 114. Only two photomasks are used compared to the conventional logic circuit process.

In the above embodiment, the pitch between the gate and the floating gate is determined by the thickness of the spacer 122, so that the spacing between the gate and the floating gate can be further narrowed, and the accumulation of components can be improved.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100‧‧‧Base

102a, 102b, 102c‧‧‧ doped areas

104a‧‧‧Selecting the gate dielectric layer

104b‧‧‧Tunnel dielectric layer

110a, 110b‧‧‧ conductor layer

111, 111a, 111b‧‧‧ etch stop layer

112‧‧‧ openings

114‧‧‧Conductor layer

116‧‧‧Top cover

120a‧‧‧ Cover layer

ST‧‧‧Selected gate transistor

FT‧‧‧Floating gate transistor

Claims (14)

A method of fabricating a non-volatile memory, comprising: providing a substrate on which a dielectric layer, a first conductor layer, a second conductor layer, and a cap layer are sequentially formed; and the cap layer is patterned And the second conductor layer to form a stacked structure and expose the first conductor layer; forming a spacer on the sidewall of the stacked structure; forming a patterned pattern on the first conductor layer on one side of the stacked structure a mask layer; removing the spacer; and patterning the cap layer and the patterned mask layer as a mask, removing the first conductor layer to form a select gate and a floating gate pole. The method for manufacturing a non-volatile memory according to claim 1, wherein the step of forming the spacer on a sidewall of the stacked structure comprises: forming an insulating layer on the substrate; and performing an anisotropic The etching process removes part of the insulating layer. The method for manufacturing a non-volatile memory according to claim 1, wherein the material of the spacer comprises tantalum nitride. The method for manufacturing a non-volatile memory according to claim 1, wherein the material of the cap layer is selected from the group consisting of cerium oxide, cerium nitride, and combinations thereof. One. The method of manufacturing a non-volatile memory according to claim 1, wherein the step of forming a patterned mask layer on the first conductor layer on one side of the stacked structure comprises: the first conductor Forming a mask material layer on the layer; forming a patterned photoresist layer covering a portion of the stack structure and the mask material layer; using the patterned photoresist layer as a mask to remove a portion of the mask material layer; In addition to the patterned photoresist layer. The method of manufacturing a non-volatile memory according to claim 5, wherein the step of forming the mask material layer on the first conductor layer comprises performing a thermal oxidation process. A method of fabricating a non-volatile memory, comprising: providing a substrate on which a dielectric layer, a first conductor layer, and an etch stop layer are sequentially formed; and patterning the etch stop layer to form an opening; Forming a second conductor layer on the substrate, the second conductor layer filling the opening; forming a cap layer on the second conductor layer; patterning the cap layer, the second conductor layer, and the etching termination a layer to form a stacked structure and expose the first conductor layer, wherein the opening is located in the stacked structure; Forming a spacer on the sidewall of the stacked structure; forming a patterned mask layer on the first conductor layer on one side of the stacked structure; removing the spacer; and patterning the cap layer and pattern The mask layer is a mask, and a portion of the first conductor layer is removed to form a select gate and a floating gate. The method for producing a non-volatile memory according to claim 7, wherein the material of the etch stop layer is one selected from the group consisting of cerium oxide, cerium nitride, and a combination thereof. The method of manufacturing a non-volatile memory according to claim 7, wherein the step of forming the spacer on a sidewall of the stacked structure comprises: forming an insulating layer on the substrate; and performing an anisotropic The etching process removes part of the insulating layer. The method of manufacturing a non-volatile memory according to claim 7, wherein the material of the spacer comprises tantalum nitride. The method for producing a non-volatile memory according to claim 7, wherein the material of the cap layer is one selected from the group consisting of cerium oxide, cerium nitride, and a combination thereof. The method of manufacturing a non-volatile memory according to claim 7, wherein a patterned cover is formed on the first conductor layer on one side of the stacked structure. a step of forming a mask layer, comprising: forming a mask material layer on the first conductor layer; forming a patterned photoresist layer covering a portion of the stack structure and the mask material layer; using the patterned photoresist layer as a mask Removing a portion of the mask material layer; and removing the patterned photoresist layer. The method of manufacturing a non-volatile memory according to claim 12, wherein the step of forming the mask material layer on the first conductor layer comprises performing a thermal oxidation process. The method of manufacturing the non-volatile memory of claim 7, wherein the step of patterning the cap layer, the second conductor layer, and the etch stop layer comprises: patterning the cap The layer is a mask, a first etching process is performed, the second conductor layer is removed until the etch stop layer is exposed; and the second capping process is performed by patterning the cap layer as a mask, and removing the layer The termination layer is etched until the first conductor layer is exposed.