TWI570795B - Wafer level cutting method and system - Google Patents

Description

Wafer level cutting method and system Cross-reference to related applications

The present application claims priority to U.S. Provisional Patent Application Serial No. 61/444,618, filed on Jan. All of them are incorporated herein by reference.

The present invention is directed to methods and systems for wafer level cutting.

The semiconductor industry has developed techniques for cutting semiconductor integrated circuit dies. The die is then packaged for use in the product. In conventional processes, the wafer is attached to an adhesive tape and then cut with a saw, such as along scribe lines or saw streets between the effective die areas. The diced die attached to the tape then accepts a further packaging step.

Despite advances in die cutting technology, there is still a need in the art for improved wafer level cutting methods.

The present invention is generally related to semiconductor processing techniques. More specifically, the present invention encompasses methods and apparatus for performing wafer level dicing. By way of example only, the invention has been applied to laser cutting and stripping from carrier wafers (debonding) a method of cutting semiconductor crystal grains. The method and apparatus can be applied to a variety of semiconductor processing applications, including wafer level packaging.

In accordance with an embodiment of the present invention, a method of cutting a plurality of semiconductor dies is provided. The method includes providing a carrier substrate and bonding the semiconductor substrate to the carrier substrate. The semiconductor substrate includes a plurality of components. The method also includes forming a mask layer on the semiconductor substrate, exposing a predetermined portion of the mask layer, and processing the predetermined portion of the mask layer to form a predetermined mask pattern on the semiconductor substrate. The method further includes forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being combined with the predetermined reticle pattern and comprising one or more of the plurality of elements, and separating the plurality of plurality of elements from the carrier substrate Semiconductor die.

In accordance with another embodiment of the present invention, a system for cutting semiconductor dies is provided. The system includes: a coating unit that can be used to form a photomask layer on a semiconductor substrate including a plurality of components; a bonding unit that can be used to bond the semiconductor substrate to the carrier substrate; and a laser processing unit, A laser processing unit can be used to expose a predetermined portion of the photomask layer to the laser light. The system also includes a development processing unit operable to form a predetermined reticle pattern on the semiconductor substrate, and a dicing unit operable to form the plurality of semiconductor dies. Each of the plurality of semiconductor dies is combined with the predetermined reticle pattern and includes one or more of the plurality of elements. The system further includes a die separation unit that can be used to separate the plurality of semiconductor dies from the carrier substrate.

According to a particular embodiment of the invention, another cutting plurality is provided A method of semiconductor grains. The method includes: forming an inert film coupled to a surface of a component of a semiconductor substrate; removing a portion of the inert film located in the peripheral region; and forming an adhesive material coupled to a periphery of the surface of the component of the semiconductor substrate On the area. The method also includes bonding the semiconductor substrate to the carrier substrate and forming a plurality of semiconductor dies. The process of forming the plurality of semiconductor dies may include a reticle process, or may be performed using a reticle process, either or both of which may employ a laser dicing process. The method further includes separating the plurality of semiconductor dies from the carrier substrate.

A number of benefits over the prior art can be obtained using the method of the present invention. For example, in an embodiment in accordance with the present invention, a method and system for wafer level cutting is provided to reduce packaging costs. In some embodiments, the components can be tested at the wafer level and only the components that pass the test are removed during processing. One or more of these benefits may exist depending on the embodiment. These and other benefits are described in this specification and are described in more detail below. A variety of other objects, features, and advantages of the present invention will be more fully appreciated.

In accordance with the present invention, semiconductor processing techniques are provided. More specifically, the present invention encompasses a method and apparatus for performing wafer level dicing. By way of example only, the invention has been applied to laser cutting and stripping of semiconductor dies from a carrier wafer. The method and apparatus can be applied to a variety of semiconductor processing applications, including wafer level packaging.

In accordance with an embodiment of the invention, wafer bonding and lift-off techniques are used. A carrier substrate, also referred to as a carrier wafer, is provided as described below. In some implementations, a tantalum carrier substrate is used, although other suitable substrates characterized by mechanical rigidity and the ability to be processed at a suitable temperature can also be used. A semiconductor substrate, also referred to as an element wafer, is bonded to the carrier substrate.

In some wafer bonding processes, an adhesive is applied to one or more surfaces of the carrier substrate and/or the semiconductor substrate as part of the bonding process. A heat treatment process can also be performed. Therefore, a temporary bond is formed during the wafer bonding process. The thinning of the substrate can be performed by a chemical mechanical polishing (CMP) process or other suitable process to reduce the thickness of the semiconductor substrate. After thinning, the semiconductor substrate is typically attached to the tape, and the carrier substrate is removed using a wafer lift-off process, such as shearing the substrate, embedding a wedge at the land, or the like. Once attached to the tape, the semiconductor substrate can be cut and the die can then be selected for placement during packaging.

The inventors have determined that the use of tape brings several undesirable processing limitations. As an example, the use of tape does not allow some high temperature processing steps to be performed on the semiconductor substrate.

1A-1D is a schematic diagram showing a first process flow in accordance with an embodiment of the present invention. Referring to FIG. 1A, an inert film 110 is formed on the surface of the element of the semiconductor substrate 120. The inert film 110 can also be referred to as a molding material. Referring to FIG. 1A, the inert film 110 provides a film compatible with low temperature processing (eg, below 300 ° C, below 275 ° C, below 250 ° C, or the like) to protect the elements fabricated on the semiconductor substrate. Pieces 125a, 125b and 125c, and surfaces of the semiconductor substrate. The elements 125a, 125b, and 125c can be a wide variety of semiconductor components, including integrated circuits used to fabricate processors, memories, and the like. The term "inert" is used to mean that the film does not substantially react with the elements formed on the semiconductor substrate. Embodiments of the present invention use an inert film that is easily removed from the semiconductor substrate, as described more fully below.

The scope of the present invention encompasses inert films comprising spin-on films, spin-on carbon films, photoresists, oxide films that can be removed by wet chemical, solvent-soluble films such as Advanced Patterned Films (APF), advanced patterns The film can be deposited by plasma assisted chemical vapor deposition (PECVD) using the Applied Producer system. The APF films (eg, APF, APFe, APFx, or the like) use a removable (ie, plasma ashable) amorphous carbon hard mask that is suitable for critical The patterning step. A combination of materials can be used to form a composite inert structure having a plurality of layers comprised of the various materials described herein. As an example, an adhesive layer can be applied over the inert film 110 or below the inert film 110, which, as described above, can be a multilayer composite structure. A number of variations, adjustments, and alternatives can be identified by those skilled in the art.

The compatibility of the inert film 110 with low temperature processing allows the embodiments described herein to be suitable for use with a wide variety of semiconductor substrates containing active components because, for example, solder bumps on semiconductor substrates are above 250 °C. There is a tendency to reflow at temperature. Well-known artisans can recognize many changes Differences, adjustments and alternatives. Depending on the presence of components on the semiconductor substrate, the definition of low temperature processing may vary depending on the particular component structure and features.

Referring to FIG. 1B, an edge removal process is performed to remove the peripheral portion of the inert film 110 to provide a carrier substrate peripheral region 111 that is substantially free of the inert film 110. As an example, a processing unit containing an edge ball removal (EBR) arm can be provided at the corner of the processing unit. In this example, the EBR arm rotates about a pivot located at the proximal end of the EBR arm to position the distal end of the EBR arm above the edge of the semiconductor substrate mounted on the rotating chuck. The EBR flow system is dispensed via a nozzle located at the distal end of the EBR arm to remove the peripheral portion of the inert film 110. Other suitable techniques for removing the peripheral portion of the inert film 110 are also included in the scope of the present invention.

Referring to Figure 1C, an adhesive material 113 is applied to the semiconductor substrate to cover the inert film 110 of the illustrated embodiment. The adhesive material is then planarized to form an annulus 114 at the peripheral portion of the carrier substrate, as shown in Figure 1D. In addition to planarization, both the inert layer 110 and the ring 114 can be thinned during these processing steps. As described below, the semiconductor substrate can be bonded to the carrier substrate for further processing, such as thinning. Although the 1D diagram shows a planar structure, the present invention does not require such a planar structure. In some embodiments, a cavity extending toward the surface of the component (downward in FIG. 1D) may be formed within the inert film and/or the adhesive film.

In some embodiments, the inert film and/or the adhesive film is applied to the carrier substrate instead of the semiconductor substrate. Knowing the artisan Don't make a lot of variations, adjustments and alternatives.

In some embodiments, the adhesive material is applied to other predetermined portions of the semiconductor substrate instead of using an adhesive material ring. For example, at the edge of the wafer, there are typically partial dies or dummy dies that are generally circular in shape but generally rectangular in shape. The inert material can be removed at the location of the incomplete grains or dummy grains, and the adhesive material can be applied at these locations to provide an adhesive location splicing dispersed on the surface of the semiconductor substrate. As an example, a small amount of adhesive can be applied after applying a small amount of solvent. Alternatively, in the case of pre-wafer bonding processing combined with electrical testing, defective grains (i.e., non-yielding dies) can be identified and an adhesive can be applied to the grains. Continuing with this example, applying an adhesive to the non-productive die prevents these grains from being selected at a later processing stage, thereby simplifying the selection process and providing downstream downstream intelligence. Combinations of these techniques can also be used. A number of variations, adjustments, and alternatives can be identified by those skilled in the art.

2A-2F is a schematic diagram showing a second process flow in accordance with an embodiment of the present invention. The second process flow includes wafer bonding, laser cutting, and die removal processes provided by embodiments of the present invention. Referring to FIG. 2A, the semiconductor substrate 120 including the inert layer 110 and the ring 114 is disposed adjacent to the carrier substrate 100 having the bonding surface 105. In an embodiment, the carrier substrate comprises a germanium substrate. In other embodiments, the carrier substrate comprises a glass material to provide transparency in the visible spectrum, which is useful during some optical calibration processes.

As shown in FIG. 2B, a wafer bonding process is performed to bond the semiconductor substrate to the carrier substrate. The wafer bonding process can use one of several wafer bonding techniques. These techniques include low temperature bonding methods such as anode, eutectic, fusion, covalent, glass frit, and/or other bonding techniques. In an alternative embodiment, various techniques are used to perform the bonding of the two substrates. In a particular embodiment, the bonding is performed using a room temperature covalent bonding process. Each joint surface is cleaned and activated, for example, with plasma activation or with wet treatment. The activating surfaces are brought into contact with each other to promote adhesion. In some bonding processes, mechanical forces are provided on each of the substrate structures to press the bonding surfaces. In some embodiments, a chemical mechanical polishing (CMP) process is used to polish the bonding surface of one or more substrates to provide an extremely smooth surface that is conductive to the covalent bonding process. Of course, the skilled artisan can recognize many variations, adjustments, and alternatives. In some embodiments, a vent (eg, in the radial direction) through the annulus 114 is provided to provide venting to prevent air bubbles from creating within the engagement surface.

Referring to Figure 2C, the back side 124 of the semiconductor substrate is thinned by one or more processing steps to reduce the thickness of the substrate. Such processing steps can include CMP, grinding, etch back, any combination of these steps, and the like. In some implementations, an etch stop layer is integrated in the semiconductor substrate to assist in the termination of the thinning process. Plasma ashing and/or other cleaning processes can be performed as part of the thinning process. As shown in FIG. 2C, after thinning, the structure includes the carrier substrate 100, the inert layer 110 at the central portion of the structure, the annular adhesive layer 114, and the device. Thinned semiconductor substrate 120 of 125a/b/c. Other protective layers may be incorporated in addition to the exemplary layers discussed in this specification.

Embodiments of the invention use a laser cutting process. As shown in Fig. 2D, a mask layer 130 is formed on the surface of the semiconductor substrate, for example, a surface opposite to the surface of the element. The mask layer 130 can be a single layer or a multilayer structure containing one or more layers that can be used to protect the surface of the semiconductor substrate in which solder balls or other structures can be formed. In the illustrated embodiment, the laser reticle is formed directly on the surface of the crucible, but the present invention does not address this requirement, and other embodiments use a two-stage reticle layer, such as a polytheneamine/oxide combination. . Although the thinning of the semiconductor substrate is illustrated as occurring prior to dicing, other embodiments perform thinning after dicing or a combination of both.

Various suitable reticle materials are used in accordance with embodiments of the present invention, including polybenzamine materials, photopolymers, non-photopolymers, photoresists, combinations of the foregoing, or the like.

The etched reticle and the elements 125a/b/c are calibrated using backside alignment (ie, viewing the calibration marks on the surface of the semiconductor substrate element through the thinned substrate). The predetermined portion of the reticle layer is removed by laser lift-off, as shown in the space between regions 130a, 130b, 130c, 130d and 130e in Figure 2E. While FIG. 2E shows a cross-sectional view, it will be understood by those skilled in the art that in a typical application a two-dimensional pattern extending into the plane of the pattern will be formed. Laser lift-off of the photomask layer results in the formation of an etch mask having a predetermined pattern. In the illustrated embodiment, the mask layer, for example, polyamidamine and/or a thin protective layer, is used during the subsequent etching process as Hard reticle, as described below. Although a single layer is shown to represent the photomask layer 130, the present invention does not address this requirement, and a multilayer stack comprising, for example, polyamidoamine, an oxide, a photoresist, a combination of the above materials, or the like can be used. . Thus, one or more materials may provide a mask during laser stripping, while other materials may provide a mask during etching.

While laser lift-off is used in some embodiments, other embodiments use a lithography process in conjunction with laser lift-off, or a lithography process instead of laser lift-off. In one embodiment, the photomask layer is not used and a laser lift-off process is utilized that can perform the component cutting based on a Cartesian coordinate system. In yet another embodiment, the component cutting is performed using a mechanical separation process such as diamond cutting. Combinations of these techniques can be used as will be apparent to those skilled in the art. Therefore, various techniques including laser stripping without using a photomask, laser patterning/laser stripping/etching process of a mask, or mechanical scribing/cutting are included in the scope of the present invention.

An etching process is then used to remove the portion of the semiconductor substrate that is below the portion of the photomask layer that is removed by laser lift-off (ie, the scribe etch process), as shown in FIG. 2E. The etching process can include various material removal processes, including dry etching, reactive ion etching, wet etching, or the like. The etching process results in the dicing of the semiconductor dies. One advantage provided by the laser cutting process is the very small scribed channel. Depending on the presence of features on the surface of the component (such as, for example, metallization of the interconnect layer), an additional laser lift-off process can be used to complement the etch to strip a portion of the structures. Therefore, the etching process can be a multi-step process. A plurality of etching steps, laser stripping, combinations of the above steps, or the like are included. To provide protection of the sides of the grains, a liner can be placed over the trenches, for example, using a low temperature oxide film formation process. Metal sputtering and/or electroplating can then be performed depending on the particular application.

After dicing, the dies can be easily removed as shown in FIG. 2F, for example, using a vacuum assisted selection and setting tool to make contact with the back side of the semiconductor substrate because the inert film is The surface of the element of the semiconductor substrate has a low adhesion. As shown in FIG. 2E, since the adhesive material is in contact with the semiconductor substrate only at the peripheral region without the element structure, the adhesive material does not adhere the cut crystal grains to the carrier substrate. In some embodiments, surface interactions (e.g., van der Waals) between the element structures and the inert material provide sufficient adhesion to hold the dies in place prior to removal. In other embodiments, a soft adhesion promoter is deposited on the semiconductor substrate prior to depositing the inert layer 110 shown in FIG. In still other embodiments, a low temperature thermal process is used to reduce any residual adhesion associated with the inert layer while assisting the die removal process.

After dicing, the tool can be selected to select individual dies, such as a vacuum selection tool, and the residue can be removed from the front side of the component wafer using appropriate cleaning techniques (eg, to oxidize the plasma). After selection and/or cleaning, the dies may be placed on another carrier, placed on tape, flipped over another selection tool/tape, etc., or the like. Thus, embodiments of the present invention provide much greater flexibility than those available using conventional techniques.

Various selection tools are available, including vacuum workers with O-ring clamps An acyclic shoe that is suitable for a particular die, or the like. A pixelated electrostatic chuck can be used as a carrier, and the diced die can be placed on the carrier after selection to assist in the wafer level cleaning process. In addition, several types of carriers, die disks, a column of die disks, or the like can be used to accommodate individual die. Since the surface force of individual crystal grains is reduced as compared with the thinned wafer, there is usually no problem of grain curling, so that the arrangement of the crystal grains after the selection process is highly elastic. In some embodiments, the picking station is integrated with a die bonding tool. Alternatively, the cleaning process can be performed simultaneously on multiple dies after selection and setup.

In some embodiments, the protective layer can be applied prior to application of the inert film, depending on the particular component present on the die. As an example, if the components use copper pads with aluminum layers to support the silver-tin solder balls, these structures may be damaged during the selected plasma ash cleaning process. In order to protect these structures, a protective film may be formed before the formation of the inert layer 110 shown in Fig. 1A. After cleaning the inert film, the protective layer can be removed by a suitable cleaning process suitable for the protective layer. Exemplary protective layers include, for example, polymers, spin-on materials, other films, combinations of the above-described films, or the like. Therefore, although a single layer of the inert film 110 is formed on the semiconductor substrate in the embodiment shown in Fig. 1A, the present invention is not limited to this single layer, and a multilayer structure can be used depending on the specific application. In some embodiments in which solder balls or other structures extend from the surface of the substrate, a compliant layer can be formed such that one or more sides of the solder balls or other structures are surrounded by the compliant layer.

Some embodiments in which the inert material is characterized by a high degree of adhesion A thermal process can be used on a glass carrier substrate in which light in the visible spectrum (eg, from a lamp) is illuminated through the carrier wafer in a predetermined pattern to locally heat the inert material thereby facilitating die removal. Thus, some embodiments may use an adhesive layer that covers the entire semiconductor substrate to eliminate the use of an inert film. In other embodiments, the concept is adjusted to use a substantially transparent substrate at other wavelengths to emit light sources of the other wavelengths (eg, germanium substrates and infrared light). In these embodiments, the adhesive material is treated to absorb at a suitable wavelength, while the component features are not absorbed at this appropriate wavelength. Therefore, the adhesive material can be heat treated to reduce the adhesion and the solder balls are no longer reflowed. A number of variations, adjustments, and alternatives can be identified by those skilled in the art.

Figure 3 is a plan view of a semiconductor substrate 120 during dicing in accordance with an embodiment of the present invention. As shown in FIG. 3, several of the dies disposed at locations 310, 312, and 314 have been cut and removed while a plurality of dies 320-330 are still attached to the semiconductor substrate 120.

Figure 4 is a simplified flow diagram showing a method of cutting a plurality of semiconductor dies in accordance with an embodiment of the present invention. The method 400 includes providing a carrier substrate (410) and bonding the semiconductor substrate to the carrier substrate (412). The semiconductor substrate includes a plurality of components. In one embodiment, the carrier substrate contains a germanium substrate, although other substrates may be used, including a glass substrate. As described above, bonding the semiconductor substrate to the carrier substrate, in some embodiments, comprising forming a thin film on the semiconductor substrate, such as an inert film (eg, an amorphous carbon film), the film being substantially not on the semiconductor substrate Component response. In an embodiment, the edge portion of the film is removed, And forming an adhesive layer coupled to the semiconductor substrate. As an example, the adhesive layer can be formed as an annular layer surrounding the film. The carrier substrate, the film, and the adhesive layer are brought into contact to join the two substrates. The film may be a single layer of a single material or a composite structure comprising a plurality of materials including adhesion promoters, protective layers, and the like.

In one embodiment, a photosensitive material is used as the composite adhesive/inert material. As an example, a material that becomes tacky after exposure can be applied, and a peripheral or other portion of the material can be exposed, creating an adhesive ring or pattern in the material. Unexposed materials may be characterized by low adhesion, providing functionality associated with the inert materials described herein. In an alternate embodiment, a complementary material is used in which exposure results in a decrease in the adhesion of the material and the lack of exposure is related to the degree of adhesion. A number of variations, adjustments, and alternatives can be identified by those skilled in the art. In addition to the ring structure, the photosensitive material can be exposed by a Kelvin coordinate system to provide an adhesive material in relation to one or more of the grains, for example, which are screened and determined to be unstable grains.

In an alternative embodiment, bonding the semiconductor substrate to the carrier substrate comprises forming an inert film on the semiconductor substrate, and removing a portion of the inert film associated with a predetermined pattern, the predetermined pattern being associated with one or more of the plurality of elements Multiple combinations. As an example, if some testing is performed on the die and it is determined that the particular die does not have a full function, the adhesive can be applied adjacent to the non-functional die to prevent the die from being separated during the laser process.

The method also includes forming a photomask layer (414) on the semiconductor substrate, exposing A predetermined portion (416) of the mask layer is lighted, and a predetermined portion of the mask layer is processed to form a predetermined mask pattern (418) on the semiconductor substrate. As an example, forming the predetermined reticle pattern can include developing a predetermined portion of the reticle layer and etching a predetermined portion of the reticle layer to expose a surface of the semiconductor substrate. As shown in FIG. 2E, the portion of the semiconductor substrate that is below the open area of the mask layer can be etched all the way through the semiconductor substrate to touch the film/adhesive layer or the carrier substrate.

The method further includes forming the plurality of semiconductor dies (420) and separating the plurality of semiconductor dies (422) from the carrier substrate. Each of the plurality of semiconductor dies is associated with the predetermined reticle pattern and includes one or more of the plurality of elements. In some embodiments, the plurality of semiconductor dies can be cleaned using one of a plurality of processes after the dies are separated. The crystal grains may be selected from the carrier substrate one at a time, or a device (tissue separation) capable of simultaneously selecting a plurality of crystal grains may be used. In some embodiments in which multiple dies are selected simultaneously, the vacuum of each of the selected elements can be independently controlled to avoid picking grains that have been determined to be unstable or not selected due to other factors. As an example, the die separation tool can be programmed to select a predetermined die and leave the remaining die attached to the carrier substrate.

It will be understood that the specific steps illustrated in Figure 4 provide a particular method of cutting a plurality of semiconductor dies in accordance with an embodiment of the present invention. Other sequences of steps may also be performed in accordance with alternative embodiments. For example, alternative embodiments of the invention may perform the steps outlined above in a different order. Furthermore, the individual steps shown in FIG. 4 may include a plurality of sub-steps that may be performed in various orders depending on the individual step suitability. Also, it can be added depending on the specific application Or remove extra steps. A number of variations, adjustments, and alternatives can be identified by those skilled in the art.

Figure 5 is a schematic diagram of a system for cutting a plurality of semiconductor dies in accordance with one embodiment of the present invention. The system 500 includes control elements such as an input/output interface 510, a processor 512 (also referred to as a data processor), and a computer readable medium 514, such as a memory. The processor 512 and the memory 514 interact with the input/output interface to provide user control of the various units described herein. The processor 512 represents a central processing unit of any architecture type, such as CISC (Complex Instruction Set Operation), RISC (Reduced Instruction Set Operation), VLIW (Very Long Instruction Set) or hybrid architecture, although any suitable processor may be used. The processor 512 executes the instructions and includes portions of the computer that control the operation of the entire computer. Although not shown in FIG. 5, the processor 512 typically includes a control unit that organizes data and programs in the memory to store and transfer data and other information between various components of the computer. The processor 512 receives input data from the input/output interface 510 and/or network (not shown), then reads and stores the code and data in the computer readable medium 514, and submits the data to the input. / Output interface 510. Although Figure 5 illustrates a single processor, the disclosed embodiments are also applicable to computers that may have multiple processors, and may have multiple bus bars, and some or all of the bus bars perform different functions in different ways. on the computer.

The computer readable medium 514 represents one or more stored data mechanisms. For example, the computer readable medium 514 can include read only memory (ROM), random access memory (RAM), disk storage media, optical storage media, Flash memory components and/or other mechanically readable media. In other embodiments, any suitable type of storage element can be used. Although only one computer readable medium 514 is shown, there may be multiple computer readable media and multiple types of storage elements. Moreover, although the computer readable medium 514 is illustrated as being coupled to the processor 512, it can be distributed to other computers, such as on a server.

The computer readable medium 514 includes a controller (not shown in Figure 5) and data items. The controller includes instructions that can be executed on the processor 512 to carry out the methods more fully described in this specification. In another embodiment, some or all of the functionality is implemented by replacing the hardware of the processor-based system. In one embodiment, the controller is a web browser, but in other embodiments, the controller can be a database system, a file system, an email system, a media manager, an image manager, or can include Access any other features of the data item. Of course, the computer readable medium 514 may also contain other software and materials (not shown), which is not necessary to understand the present invention.

The system further includes a coating unit 520 that can be used to form a photomask layer on a semiconductor substrate having a plurality of components, and a bonding unit 530 that can be used to bond the semiconductor substrate to the carrier substrate. The coating unit can be utilized to form the various coatings described herein. The processing and developing unit 540 includes one or more subunits including: a laser processing unit 542, the laser processing unit 542 can be used to expose a predetermined portion of the mask layer under laser light; and the development processing unit 544 a development processing unit 544 can be used to shape the semiconductor substrate Forming a predetermined mask pattern; and a cutting unit 546, the cutting unit 546 can be used to form a plurality of semiconductor dies. The cutting unit 546 can include a developing unit and an etching unit. Although these subunits are illustrated as being incorporated within the processing and developing unit 540 in the embodiment illustrated in Figure 5, the present invention does not address this requirement and these subunits may be separate units. The laser processing unit 542 can include a laser source or be optically coupled to an external laser source, such as through a fiber optic cable.

According to some embodiments, system 500 includes a die separation unit 550 and a cleaning unit 560. The plurality of semiconductor dies may be separated from the carrier substrate by the die separation unit 550.

Figure 6 is a simplified flow diagram showing a method of cutting a plurality of semiconductor dies in accordance with another embodiment of the present invention. Referring to Figure 6, the method includes providing a semiconductor substrate having a plurality of components formed thereon and forming an inert material (610) coupled to the surface of the semiconductor substrate component. The inert material may be formed in contact with an adhesive layer formed on the semiconductor substrate. In some embodiments, the inert film covers the entire semiconductor substrate, while in other embodiments, portions of the semiconductor substrate do not have the inert film. As discussed above, the inert material can be a variety of materials that provide a film that is compatible with the low temperature process and that does not substantially react with the elements formed on the semiconductor substrate. By way of example only, the inert film, which may be a multilayer composite structure, may be APF deposited by PECVD, however such inert films are not limited by this example.

The method also includes removing a peripheral portion (612) of the inert film, in a In some embodiments, this exposes a peripheral portion of the semiconductor substrate. In some embodiments, the inert film within the peripheral region is completely removed, while in other embodiments, a portion of the inert film continues to be coupled within the peripheral region of the semiconductor substrate. A number of variations, adjustments, and alternatives can be identified by those skilled in the art. As discussed above, the EBR process can be used to remove the peripheral portion of the inert film.

The method further includes forming an adhesive material (614) coupled to the surface of the semiconductor substrate component. The adhesive material can be applied directly to the exposed area of the semiconductor substrate, to the adhesion promoting layer, or the like. In some embodiments, the upper surface of the adhesive material is coplanar with the upper surface of the inert material to provide a high quality wafer bonding surface for subsequent wafer bonding processes.

The semiconductor substrate is bonded to the carrier substrate (616) using a substrate or wafer bonding process. As shown in Figures 2A/2B, the inert material/adhesive material layer can be bonded to the bonding surface of the carrier substrate to form a compound semiconductor structure. In some embodiments, a portion of the semiconductor substrate (the back side of the substrate) is removed using a wafer thinning process, such as CMP, to reduce the thickness of the semiconductor substrate depending on device operational suitability. In some embodiments a reticle-based dicing process is used, the reticle layer being formed and processed (eg, on the surface of the semiconductor substrate opposite the surface of the component) to form a predetermined reticle pattern on the semiconductor substrate, such as By exposing a predetermined portion of the photomask layer. In these reticle-based cutting embodiments, the method includes processing a predetermined portion of the reticle layer to form a predetermined reticle pattern on the semiconductor substrate. As an example, forming the predetermined mask pattern may include A predetermined portion of the photomask layer is developed and a predetermined portion of the photomask layer is etched to expose a surface of the semiconductor substrate. As shown in FIG. 2E, the portion of the semiconductor substrate located below the open area of the mask layer can be etched all the way through the semiconductor substrate to touch the film/adhesive layer or the carrier substrate.

Referring to Figure 6, the method additionally includes forming a plurality of semiconductor dies (618) and separating the plurality of semiconductor dies (620) from the carrier substrate. According to some embodiments, the grains are cut as described above using a laser cutting method. Each of the plurality of semiconductor dies typically contains one or more of the plurality of elements. In some embodiments, the plurality of semiconductor dies can be cleaned using one of a plurality of processes after the dies are separated. The crystal grains may be selected from the carrier substrate one at a time, or a device (tissue separation) capable of simultaneously selecting a plurality of crystal grains may be used. In some embodiments in which multiple dies are selected simultaneously, the vacuum of each of the selected elements can be independently controlled to avoid picking grains that have been determined to be unstable or not selected due to other factors. As an example, the die separation tool can be programmed to select a predetermined die and leave the remaining die attached to the carrier substrate.

It will be appreciated that the specific steps illustrated in Figure 6 provide a particular method of cutting a plurality of semiconductor dies in accordance with an embodiment of the present invention. Other sequences of steps may also be performed in accordance with alternative embodiments. For example, alternative embodiments of the invention may perform the steps outlined above in a different order. Moreover, the individual steps illustrated in FIG. 6 may include a plurality of sub-steps that may be performed in various orders depending on the individual step suitability. In addition, additional steps may be added or removed depending on the particular application. A number of variations, adjustments, and alternatives can be identified by those skilled in the art.

It is also understood that the examples and embodiments described herein are for illustrative purposes only, and that various modifications and changes may be derived from the skilled artisan and are included in the spirit and scope of the application and the appended claims. Within the scope of the field.

100‧‧‧ Carrier substrate

105‧‧‧ joint surface

110‧‧‧film

111‧‧‧The peripheral part of the carrier substrate

113‧‧‧Adhesive materials

114‧‧‧rings

120‧‧‧Semiconductor substrate

124‧‧‧Back side of semiconductor substrate

125a, 125b, 125c‧‧‧ components

130‧‧‧mask layer

130a, 130b, 130c, 130d, 130e‧‧‧ areas

310, 312, 314, 320-330‧‧‧ position

410‧‧‧Steps

412‧‧‧Steps

414‧‧‧Steps

416‧‧‧Steps

418‧‧‧Steps

420‧‧ steps

422‧‧‧Steps

500‧‧‧ system

510‧‧‧Input/Output Interface

512‧‧‧ processor

514‧‧‧Computer readable media

520‧‧‧ Coating unit

530‧‧‧joining unit

540‧‧‧Processing and developing unit

542‧‧‧Laser processing unit

544‧‧‧Development Processing Unit

546‧‧‧Cutting unit

550‧‧‧Crystal separation unit

560‧‧‧ cleaning unit

610‧‧‧Steps

612‧‧ steps

614‧‧‧Steps

616‧‧‧Steps

618‧‧ steps

620‧‧‧Steps

1A-1D is a schematic diagram showing a first process flow according to an embodiment of the present invention; and 2A-2F is a schematic diagram showing a second process flow according to an embodiment of the present invention; 1 is a plan view of a semiconductor substrate during dicing according to an embodiment of the present invention; FIG. 4 is a schematic flow chart showing a method of dicing a plurality of semiconductor dies according to an embodiment of the present invention; A schematic diagram of a system for cutting a plurality of semiconductor dies in one embodiment; and a schematic flow diagram of FIG. 6 showing a method of dicing a plurality of semiconductor dies in accordance with another embodiment of the present invention.

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Claims (9)

A method of cutting a plurality of semiconductor dies, the method comprising the steps of: providing a carrier substrate; forming a thin film on a semiconductor substrate, the semiconductor substrate comprising a plurality of components; removing a portion of the thin film to expose the semiconductor a predetermined portion of the substrate, the predetermined portion including an edge portion and one or more central portions in combination with the defective member; the predetermined portions are coated with an adhesive material, the adhesive material being coupled to the semiconductor substrate; bonding the semiconductor Substrate to the carrier substrate; forming a photomask layer on the semiconductor substrate; exposing a predetermined portion of the photomask layer; processing the predetermined portion of the photomask layer to form a predetermined mask pattern on the semiconductor substrate; Forming the plurality of semiconductor dies, each of the plurality of semiconductor dies being combined with the predetermined reticle pattern and comprising one or more of the plurality of elements; and separating the plurality of semiconductor dies from the carrier substrate. The method of claim 1, wherein the carrier substrate comprises a substrate. The method of claim 1, wherein the step of joining the semiconductor substrate to the carrier substrate comprises the step of making a contact between the carrier substrate, the film, and the adhesive material disposed on the predetermined portions. The method of claim 3, wherein the adhesive layer comprises an annular layer surrounding the film. The method of claim 3, wherein the film comprises an inert material. The method of claim 5, wherein the inert material comprises an amorphous carbon material. The method of claim 1, wherein the step of forming the predetermined mask pattern comprises the steps of: directing a laser beam to illuminate the predetermined portion of the mask layer; and etching the predetermined portion of the mask layer to expose the semiconductor a surface of the substrate. The method of claim 7, wherein the step of forming the plurality of semiconductor dies comprises the step of etching at least a portion of the semiconductor substrate to form the plurality of semiconductor dies. The method of claim 1, the method further comprising the step of cleaning the plurality of semiconductor dies.