TWI570683B - Display apparatus - Google Patents

Description

Display device

The present invention relates to the display device, and more particularly to the shape design of the circuit region of its peripheral region.

A general display device has a rectangular shape and is mainly divided into a peripheral area of a display area and a periphery. The peripheral area contains a plurality of rectangular circuit areas for driving pixels in the display area. However, in other types of display devices, the space between the rectangular circuit region and the substrate edge of the peripheral region is too large to be properly utilized. In general, the larger the area of the circuit area, the greater the flexibility in circuit design. In order to reduce the space between the circuit area and the edge of the substrate, the existing circuit area design is often irregular, and has different shapes depending on the position, so that the circuit design of one circuit area cannot be applied to other circuit areas.

In summary, there is a need for a new circuit area shape to reduce the space between the circuit area and the edge of the substrate, and the shape of the circuit area should be applicable to any position in the peripheral area.

A display device according to an embodiment of the present invention includes: a display area having a plurality of pixels on a substrate; and a peripheral area located outside the display area, the peripheral area including a plurality of first circuit areas and a plurality of In the two circuit area, the first circuit area drives the pixels in the first direction, and the second circuit area drives the picture in the second direction Wherein at least one of the first circuit region and the second circuit region is a pentagon having a first side, a second side, a third side, a fourth side, and a fifth side sequentially connected, wherein the first The sides are parallel to the second direction, wherein the second side is parallel to the first direction, wherein the third side is parallel to the diagonal of one of the pixels, wherein the fourth side is substantially parallel to the edge of the substrate corresponding to the pentagon, and The length of the fourth side is greater than the length of at least one of the sides of the pixel, and wherein the fifth side is parallel to the third side.

A display device according to an embodiment of the present invention includes: a display area having a plurality of pixels on a substrate; and a peripheral area located outside the display area, the peripheral area including a plurality of first circuit areas and a plurality of In the two circuit area, the first circuit area drives the pixels in the first direction, and the second circuit area drives the pixels in the second direction; wherein at least one of the first circuit area and the second circuit area is a heptagon, with sequential a first side, a second side, a third side, a fourth side, a fifth side, a sixth side, and a seventh side, wherein the first side is parallel to the second direction, wherein the second side is parallel to the first direction The fourth edge is substantially parallel to the edge of the substrate corresponding to the heptagon, and the length of the fourth side is greater than the length of at least one of the sides of the pixel, wherein the sixth side is parallel to the first side, and wherein the seventh side The sides are parallel to the second side.

CLR, CLG, CLB‧‧‧ timing signal lines

D‧‧‧ data line

Mn1, Mn2, Mn3, Mn4, Mn10, Mn11, Mn12, Mn13, Mn14‧‧‧ transistors

P‧‧‧ side

S‧‧‧ scan line

VH, VL‧‧‧ power supply line

V-1, VI-1, VII-1‧‧‧ first side

V-2, VI-2, VII-2‧‧‧ second side

V-3, VI-3, VII-3‧‧‧ third side

V-4, VI-4, VII-4‧‧‧ fourth side

V-5, VI-5, VII-5‧‧‧ fifth side

VI-6, VII-6‧‧‧ sixth side

VII-7‧‧‧ seventh side

10‧‧‧Substrate

11‧‧‧ display area

11A‧‧‧First direction

11B‧‧‧second direction

11C‧‧‧ diagonal

13‧‧‧The surrounding area

13E‧‧‧ substrate edge

15‧‧‧ wiring

100‧‧‧ display device

110‧‧‧ pixels

131‧‧‧First Circuit Area

133‧‧‧Second circuit area

Figure 1 is a schematic view of a display device in an embodiment of the present invention.

2 and 3 are diagrams showing the distribution of the first circuit area and the second circuit area in the embodiment of the present invention.

4 to 9 are views showing the shapes of the first circuit region and the second circuit region in the embodiment of the present invention.

10A to 10D are diagrams showing a first circuit area and a second circuit area in an embodiment of the present invention Layout diagram.

Figure 11 is a circuit diagram of a shift register in an embodiment of the present invention.

Figure 12 is a circuit diagram of a multiplex controller in an embodiment of the present invention.

Figure 1 is a schematic view of a display device of the present invention. The display device 100 has a circular substrate edge and is mainly divided into a display area 11 and a peripheral area 13. The display area 11 has a pixel 110 on the substrate 10. In the embodiment of Fig. 1, the pixels 110 are square and the first direction 11A is perpendicular to the second direction 11B. In other embodiments, the pixels may be hexagonal, and the angle between the first direction 11A and the second direction 11B is 60 degrees.

The peripheral region 13 of FIG. 1 has a plurality of first circuit regions 131 and second circuit regions 133 on the substrate 10. The first circuit region 131 drives the pixels 110 in the first direction 11A, and the second circuit region 133 drives the pixels 110 in the second direction 11B. For example, the first circuit region 131 can be a shift register (SR), and the single first circuit region 131 drives only a single column of pixels 110 (and connected to its scan line S). The second circuit region 133 can be a switch of a multiplex controller (MUX switch), and a single second circuit region 133 drives at least one row of pixels 110 (and connected to its data line D).

The first circuit region 131 and the second circuit region 133 included in the peripheral region 13 of Fig. 1 can be as shown in Fig. 2 or Fig. 3. In Fig. 2, a portion of the peripheral region 13 is provided with a first circuit region 131 and a second circuit 133 region. In Fig. 3, a portion of the peripheral region 13 is provided with only the first circuit region 131 and a portion of the peripheral region 13 where only the second circuit region 133 is provided.

Fig. 4 is an enlarged view of a region 200 of Fig. 1 for explaining the shape of the first circuit region 131 and the second circuit region 133 in the design of Fig. 3. It can be understood that although the lower left corner of FIG. 3 is the second circuit region 133, the shape of the second circuit region 133 The design can also be applied to the first circuit area 131 in the lower right corner.

As shown in Fig. 4, each pixel 110 has three sub-pixels (R, G, and B). It can be understood that the pixel 110 can have more sub-pixels and is not limited to the design of the common three sub-pixels, and the arrangement and area of the three sub-pixels can also be adjusted as needed. In Fig. 4, the second circuit region 133 is a pentagon. Taking the second circuit region 133 in the middle as an example, the pentagon has a first side V-1, a second side V-2, a third side V-3, a fourth side V-4, and a fifth. Side V-5. The first side V-1 is parallel to the second direction 11B, the second side V-2 is parallel to the first direction 11A, and the third side V-3 is parallel to the diagonal 11C of the pixel 110. The fourth side V-4 is substantially parallel to the substrate edge 13E of the peripheral region 13 corresponding to the pentagon, and the fourth side V-4 is larger than at least one of the side edges P of the pixel 110. For example, the fourth side V-4 is larger than the right side, the left side, the upper side, or the lower side of the pixel 110. The fifth side V-5 is parallel to the third side V-3. In an embodiment of the invention, a wiring 15 may be sandwiched between the second circuit region 133 and the substrate edge 13E to connect the different second circuit regions 133 to the external circuit. As in the embodiment shown in FIG. 4, the first side V-1 is opposite to the side of one of the outermost pixels 110 in the display area 11 (as the left side of the pixel 110 on the right side of the second circuit area 133). Adjacent, and the second side V-2 is adjacent to the side of the other of the outermost pixels 110 in the display area 11 (such as the lower side of the pixel 110 above the second circuit area 133).

In Fig. 4, the third side V-3 is the same length as the fifth side V-5. However, in other embodiments, the lengths of the third side V-3 and the fifth side V-5 may be different, such that the fourth side V-4 is substantially parallel to the substrate edge 13E at different positions, as shown in FIG. Similarly, the lengths of the first side V-1 and the second side V-2 are not necessarily the same, and the length depends on the number of corresponding pixels. In any event, the fourth side V-4 is substantially parallel to the substrate edge 13E. It must be noted here that although the giant substrate upper edge 13E is circular, However, at a microscopic scale, the substrate edge 13E corresponding to the second circuit region 133 can be regarded as a straight line.

Fig. 6 is an enlarged view of a region 200 of Fig. 1 for illustrating that the peripheral regions 13 of the portion of the design of Fig. 2 are provided with the shapes of the first circuit region 131 and the second circuit region 133 (lower half). As for the peripheral portion 13 of the portion in Fig. 2, only the first circuit region 131 (upper half) is provided, and the aforementioned pentagon design can be employed. It can be understood that although the design of FIG. 6 corresponds to the peripheral area 13 of the lower left corner, the first circuit area 131 and the second circuit area 133 are disposed, but the peripheral area 13 of the lower right corner portion can also be applied. The first circuit region 131 and the second circuit region 133 are disposed. In other embodiments, a portion of the peripheral region 13 is provided with the first circuit region 131 and the second circuit region 133 may be located in other regions than the lower half of the peripheral region 13, but the design of FIG. 6 is applicable.

In FIG. 6, the second circuit region 133 is located between the first circuit region 131 and the display region 11. The first circuit region 131 of the pentagon has a first side V-1, a second side V-2, a third side V-3, a fourth side V-4, and a fifth side V-5 which are sequentially connected. The first side V-1 is parallel to the second direction 11B, the second side V-2 is parallel to the first direction 11A, and the third side V-3 is parallel to the diagonal 11C of the pixel 110. The fourth side V-4 is substantially parallel to the substrate edge 13E of the peripheral region 13 corresponding to the pentagon, and the fourth side V-4 is larger than at least one of the side edges P of the pixel 110. For example, the fourth side V-4 is larger than the right side, the left side, the upper side, or the lower side of the pixel 110. The fifth side V-5 is parallel to the third side V-3. In an embodiment of the invention, a wiring 15 may be interposed between the first circuit region 131 and the substrate edge 13E to connect different first circuit regions 131 to external circuits.

As shown in FIG. 6, the hexagonal second circuit region 133 has a first side VI-1, a second side VI-2, a third side VI-3, and a fourth side VI-4, which are sequentially connected. Five sides VI-5, and the sixth side VI-6. The first side VI-1 is parallel to the second direction 11B, and The side of one of the outermost pixels 110 in the display area 11 (as the left side of the pixel 110 to the right of the second circuit area 133) is adjacent. The second side VI-2 is parallel to the first direction 11A and is adjacent to the side of the other of the outermost pixels in the display area 11 (e.g., the lower side of the pixel 110 above the second circuit area 133). The third side VI-3 is parallel to the diagonal 11C of one of the pixels 110. The fourth side VI-4 is parallel to the first side VI-1 and is adjacent to the first side V-1 of the first circuit area 131 of the left side of the pentagon. The fifth side VI-5 is parallel to the second side VI-2 and is adjacent to the second side V-2 of the first circuit area 131 of the lower pentagon. The sixth side VI-6 is parallel to the third side VI-3.

Fig. 7 is an enlarged view of a region 200 of Fig. 1 for explaining the shapes of the first circuit region 131 and the second circuit region 133 in the design of Fig. 3. It can be understood that although the lower left corner of FIG. 7 is the second circuit region 133, the shape design of the second circuit region 133 can also be applied to the first circuit region 131 in the lower right corner.

As shown in FIG. 7, the second circuit region 133 is a heptagon having a first side VII-1, a second side VII-2, a third side VII-3, and a fourth side VII-4 connected in sequence. The fifth side VII-5, the sixth side VII-6, and the seventh side VII-7. The first side VII-1 is parallel to the second direction 11B and is adjacent to the first side of the first one of the outermost pixels 110 in the display area 11 (as the left side of the pixel 110 in the middle of FIG. 7) . The second side VII-2 is parallel to the first direction 11A and is adjacent to the side of the second one of the outermost pixels 110 in the display area 11 (as the lower side of the pixel 110 above in Fig. 7). The fourth side VII-4 is substantially parallel to the substrate edge 13E of the peripheral region 13 corresponding to the heptagon, and the fourth side VII-4 is larger than at least one of the side edges P of the pixel 110. For example, the length of the fourth side VII-4 is greater than the upper side, the lower side, the left side, or the right side of the pixel 110. The sixth side VII-6 is parallel to the first side VII-1 and is adjacent to the side of the third party of the outermost pixel 110 in the display area 11 (as the left side of the pixel below in Fig. 7). The seventh side VII-7 and the second side VII-2 is parallel and adjacent to the second side of the first one of the outermost pixels 110 in the display area 11 (as the lower side of the pixel 110 in the middle of Fig. 7). In an embodiment of the invention, a wiring 15 may be sandwiched between the second circuit region 133 and the substrate edge 13E to connect the different second circuit regions 133 to the external circuit.

In Fig. 7, the lengths of the third side VII-3 and the fifth side VII-5 may be adjusted such that the fourth side VII-4 is substantially parallel to the substrate edge 13E at different positions, as shown in Fig. 8. Similarly, the lengths of the first side VII-1, the second side VII-2, the sixth side VII-6, and the seventh side VII-7 are not necessarily the same, depending on the number of corresponding pixels. In any event, the fourth side VII-4 is substantially parallel to the substrate edge 13E. It must be noted here that although the giant substrate edge 13E is circular, the substrate edge 13E corresponding to the second circuit region 133 may be regarded as a straight line when microscopically, for example, the pixel size.

Fig. 9 is an enlarged view of a region 200 of Fig. 1 for illustrating that the peripheral portion 13 of the design of Fig. 2 is provided with the shapes of the first circuit region 131 and the second circuit region 133 (lower half). As for the peripheral portion 13 of the portion in Fig. 9, only the first circuit region (upper half) is provided, and the aforementioned pentagon design can be employed. It can be understood that although the design of FIG. 9 corresponds to the peripheral portion 13 of the lower left corner, the first circuit region 131 and the second circuit region 133 are disposed, but the peripheral region 13 of the lower right corner portion can also be applied. The first circuit region 131 and the second circuit region 133 are disposed. In other embodiments, a portion of the peripheral region 13 is provided with the first circuit region 131 and the second circuit region 133 may be located in other regions than the lower half of the peripheral region 13, but the design of FIG. 9 is applicable.

In FIG. 9, the second circuit region 133 is located between the first circuit region 131 and the display region 11. The first circuit region 131 of the heptagon has a first side VII-1, a second side VII-2, a third side VII-3, a fourth side VII-4, and a fifth side VII-5, which are sequentially connected. Six sides VII-6, and the seventh side VII-7. The first side VII-1 is parallel to the second direction 11B. The second side VII-2 is parallel to the first direction 11A. The fourth side VII-4 is substantially parallel to the substrate edge 13E of the peripheral region 13 corresponding to the heptagon, and the fourth side VII-4 is larger than at least one of the side edges P of the pixel 110. For example, the length of the fourth side VII-4 is greater than the upper side, the lower side, the left side, or the right side of the pixel 110. The sixth side VII-6 is parallel to the first side VII-1. The seventh side VII-7 is parallel to the second side VII-2. In an embodiment of the invention, a wiring 15 may be interposed between the first circuit region 131 and the substrate edge 13E to connect different first circuit regions 131 to external circuits.

As shown in FIG. 9, the hexagonal second circuit region 133 has a first side VI-1, a second side VI-2, a third side VI-3, and a fourth side VI-4, which are sequentially connected. Five sides VI-5, and the sixth side VI-6. The first side VI-1 is parallel to the second direction 11B and is adjacent to the side of one of the outermost pixels 110 in the display area 11 (such as the left side of the pixel 110 to the right of the second circuit area 133). The second side VI-2 is parallel to the first direction 11A and is adjacent to the side of the other of the outermost pixels in the display area 11 (e.g., the lower side of the pixel 110 above the second circuit area 133). The third side VI-3 is parallel to the diagonal 11C of one of the pixels 110. The fourth side VI-4 is parallel to the first side VI-1 and adjacent to the first side VII-1 of the first circuit region 131 of the heptagon. The fifth side VI-5 is parallel to the second side VI-2 and is adjacent to the seventh side VII-7 of the first circuit region 131 of the heptagon. The sixth side VI-6 is parallel to the third side VI-3.

In an embodiment of the present invention, the layout of the first circuit region 131 of the pentagon (such as the design of FIG. 4 or FIG. 5) is as shown in FIG. 10A, which is a plurality of shifts corresponding to driving the plurality of scan lines S. The bit register, one of the shift registers includes power supply lines VH and VL, the power supply lines VH and VL are adjacent to the fourth side V-4 of the pentagon, and the substrate edge corresponding to the pentagon 13E is substantially parallel. The circuit diagram of the above shift register is shown in Fig. 11. In general, the shift register has four transistors Mn1, Mn2. Mn3, and Mn4, drive the gates in a single column of pixels 110.

In an embodiment of the present invention, the layout pattern of the pentagonized second circuit region 133 (such as the design of FIG. 4 or FIG. 5) is as shown in FIG. 10B, which is a plurality of multiplexes corresponding to driving a plurality of data lines. Controller. One of the multiplex controllers includes timing signal lines CLR, CLG, and CLB adjacent to the fourth side V-4 of the pentagon, and the substrate edge 13E corresponding to the pentagon is substantially parallel. The circuit diagram of the above multiplex controller is shown in Fig. 12. In general, the three transistors Mn10, Mn11, and Mn12 of the multiplex controller can respectively switch the data lines of the RGB sub-pixels in the pixel 110 of a single row at different time phases. If the pixel 110 has more pixels (such as RGBY), then the number of transistors is more (such as 4). On the other hand, the transistors Mn13 and Mn14 of the multiplex controller are protection circuits for electrostatic discharge.

In an embodiment of the invention, the first circuit region 131 is a pentagon, and the second circuit region 133 is hexagonal, and the second circuit region 133 is sandwiched between the first circuit region 131 and the pixel 110 ( As designed in Figure 6). The first circuit area 131 is a shift register, and its layout can be referred to FIG. 10A. The second circuit area 133 is a plurality of multiplex controllers corresponding to driving a plurality of data lines, and the layout thereof is as shown in FIG. 10C. One of the multiplex controllers includes a power supply line VL, and the power supply line VL is adjacent to the fifth side VI-5 of the hexagon. The circuit diagram of the above multiplex controller is shown in Fig. 12.

In an embodiment of the present invention, the first circuit region 131 of the heptagon (such as the design of the seventh or eighth figure) is a plurality of shift registers corresponding to driving a plurality of scan lines, and the layout thereof is as shown in FIG. 10D. Shown. One of the shift registers includes a power supply line VL adjacent to the fourth side VII-4 of the heptagon, and the substrate edge 13E corresponding to the heptagon is substantially parallel. The circuit diagram of the above shift register is shown in Fig. 11.

In an embodiment of the invention, the first circuit region 131 of the heptagon is The design of the seventh or eighth figure is a plurality of shift registers corresponding to driving a plurality of scan lines, and the layout thereof is as shown in FIG. 10D. One of the shift registers includes a power supply line VL adjacent to a fifth side VII-5 of the heptagon. The circuit diagram of the above shift register is shown in Fig. 11.

In an embodiment of the present invention, the first circuit region 131 of the heptagon (such as the design of the seventh or eighth figure) is a plurality of shift registers corresponding to driving a plurality of scan lines, and the layout thereof is as shown in FIG. 10D. Shown. One of the shift registers includes a power supply line VH adjacent to the first side VII-1 and the seventh side VII-7 of the heptagon. The circuit diagram of the above shift register is shown in Fig. 11.

In an embodiment of the invention, the first circuit region 131 is a heptagon, and the second circuit region 133 is hexagonal, and the second circuit region 133 is sandwiched between the first circuit region 131 and the pixel 110 ( As designed in Figure 9). The first circuit area 131 is a shift register, and the layout thereof can be referred to the 10D. The second circuit area 133 is a plurality of multiplex controllers corresponding to driving a plurality of data lines, and one of the multiplex controllers includes a power supply line VL adjacent to the fifth side VI-5 of the hexagon. The circuit diagram of the above multiplex controller is shown in Fig. 12. It is to be noted that the layout of Figures 10A through 10D and the circuit diagrams shown in Figures 11 and 12 are for illustrative purposes only and are not intended to limit the invention. As long as it is a layout or circuit capable of driving a pixel shift register or a multiplex controller, it can be used as a layout or circuit of the first circuit region 131 or the second circuit region 133 of the present application.

In summary, the present application has provided a novel circuit area shape design. The above circuit area shape can reduce the space between the circuit area and the edge of the substrate, and can be applied to any position of the peripheral area.

Although the present invention has been disclosed above in several embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art In the spirit and scope of the invention, the scope of the invention is defined by the scope of the appended claims.

P‧‧‧ side

V-1‧‧‧ first side

V-2‧‧‧ second side

V-3‧‧‧ third side

V-4‧‧‧ fourth side

V-5‧‧‧ fifth side

11A‧‧‧First direction

11B‧‧‧second direction

11C‧‧‧ diagonal

13E‧‧‧ substrate edge

15‧‧‧ wiring

110‧‧‧ pixels

133‧‧‧Second circuit area

Claims (17)

A display device includes: a display area having a plurality of pixels on a substrate; and a peripheral area located outside the display area, the peripheral area having a plurality of first circuit areas and a plurality of In the two circuit areas, the first circuit areas drive the pixels in a first direction, and the second circuit areas drive the pixels in a second direction; wherein one of the first circuit areas At least one of the second circuit regions is a pentagon having a first side, a second side, a third side, a fourth side, and a fifth side connected in sequence, wherein the five The first side of the edge is parallel to the second direction, wherein the second side of the pentagon is parallel to the first direction, wherein the third side of the pentagon is diagonal to one of the pixels Parallel, wherein the fourth side of the pentagon is substantially parallel to the edge of the substrate corresponding to the pentagon, and the length of the fourth side of the pentagon is greater than the length of at least one of the sides of the pixels And wherein the fifth side of the pentagon is parallel to the third side of the pentagon. The display device of claim 1, wherein the first side of the pentagon is adjacent to a side of one of the outermost pixels of the display area, and the second side of the pentagon Adjacent to the side of the other of the outermost pixels in the display area. The display device of claim 1, wherein the pixels are rectangular, the first direction is perpendicular to the second direction, and each of the first electrodes The lane drives a single column of pixels, and each of the second circuit regions drives at least one row of pixels. The display device of claim 1, wherein the display area is substantially circular. The display device of claim 1, wherein the first circuit regions are a plurality of shift registers corresponding to driving a plurality of scan lines, and one of the shift registers includes a power supply line. The power supply line is adjacent to the fourth side of the pentagon, and the substrate edge corresponding to the pentagon is substantially parallel. The display device of claim 1, wherein the second circuit regions are a plurality of multiplex controllers corresponding to driving a plurality of data lines, and one of the multiplex controllers includes a timing signal line. The timing signal line is adjacent to the fourth side of the pentagon, and the substrate edge corresponding to the pentagon is substantially parallel. The display device of claim 1, wherein one of the first circuit regions and the other one of the second circuit regions are hexagonal and sandwiched between the pentagons Between the display area and the display area, wherein the hexagon has a first side, a second side, a third side, a fourth side, a fifth side, and a sixth side connected in sequence, wherein the hexagon is first The edge is parallel to the second direction and adjacent to a side of one of the outermost pixels in the display area, wherein the second side of the hexagon is parallel to the first direction and is the most in the display area The other side of the outer pixel is adjacent to the side, wherein the third side of the hexagon is parallel to the diagonal of one of the pixels, wherein the fourth side of the hexagon and the six sides The first side of the shape is parallel and The first side of the pentagon is parallel, wherein the fifth side of the hexagon is parallel to the second side of the hexagon and parallel to the second side of the pentagon, wherein the sixth of the hexagon The sides are parallel to the third side of the hexagon. The display device of claim 7, wherein the second circuit areas are a plurality of multiplex controllers corresponding to driving a plurality of data lines, and one of the multiplex controllers includes a power supply line. The power supply line is adjacent to the fifth side of the hexagon. A display device includes: a display area having a plurality of pixels on a substrate; and a peripheral area located outside the display area, the peripheral area including a plurality of first circuit areas and a plurality of In the two circuit regions, the first circuit regions drive the pixels in a first direction, and the second circuit regions drive the pixels in a second direction; wherein the one of the first circuit regions and the pixels At least one of the second circuit regions is a heptagonal shape having a first side, a second side, a third side, a fourth side, a fifth side, a sixth side, and a seventh side, wherein the first side of the heptagon is parallel to the second direction, wherein the second side of the heptagon is parallel to the first direction, wherein the fourth side of the heptagon and the heptagon Correspondingly, the edge of the substrate is substantially parallel, and the length of the fourth side of the heptagon is greater than the length of at least one of the sides of the pixels, wherein the sixth side of the heptagon and the heptagon The first side is parallel, and wherein the seventh side of the heptagon is parallel to the second side of the heptagon. The display device of claim 9, wherein the first side of the heptagon is adjacent to the first side of the first one of the outermost pixels in the display area, the seventh side of the heptagon The two sides are adjacent to the side of the second one of the outermost pixels in the display area, and the sixth side of the heptagon is adjacent to the side of the third party of the outermost pixel in the display area And the seventh side of the heptagon is adjacent to the second side of the first one of the outermost pixels in the display area. The display device of claim 9, wherein the pixels are rectangular, the first direction is perpendicular to the second direction, and each of the first circuit regions drives a single column of pixels, and each of the pixels The second circuit regions drive at least one row of pixels. The display device of claim 9, wherein the display area is substantially circular. The display device of claim 9, wherein the first circuit regions are a plurality of shift registers corresponding to driving a plurality of scan lines, and one of the shift registers includes a power supply line The power supply line is adjacent to the fourth side of the heptagon, and the substrate edge corresponding to the heptagon is substantially parallel. The display device of claim 9, wherein the first circuit regions are a plurality of shift registers corresponding to driving a plurality of scan lines, and one of the shift registers includes a power supply line The power supply line is adjacent to the fifth side of the heptagon. The display device of claim 9, wherein the first circuit regions are a plurality of shift registers corresponding to driving a plurality of scan lines, and one of the shift registers includes a power supply line The power supply line is adjacent to the first side of the heptagon and adjacent to the seventh side of the heptagon. The display device of claim 9, wherein one of the first circuit regions and the other one of the second circuit regions are hexagonal and sandwiched by the heptagon Between the display area and the display area, wherein the hexagon has a first side, a second side, a third side, a fourth side, a fifth side, and a sixth side connected in sequence, wherein the hexagon is first The edge is parallel to the second direction and adjacent to a side of one of the outermost pixels in the display area, wherein the second side of the hexagon is parallel to the first direction and is the most in the display area The other side of the outer pixel is adjacent to the side, wherein the third side of the hexagon is parallel to the diagonal of one of the pixels, wherein the fourth side of the hexagon and the six sides The first side of the shape is parallel and adjacent to the first side of the heptagon or the sixth side of the heptagon, wherein the fifth side of the hexagon is parallel to the second side of the hexagon, and Adjacent to the second side of the heptagon or the seventh side of the heptagon, wherein the sixth side of the hexagon is parallel to the third side of the hexagon. The display device of claim 16, wherein the second circuit areas are a plurality of multiplex controllers corresponding to driving a plurality of data lines, and one of the multiplex controllers includes a power supply line. The power supply line is adjacent to the fifth side of the hexagon.