TWI570561B - Memory apparatus and method for operating cache - Google Patents

Description

Memory device and method of operating memory

The present invention relates generally to semiconductor memory and methods, and more particularly to apparatus and methods for a cache memory structure.

Memory devices are typically provided as internal semiconductor integrated circuits in computing devices or other electronic devices. There are many different types of memory containing volatile and non-volatile memory. Volatile memory can require power to maintain its data (eg, user data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory. Body (SDRAM) and other volatile memory. Non-volatile memory provides long-lasting data by retaining stored data when not powered, and can include NAND flash memory, NOR flash memory, read-only memory (ROM), and electrically erasable Programmable ROM (EEPROM), erasable programmable ROM (EPROM) and resistive variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM) and magnetoresistive Random access memory (MRAM) and other non-volatile memory.

A memory system can include a cache memory that can be smaller and/or faster than other memory of the system (eg, DRAM, NAND, disk storage, solid state, which can be referred to as main memory) Hard disk drive (SSD), etc.). As an example, the cache memory can include DRAM memory. A memory system can cache data to improve the performance of the memory system. Therefore, it is desirable to provide an improved performance cache memory system for delivering a memory system. of. The improved cache memory latency and hit rate provide improved performance performance of the memory system.

100‧‧‧ system

102‧‧‧Interconnect bus

104‧‧‧伫

110‧‧‧Cache Memory DRAM Device / Cache Memory DRAM

112‧‧‧Cache Memory Controller

114‧‧‧Input interface

115‧‧‧Sense Amplifier

116‧‧‧Output interface

117‧‧‧Comparative logic

118‧‧‧Array

119‧‧‧Sensor circuit

120‧‧‧ memory device

122‧‧‧ Controller

124‧‧‧ Busbars

210‧‧‧Cache Memory DRAM Device / Cache Memory DRAM

220‧‧‧ memory device

230-0‧‧‧

Page 230-R‧‧‧

232-0‧‧‧

Page 232-1‧‧‧

232-(S-1)‧‧‧Page

232-S‧‧‧

234-0‧‧‧ Block

234-(P-1)‧‧‧ Block

340‧‧‧ slots

342‧‧‧ address

344‧‧‧ Valid Bits

346‧‧‧ changed bits

348‧‧‧Information

432-1‧‧‧Cache Memory Page/Page

432-2‧‧‧Cache Memory Page/Page

452-(M-1)‧‧‧ slot

452-(M/2)‧‧‧ slots

452-(M/4)‧‧‧ slots

560‧‧‧ Order

562‧‧‧Command indicator

564‧‧‧ address

566‧‧‧Transaction ID

648‧‧‧Information

666‧‧‧Transaction ID

672‧‧‧Respond

674‧‧‧Respond

676‧‧‧ hit indicator

678‧‧‧ Missing indicator

742‧‧‧ address

748‧‧‧Information

766‧‧‧Transaction ID

782‧‧‧Respond

784‧‧‧Respond

786‧‧‧Write completion indicator

M-1‧‧‧ position

M-2‧‧‧ position

M/2‧‧‧ position

(M/2)-1‧‧‧ position

1 illustrates a block diagram of one of the devices in the form of a system including a cache memory in accordance with several embodiments of the present invention.

2 is a block diagram illustrating a mapping of data mapped from one memory of a memory device to a cache memory in accordance with some embodiments of the present invention.

3 illustrates one cache memory item in a cache memory in accordance with several embodiments of the present invention.

4A and 4B illustrate the contents of a page in a cache memory in accordance with several embodiments of the present invention.

Figure 5 illustrates one of the commands associated with one of the devices including the cache memory in accordance with several embodiments of the present invention.

6A-6B illustrate a response to a read command associated with one of the devices including the cache memory, in accordance with several embodiments of the present invention.

7A-7B illustrate a response to a write command associated with one of the devices including the cache memory, in accordance with several embodiments of the present invention.

The present invention includes apparatus and methods for a cache memory structure. An exemplary device comprising a cache memory structure in accordance with the present invention can include an array of memory cells configured to store a plurality of cache memory items per memory unit page. The device can include a sensing circuit configured to determine whether a cache memory data corresponding to a request from one of the cache memory controllers is located at a location in the array corresponding to the request, And the response indicating whether the cache memory data is located at the location in the array corresponding to the request is returned to the cache controller.

In several embodiments, the cache memory structure of the present invention can provide a mapping to a record Multiple cache memory items on the same page (eg, a column) of a memory device (eg, a CDRAM device, an STT-RAM device, a PCM device (for example), and other memory devices), which may allow Parallel inspection of multiple cache memory items on the memory device. In several embodiments, the cache memory structure of the present invention can provide reduced energy consumption and/or improved delay as compared to prior methods. For example, in some embodiments, comparison logic (eg, a comparator) can be embedded in a sensing circuit or elsewhere in a cache memory (eg, CDRAM) to not include data (eg, tags) Data and/or cache memory data) A comparison of multiple cache memory items is performed in parallel with the transfer of CDRAM (eg, via an input/output (I/O) line). The tag data from the command tag data and the CDRAM cache memory item can be compared to determine whether the requested data is in the CDRAM or whether the CDRAM is ready to write the data corresponding to a command to the CDRAM. Performing such comparisons using the sensing circuitry on the CDRAM may allow execution of the command without, for example, transferring data between the CDRAM and a cache memory controller. In some embodiments, a cache memory structure can include a dual (eg, separate) interface (eg, an input interface and an output interface) for receiving commands and transmitting responses.

BRIEF DESCRIPTION OF THE DRAWINGS In the following detailed description of the invention, reference to the claims The embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments of the present invention, and it is understood that other embodiments can be utilized and can be practiced without departing from the scope of the invention. / or structural changes. As used herein, the designations "M", "N", "P", "R", and "S" (especially with respect to the component symbols in the drawings) may include a number of specific features so marked. As used herein, "a plurality of" a particular thing may refer to one or more of such things (eg, a plurality of memory devices may refer to one or more memory devices).

The figures herein follow the numbering convention in which the first number or the first few digits correspond to the figure number of the drawing and the remaining digits identify one of the elements or components in the drawing. By making Similar numbers are used to identify similar elements or components between different figures. For example, 120 can refer to component "20" in FIG. 1, and a similar component in FIG. 2 can be referred to as 220. As will be appreciated, the elements shown in the various embodiments herein can be added, interchanged, and/or eliminated to provide several additional embodiments of the invention.

1 is a block diagram of one of the devices in the form of a system 100 including a cache memory in accordance with several embodiments of the present invention. In FIG. 1, the cache memory can be a cache memory DRAM (CDRAM) device 110. In the example shown in FIG. 1, system 100 includes a memory device 120, a cache controller 112, a controller 122, a queue 104, and an interconnect bus 102. In some embodiments, CDRAM device 110, memory device 120, cache memory controller 112, controller 122, and queue 104 can also be considered a device. The CDRAM device 110 includes an array 118 of DRAM memory cells and a sensing circuit 119. Sensing circuit 119 can include a number of sense amplifiers 115 and comparison logic 117 (eg, a number of comparators) that are used in connection with executing commands received by CDRAM device 110. CDRAM device 110 can be coupled to cache memory controller 112 via input interface 114 and output interface 116. Input interface 114 can be used to receive information (e.g., commands and/or data) from cache memory controller 112 at CDRAM device 110. Output interface 116 can be used to send information from CDRAM device 110 to cache memory controller 112.

In some embodiments, memory device 120 can include an array of memory cells (such as DRAM memory cells and/or NAND memory cells (for example) and other types of memory cells). The memory device 120 can be used as a backup storage area for storing data that can be cached by the CDRAM device 110.

In some embodiments, memory device 120 can be coupled to controller 122 via bus bar 124. The bus bar 124 can be a shared bus bar 124 or can include a number of individual bus bars (eg, address bus, data bus, control bus, etc.) to transfer information between the controller 122 and the memory device 120. In some embodiments, system 100 can include a number of memory devices (eg, memory device 120) coupled together via bus bar 124 and if A dry controller (eg, controller 122).

In some embodiments, system 100 can be coupled to a host (eg, a host processor) and/or other memory device (not shown) via interconnect bus 102. The host and/or other memory device can send data and/or commands to the queue 104 via the interconnect bus 102. System 100 can store data in memory device 120 and use CDRAM memory device 110 to retrieve one of the memory systems from memory device 120. System 100 can also cache data received from a host and/or other memory device via interconnect bus 102 (e.g., in CDRAM device 110).

System 100 can cache data by sending a command, for example, from queue 104 to CDRAM 110. For example, the command can be a read command or a write command. The command can be communicated from the queue 104 to the cache controller 112 and to the CDRAM 110 via the input interface 114. The commands communicated via the input interface 114 can include a command indicator, tag data (eg, a single address), and a transaction ID (TID).

In some embodiments, CDRAM device 110 can process a read command by locating a particular cache memory item (e.g., slot) indicated by the read command address. CDRAM device 110 may include multiple cache memory items on a single page, which may allow for the inspection of multiple cache memory items by accessing (eg, turning on) a single page. In some embodiments, a cache memory page can include a plurality of cache memory items, wherein each cache memory item includes cached data from a backup storage area (eg, memory device 120). portion. Exemplary cache memory pages and cache memory items are further illustrated below in connection with Figures 2 through 4. The CDRAM device 110 can read the data corresponding to the indicated cache memory item and use comparison logic (eg, a comparator) to determine whether a validity indicator indicates that the data corresponding to the command is located at an address corresponding to the command. (For example, whether one of the valid bits of the cache memory item is set and the block address of one of the read command addresses matches the block address bit of the cache memory item). If a valid bit is set and the block address matches, the slot can be considered a hit and CDRAM 110 can pass a suitable response via the output. Interface 116 is passed back to cache memory controller 112. The response to the cache controller 112 may include a TID and cache data corresponding to the cache memory item. Including the TID in the response may allow the cache memory controller 112 to identify the particular command corresponding to the response. For example, if the valid bit and/or the block address are not matched, the cache memory item can be regarded as a miss and the CDRAM 110 can indicate the cache data requested in the read command. One of the non-located CDRAMs 110 is adapted to be passed back to the cache controller 112 via the output interface 116. The response to the cache controller 112 can include a TID that can be used by the cache controller to identify the particular command corresponding to the response.

In some embodiments, CDRAM device 110 can process a write command by locating a particular cache memory item (e.g., a slot) indicated by a write command address. The CDRAM 110 can read the data corresponding to the indicated slot and use the comparison logic located on the CDRAM device 110 to determine whether a validity indicator indicates that the valid data is located in a slot corresponding to the address in the command (eg, whether to set The valid bit in the slot and whether the changed bit in the slot is set. One of the unset valid bits determines that the slot is not storing valid data so that data corresponding to the write command can be written to the cache memory item. Setting a valid bit but not setting one of the changed bits determines that the cache memory item is storing valid data that is not different from the data in a backup storage area, so that the data can be written from the write command to Cache memory items. A response indicating that the write has been completed can be sent to the cache controller. The response may include a Transaction ID (TID) that identifies which particular command was completed. Setting a valid bit and setting one of the changed bits determines that the data currently in the slot will be withdrawn. After the data is withdrawn from the slot, the data corresponding to the write command is written to the slot. A response indicating that the write has been completed can then be sent to the cache controller 112. The response may include a TID and the information withdrawn from the slot and the address of the data. System 100 can then pass the withdrawn data back to a backup storage area (e.g., memory device 120).

2 is a block diagram illustrating a mapping of data mapped from one memory of a memory device to a cache memory in accordance with some embodiments of the present invention. The example shown in FIG. 2 illustrates a direct mapping of data from memory device 220 to CDRAM device 210. The memory device 220 can include a number of blocks (eg, block 234-0 and block 234-(P-1)) and each block can include several pages of memory cells (eg, page 230-0 and page 230) -R). Each page of a block can be cached to the same location in CDRAM device 210. For example, a first page of a block (eg, page 230-0 from block 234-0 or block 234-(P-1)) may be cached to the first two pages of CDRAM device 210 (eg, , pages 232-0 and 232-1). The data from locations M-1 through M/2 of page 230-0 can be mapped and cached to page 232-1 of CDRAM device 210. In some embodiments, a page from a memory device can be mapped to the first two pages of a CDRAM device (eg, if one of the pages in the memory device is twice as large as one of the pages in the CDRAM device). For example, a 4KB page of a particular memory device can be mapped into two 2KB pages of a CDRAM device. In FIG. 2, page 230-0 from memory device 220 includes locations 0, 1, ..., M-2, M-1, and page 230-0 is mapped to pages 232-0 and 232 in CDRAM device 210. 1. The first half of page 230-0, such as position 0 to (M/2)-1, is mapped to page 232-1 and the second half of page 230-0, such as position M/2 to M-1, Mapped to page 232-0. In addition, in FIG. 2, the last page of the block in memory device 220 (eg, page 230-R) is mapped to the last two pages of CDRAM 210 (eg, page 232-(S-1) and 232-S). The first half of page 230-R is mapped to page 232-S and the second half of page 230-R is mapped to page 232-(S-1).

Embodiments of the invention are not limited to direct mapping. For example, CDRAM device 210 can be used as an N-way associated cache memory. That is, correlation can be used to map data from a memory device to a CDRAM device. The CDRAM device can be configured such that each of the locations of the cache memory item (e.g., slot) corresponding to one of a particular portion of the data from a memory device can be mapped to the same page in the CDRAM device . Thus, when the data is located in the CDRAM device, each location (e.g., slot) to which the requested data can be located is on the same page in the CDRAM. So, just open, Reading a page, and only one page needs to have its tag data compared to the tag data from a command to determine whether the requested cache data is located in a CDRAM device corresponding to a particular portion of the data from a memory device. One of the possible locations of the cache memory item.

3 illustrates one cache memory item in a cache memory in accordance with several embodiments of the present invention. In several embodiments, one page of the cache memory, such as CDRAM, can include several (eg, multiple) cache memory items (eg, slots). Each slot may contain a portion of the data cached from a memory device and tag data (eg, a bit address, a valid bit, and a changed bit). In FIG. 3, slot 340 contains tag data including a bit address 342, a valid bit 344, and a changed bit 346. Slot 340 also contains material 348 (e.g., cache memory data). Address 342 contains a number of bits indicating the block, page, and slot of slot 340. Valid bit 344 contains a bit indicating whether the data in the slot is valid (eg, contains data currently being cached by CDRAM) and changed bit 346 contains information indicating whether the data in the slot has changed but has not been written yet One bit to a backup storage area. The data 348 can include a number of bits representing the cache memory data stored in the slot 340.

4A and 4B illustrate the contents of a page in a cache memory in accordance with several embodiments of the present invention. In FIG. 4A, cache memory page 432-1 may include a number of cache memory items (eg, slots 452-(M-1) and 452-M/2). Each of the slots may contain tag data (which includes a bit address, a valid bit, and a changed bit) and cache data. For example, page 432-1 can cache data corresponding to the first half of one of the pages from a backup storage area (eg, if the page from the backup storage area is the cache memory) Page 432-1 is twice as large).

In FIG. 4B, cache memory page 432-2 may include a number of cache memory items (eg, slots 452-(M-1) and 452-M/4). Each of the slots may include tag data (which includes a bit address, a valid bit, and a changed bit), and also includes cache memory data to And a path index (WI). A path index (eg, WI-1 or WI-N) may be used to indicate one of a number of potential slots, where, for example, when CDRAM is using N-way correlation, the requested data may be located at that particular In the slot. In this example, page 432-2 can include a number of slots, each of which can store data corresponding to one-quarter of one page of data from a backup storage area (eg, if data from the backup storage area) This page is twice as large as the cache memory page 432-2 and is cached by the 2-way associative memory page 432-2). In FIG. 4B, cache memory page 432-2 illustrates 2-way correlation, wherein data corresponding to location M-1 from a memory device (eg, a backup storage area) may be located in a corresponding path. The information in any of the slots 452-(M-1) of the index WI-1 or WI-N and corresponding to the location M/4 from a memory device may be located with the path index WI-1 or WI-N. In any of the slots 452-(M/4). In several embodiments, CDRAM can accommodate various degrees of correlation (eg, N-way correlation).

FIG. 5 illustrates a command 560 associated with a device including one of cache memories in accordance with several embodiments of the present invention. For example, command 560 can be a read command or a write command. Command 560 can include a command indicator 562 that indicates the type of command (eg, a read command or a write command). The command 560 can also include tag material that includes a bit address 564 that indicates the block, page, and/or slot of the data associated with the command 560. The command 560 also includes a transaction ID (TID) 566 that can be used by the cache controller and/or the CDRAM device to identify commands corresponding to the data communicated between the cache controller and the CDRAM device.

As an example, command 560 can receive a read command from a CDRAM device. The CDRAM device can process the command by locating the particular cache page indicated in the command and opening the page. One of the specific slots indicated in the command can be located in the cache page that is opened and the tag data in the particular slot can be read. The compare logic on the CDRAM device can be used to check if the valid bit in the slot is set and the block address in the command address matches the block address bit in the slot. If the valid bit is set and the block address is With the match, the slot can be considered a hit and the CDRAM can pass a suitable response back to the cache controller. The response to the cache controller can include a TID and cache data from a particular slot. If the valid bit and/or the block address are not matched, the slot is considered to be a miss and the CDRAM can respond with a suitable response (eg, indicating that the requested data in the read command is not located in the CDRAM) ) is passed back to the cache memory controller.

In some embodiments, a CDRAM 110 can process the write command by locating the slot indicated in the address of a write command. The CDRAM (e.g., 110) can read the data at the slot and use the comparator to check if the valid bit in the slot is set and if the changed bit is set. If a valid bit is not set, the data from the write command can be written to the slot. If a valid bit is set but the changed bit is not set, the data from the write command can be written to the slot. A response indicating that the write has been completed may be sent to a cache controller (e.g., 112). The response may include a transaction ID (TID) that may be used by the cache controller (e.g., 112) to identify which particular command was completed. Setting a valid bit and setting one of the changed bits determines that the cached data currently in the slot needs to be withdrawn. After the cache data is withdrawn from the slot, the cache data from the write command can be immediately written to the slot. A suitable response to the write write can then be sent to a cache controller. The response may include a Transaction ID (TID) and the information withdrawn from the slot and the address of the data. The withdrawn data can be passed back from the CDRAM to a backup storage area (e.g., memory device 120).

6A-6B illustrate a response to a read command associated with one of the devices including the cache memory, in accordance with several embodiments of the present invention. Figure 6A illustrates a response 672 to one of the read commands, the response being a hit. In FIG. 6A, response 672 includes a hit indicator 676, a transaction ID (TID) 666, and data 648. The hit indicator 676 can indicate that the requested data in the read command is present in the CDRAM. The transaction ID 666 can be used to identify the command associated with the response 672. The data 648 can be the cache data requested in the read command read from the CDRAM. Can respond to processing one of the commands CDRAM The device transmits a response 672 from the CDRAM device to a cache memory controller on an output interface. The CDRAM device can process the command during processing of a command without transmitting data (e.g., tag data) between the CDRAM device and the cache controller.

Figure 6B illustrates a response 674 to one of the read commands, which is a miss. In FIG. 6B, response 674 includes a missing indicator 678 and a transaction ID (TID) 666. The missing indicator 678 may indicate that the requested material in the read command is not present in the CDRAM. The transaction ID 666 can be used to identify the command associated with the response 674. A response 674 can be sent from the CDRAM device to a cache memory controller on an output interface in response to processing a CDRAM device of a command. The CDRAM device can process the command during processing of a command without transmitting data (e.g., tag data) between the CDRAM device and the cache controller.

7A-7B illustrate a response to a write command associated with one of the devices including the cache memory, in accordance with several embodiments of the present invention. Figure 7A illustrates a response 782 to a write command that writes data to a valid bit or changed bit (e.g., when the write command is executed, the data is not withdrawn) ) One of the slots. In FIG. 7A, response 782 includes a write completion indicator 786 and a transaction ID (TID) 766. The write completion indicator 786 can indicate that the data in the write command is written to the CDRAM. The transaction ID 766 can be used to identify the command associated with the response 782. A response 782 can be sent from the CDRAM device to a cache memory controller on an output interface in response to processing a CDRAM device of a command. The CDRAM device can process the command during processing of a command without transmitting data (e.g., tag data) between the CDRAM device and the cache controller.

Figure 7B illustrates a response 784 to one of the write commands that writes data to where the valid bit and the changed bit are set (e.g., when the write command is executed, the data is withdrawn) One of the slots. In Figure 7B, response 784 includes a write completion indicator. 786, a transaction ID (TID) 766 and the address 742 of the withdrawn data, and information 748 withdrawn from a slot. The write completion indicator 786 can indicate that the data in the write command is written to the CDRAM. The transaction ID 766 can be used to identify the command associated with the response 782. The address 742 of the withdrawn data and the withdrawn data 748 can be read from the slot by the CDRAM device and sent to the cache controller in response 784 so that the withdrawn data can be written to Memory device. A response 784 can be sent from the CDRAM device to a cache memory controller on an output interface in response to processing a CDRAM device of a command. The CDRAM device can process the command during processing of a command without transmitting data (e.g., tag data) between the CDRAM device and the cache controller.

The present invention includes apparatus and methods for a cache memory structure. An exemplary device comprising a cache memory structure in accordance with the present invention can comprise: a memory cell array configured to store a plurality of cache memory items per memory cell page; and a sensing circuit Configuring to determine whether a cache memory data corresponding to a request from one of the cache memory controllers is located at a location in the array corresponding to the request, and indicating whether the cache memory data is located corresponding to the One of the requested locations in the array is returned to the cache controller.

Although specific embodiments have been illustrated and described herein, it will be understood by those skilled in the art that the <RTIgt; The invention is intended to cover modifications or variations of one or more embodiments of the invention. It should be understood that the above description has been made in an illustrative manner and not in a limiting manner. After reviewing the above description, those skilled in the art will immediately understand the combination of the above embodiments and other embodiments not specifically described herein. The scope of one or more embodiments of the invention encompasses other applications in which the above architectures and methods are used. Therefore, the scope of one or more embodiments of the invention should be determined by the scope of the appended claims.

In the foregoing embodiments, certain features are included together for the purpose of simplifying the present invention. Collected in a single embodiment. This method of the invention is not to be interpreted as reflecting that the disclosed embodiments of the invention are intended to use one of the features of the invention. Rather, the scope of the following claims is to be construed that the invention Accordingly, the scope of the following claims is hereby incorporated by reference in its entirety in its entirety in its entirety herein

100‧‧‧ system

102‧‧‧Interconnect bus

104‧‧‧伫

110‧‧‧Cache Memory DRAM Device / Cache Memory DRAM

112‧‧‧Cache Memory Controller

114‧‧‧Input interface

115‧‧‧Sense Amplifier

116‧‧‧Output interface

117‧‧‧Comparative logic

118‧‧‧Array

119‧‧‧Sensor circuit

120‧‧‧ memory device

122‧‧‧ Controller

124‧‧‧ Busbars

Claims (23)

A memory device comprising: a memory cell array configured to store a plurality of cache memory items per memory cell page; and a sensing circuit configured to: compare by a fast Taking the tag data read from the location in the memory and the tag data requested from one of the comparison logics located in the cache memory to determine the cache memory corresponding to the request from a cache memory controller Whether the volume data is located at a location in the array corresponding to the request, wherein the tag data read from the location in the array is the only tag data that is read and based on the controller from the cache memory The information in the request is located in the array, and wherein the location in the array corresponds to a specific location in a memory device, the specific location is mapped to where the corresponding data is requested; and the indication is fast Whether the memory data is located at one of the locations in the array corresponding to the request is returned to the cache controller. The device of claim 1, wherein the device is configured to: return the cache memory in response to determining that the cache memory data corresponding to the request is located at one of the locations in the array corresponding to the request Body data. The device of claim 1, wherein the device is configured to: correspond to the request in response to indicating that the valid material is not in a state of a validity indicator at the location in the array corresponding to the request The cache data is written in the memory cell array. The device of claim 1, wherein the device is configured to: respond to a validity indicator indicating that the valid material is at the location in the array corresponding to the request A changed state is withdrawn from the array. The device of claim 4, wherein the device is configured to: after the changed data is withdrawn from the location in the array of memory cells, the cache data corresponding to the request is written in the array At that location. The device of claim 1 to 5, wherein the device is configured to: determine whether the cache data is located in the array corresponding to the request without transmitting the tag data to the cache controller In the middle of the location. The device of any one of claims 1 to 5, wherein each of the plurality of cache memory items is stored in one of a plurality of slots on one of a plurality of pages of the array of memory cells . A method for operating a cache memory, comprising: receiving a read request from a cache memory controller; transmitting a tag from the cache memory without an input/output (I/O) interface In the case of data, the cache corresponding to the read request is determined by comparing the tag data read from the cache memory with the tag data from the read request using the comparison logic located in the cache memory. Whether the memory data is located in the cache memory, wherein the tag data read from the location in the cache memory is the only tag data read and based on the tag from the cache controller The information in the read request is located in the cache memory, and wherein the location in the cache memory corresponds to a specific location in a memory device, the specific location is mapped to the corresponding location of the data And returning to the cache memory controller a response indicating whether the cache memory data corresponding to the read request is located in the cache memory. The method of claim 8, wherein the method comprises: responding to the cache memory by one of the cache memory data corresponding to the read request by the comparison logic being located in the cache memory The body data is passed back to the cache from the read request Memory controller. The method of any one of clauses 8 to 9, wherein the returning the response comprises: responding to the validity indication that the valid material is not located in the cache memory at the location corresponding to the read request And providing an indication in the response that the cache memory data is not located in the cache memory. The method of any one of clauses 8 to 9, wherein the returning the response comprises: responding to the tag data associated with the read request not matching the tag data in a corresponding location in the cache memory The response provides an indication that the cache memory data is not located in the cache memory. A method for operating a cache memory, comprising: receiving a write request from a cache memory controller; and comparing the tag data read from the cache memory with the slave access located in the cache The comparison logic of the memory writes the tag data of the request to determine whether the valid data is located at a position in the cache corresponding to the write request, wherein the location is read from the cache memory Taking the tag data as the only tag data to be read and the information based on the write request from the cache controller is located in the cache memory, and wherein the location in the cache memory Corresponding to a specific location in a memory device, the specific location is mapped to the location corresponding to the data requested; and the location in the cache corresponding to the write request includes one of valid data Deciding to withdraw the data from the location; writing the cache data corresponding to the write request to the location in the cache corresponding to the write request; and indicating the corresponding to the write The demand of cache data has been written to one of the cache memory responses are returned to the cache memory controller. The method of claim 12, wherein determining whether the valid material is located corresponding to the write The location in the requested cache memory includes: determining a state of a first indicator and a second indicator. The method of any one of clauses 12 to 13, wherein the first indicator is a valid bit and a second indicator is a changed bit. The method of any one of clauses 12 to 13, wherein the returning the response back to the cache memory controller includes the location of the location in the cache memory corresponding to the write request being withdrawn data. A memory device, comprising: a memory device coupled to a controller; and a cache memory comprising a memory cell array and a sensing circuit, wherein the cache memory is via an input interface and An output interface is coupled to a cache memory controller, and wherein the cache memory is configured to locate a particular page of the cache memory indicated by a command and only from the input interface via the input interface Receiving the command, processing the command, and transmitting a response to the cache controller via the output interface, wherein the specific page in the cache corresponds to a memory A particular location in the device that is mapped to where the data corresponding to the command is located. The device of claim 16, wherein the sensing circuit includes comparison logic to determine whether the material corresponding to the command is located at a location in the cache corresponding to the command. The device of any one of claims 16 to 17, wherein the cache memory is configured to process the command without transferring the tag data to the cache memory controller. The device of any one of claims 16 to 17, wherein the cache memory is configured to: process the command by checking a plurality of cache memory items in parallel logic to determine whether the data corresponding to the command is Located in the cache memory corresponding to the command In the body. A memory device includes: a memory cell array configured to store a plurality of cache memory items per memory unit page, and each specific memory unit page is configured to store a backup corresponding to a backup a plurality of cache memory items at a specific address of the storage area; and a sensing circuit configured to: transfer the tag data from the plurality of cache memory items to a cache memory controller In the case of determining whether the cache memory data is located corresponding to the command in the command by locating a specific page in the cache memory indicated by a command and reading only the data from the specific page. In one of the plurality of cache memory items of a specific address of the backup storage area, the data corresponding to the command is also located at the specific address of the backup storage area. The device of claim 20, wherein the sensing circuit is configured to indicate whether the cache memory data is located in the plurality of cache memories corresponding to the particular address of the backup storage area indicated in the command One of the items responded back to the cache controller. The device of any one of claims 20 to 21, wherein the sensing circuit includes the plurality of sensing circuits for determining whether the cache memory material is located at the specific address corresponding to the backup storage area indicated in the command The comparison logic in one of the cached memory items. The device of any one of claims 20 to 21, wherein the sensing circuit is configured to: determine whether the cache memory data is located in the command corresponding to the command by turning on a particular page of the memory cell array One of the plurality of cache memory items indicating the particular address of the backup storage area.