TWI569577B - Logic circuits - Google Patents

Description

Logic circuit

The invention relates to a logic circuit with low leakage current, in particular to a logic circuit for reducing gate leakage current.

As the semiconductor process continues to advance, the thickness of the gate oxide layer also decreases. However, the thin gate oxide layer causes the gate leakage current to increase, which in turn causes the quiescent current to be too large when the circuit is operating in the standby state. . In order to reduce the influence of the gate leakage current, the thickness of the gate oxide layer of the semiconductor process is generally increased, so that the gate leakage current is reduced, accompanied by a drop in saturation current (I _DSAT ), so that the circuit The performance is greatly affected. Furthermore, we need a device and method that effectively reduces the gate leakage current to further enhance the performance of advanced processes.

In view of the above, the present invention provides a logic circuit, comprising: a voltage drop component coupled to a system supply power terminal for providing a system voltage lower than one of the system voltages according to a system power supply terminal An internal supply voltage; a first logic unit receiving the first internal supply voltage and outputting a first logic signal; and a first switching element, coupling the first logic unit to the first control unit according to a first control signal Ground node.

According to an embodiment of the present invention, the voltage drop element is an N-type semiconductor, including a gate terminal coupled to the voltage supply end of the system, coupled to the above a first terminal of the system supply voltage terminal and a source terminal for providing the first internal supply voltage, wherein the first logic unit is an inverter, and the first switching element is an N-type semiconductor, and includes a gate for receiving the first control signal Extremely coupled to the first terminal of the first logic unit and coupled to the source terminal of the ground node.

According to an embodiment of the present invention, the method further includes: a second switching component, configured to provide the system voltage to the first logic unit according to a second control signal, wherein the second control signal is the first control signal Inverting; a second logic unit coupled to the ground node and the first logic unit, and outputting a second logic signal according to the logic signal; and a third switching element, selecting the second control signal according to the second control signal The system voltage is supplied to the second logic unit described above.

According to an embodiment of the present invention, the first logic unit and the second logic unit operate in a standby mode and an operation mode, wherein when the first logic unit and the second logic unit operate in the standby mode, The first control signal is a low logic level and the second control signal is a high logic level, the second switching element and the third switching element are non-conducting, and the voltage drop element provides the first internal supply voltage to In the first logic unit, the first switching element stops coupling the first logic unit to the ground node, wherein when the first logic unit and the second logic unit operate in the operation mode, the first control signal Is a high logic level and the second control signal is a low logic level, the first switching element couples the first logic unit to the ground node, and the second switching element provides the system voltage to the first a logic unit and the third switching element The device supplies the above system voltage to the second logic unit.

According to an embodiment of the present invention, the second switching element is a P-type semiconductor, including a gate terminal receiving the second control signal, a drain terminal coupled to the first logic unit, and a power supply coupled to the system The second logic unit is an inverter, and the third switching element is a P-type semiconductor, and includes a gate terminal receiving the second control signal, and a 汲 terminal coupled to the second logic unit, and The source terminal of the above system voltage is received.

The invention further provides a logic circuit, comprising: a voltage drop component coupled to a system supply power terminal for providing a first internal supply lower than one of the system voltages according to a system voltage supplied by the system supply power terminal; a plurality of logic units, comprising: a plurality of first logic units receiving the first internal supply voltage; and a plurality of second logic units receiving the system voltage and coupled to a ground node, wherein the first logic unit and the first The two logic elements are alternately connected in series; and a first switching element is coupled to the first logic unit to a ground node according to a first control signal.

According to an embodiment of the present invention, the voltage drop element is an N-type semiconductor, including a gate terminal coupled to the gate terminal of the system supply voltage terminal, a drain terminal coupled to the system supply voltage terminal, and providing the first internal portion. The source of the supply voltage is extreme, the logic unit is a complex inverter, and the first switching element is an N-type semiconductor, and the gate terminal including the gate terminal receiving the first control signal and coupled to the first logic unit Extremely coupled to the source terminal of the ground node described above.

According to an embodiment of the present invention, the method further includes: a second switching element Providing the system voltage to the first logic unit according to a second control signal, wherein the second control signal is an inverse of the first control signal; and a third switching element according to the second control The signal selection provides the above system voltage to the second logic unit described above.

According to an embodiment of the present invention, the logic unit is switched between a standby mode and an operation mode, wherein when the first logic unit and the second logic unit are operated in the standby mode, the first control signal is low logic. Positioning the second control signal to a high logic level, the second switching element and the third switching element are non-conducting, the voltage drop element providing the first internal supply voltage to the first logic unit, the first The switching element stops coupling the first logic unit to the ground node, wherein when the first logic unit and the second logic unit operate in the operation mode, the first control signal is a high logic level and the foregoing The second control signal is coupled to the ground node, and the second switching element supplies the system voltage to the first logic unit and the third switching element. The above system voltage is supplied to the second logic unit described above.

According to an embodiment of the present invention, the second switching element is a P-type semiconductor, including a gate terminal receiving the second control signal, a drain terminal coupled to the first logic unit, and a power supply terminal coupled to the system The second logic unit is an inverter, and the third switching element is a P-type semiconductor, including a gate terminal receiving the second control signal, a 汲 terminal coupled to the second logic unit, and receiving The source of the above system voltage is extreme.

100‧‧‧Logical Circuit

101‧‧‧Reducing components

102‧‧‧First logical unit

103‧‧‧First switching element

104‧‧‧Second logic unit

105‧‧‧Second switching element

106‧‧‧ Third switching element

200‧‧‧ logic circuit

201‧‧‧First Inverter

202‧‧‧Second inverter

203‧‧‧First N-type semiconductor

204‧‧‧Second N-type semiconductor

205‧‧‧First P-type semiconductor

206‧‧‧Second P-type semiconductor

207‧‧‧Anti-gate

301‧‧‧Area

V _CC ‧‧‧ system voltage

V _IC ‧‧‧First internal supply voltage

S _C ‧‧‧First control signal

S _D ‧‧‧second control signal

S _F ‧‧‧first logic signal

S _G ‧‧‧Second logic signal

1 is a block diagram showing a logic circuit according to an embodiment of the present invention; FIG. 2 is a circuit diagram showing a logic circuit according to an embodiment of the present invention; and FIG. 3 is a view showing a circuit according to the present invention; A diagram of gate leakage current versus gate-source voltage across an embodiment.

The above described objects, features, and advantages of the present invention will become more apparent from the description of the appended claims appended claims A good example. It is to be understood that the invention is not limited to the scope of the invention.

1 is a block diagram showing a logic circuit in accordance with an embodiment of the present invention. As shown in FIG. 1, the logic circuit 100 includes a buck element 101, a first logic unit 102, a first switching element 103, a second logic unit 104, a second switching element 105, and a third switching element 106. The buck element 101 receives the system voltage V _CC and provides a first internal supply voltage V _IC , wherein the first internal supply voltage V _{IC is} lower than the system voltage V _CC . The first logic unit 102 receives the first internal supply voltage V _IC and outputs a first logic signal S _F . The first switching element 103 selectively couples the first logic unit 102 to the ground node according to the first control signal S _C .

The second logic unit 104 is coupled to the ground node and the first logic unit 102, and outputs the second logic signal S _G according to the first logic signal S _F . The second switching element 105 selectively supplies the system voltage V _CC to the first logic unit 102 according to the second control signal S _D , wherein the second control signal S _D is an inverse of the first control signal S _C . The third switching element 106 selectively provides the system voltage V _CC to the second logic unit 104 in accordance with the second control signal S _D .

According to a preferred embodiment of the present invention, the buck device 101 is an N-type semiconductor coupled to a diode type, and the first logic unit 102 and the second logic unit 104 are inverters, anti-gates, and anti-gates. Or one of the gates and other digital logic gates, the first switching element 103 is an N-type semiconductor, and the second switching element 105 and the third switching element 106 are P-type semiconductors. According to another embodiment of the present invention, the step-down element 101 can be a P-type semiconductor coupled in a diode form, the first switching element 103 can be a P-type semiconductor, and the second switching element 105 and the third switching element 106 can be For N-type semiconductors, everything is determined by the designer's considerations. In accordance with yet another embodiment of the present invention, the buck element 101 is a diode, a Schottky diode, and other components for depressurization purposes. Since the purpose of the buck element 101 is to provide a voltage value lower than the system voltage V _CC to the first logic unit 102 in the standby mode, any component that can provide a voltage drop function is within the scope of the present invention.

In order to clearly describe the embodiment of Fig. 1 of the present invention, Fig. 2 is a circuit diagram showing a logic circuit according to an embodiment of the present invention. As shown in FIG. 2, the logic circuit 200 is a ring oscillator, and the logic circuit 200 includes a plurality of first inverters 201, a plurality of second inverters 202, a first N-type semiconductor 203, and a second N-type semiconductor 204. The first P-type semiconductor 205, the second P-type semiconductor 206, and the anti-gate 207.

The first inverter 201 corresponds to the first logic unit 102 of FIG. 1, and the second inverter 202 corresponds to the second logic unit 104 of FIG. 1, and the first inverter 201 and the second inverter 202 alternate. Arranged in series, the AND gate 207 initiates the action of the logic circuit 200 in accordance with the first control signal S _C . The logic circuit 200 is operable in a standby mode as well as an operational mode.

The first N-type semiconductor 203 couples the first inverter 201 to the ground terminal when the first control signal S _C is at a high logic level. The second N-type semiconductor 204 is connected in a diode type and steps down the system voltage V _CC to a first internal supply voltage V _IC . According to a preferred embodiment of the present invention, the base end of the second N-type semiconductor 204 is coupled to the ground terminal such that the second N-type semiconductor 204 increases the threshold voltage due to a body effect, the system voltage V _The voltage difference between the _CC and the first internal supply voltage V _IC also increases.

The first P-type semiconductor 205 is coupled between the system voltage V _CC and the first internal supply voltage V _IC . When the second control signal S _D is at a low logic level, the system voltage V _{CC is} supplied to the first inverter 201. And the anti-gate 207. Similarly, when the second control signal S _D is at a low logic level, the second P-type semiconductor 206 provides the system voltage V _CC to the second inverter 202.

According to an embodiment of the invention, the logic circuit 200 is operable in a standby mode as well as an operational mode. When the logic circuit 200 is operating in the standby mode, the first control signal S _C is a low logic level, and the second control signal S _D is a high logic level; when the logic circuit 200 is operating in the operation mode, the first control Signal S _C is a high logic level and second control signal S _D is a low logic level. That is, when operating in the standby mode, the system voltage V _CC is lowered by the second N-type semiconductor 204 by a threshold voltage V _T and supplied to the first inverter 201 and the anti-gate 207, and because the first N-type semiconductor The non-conduction of 203 is not coupled to the ground node, and in addition the system voltage V _{CC is} not provided to the second inverter 202.

The gate leakage current is related to the voltage across the gate oxide layer. When operating in the standby mode, the first control signal S _C is a low logic level, and the initial signal S _I outputted by the gate 207 is (V _CC - V _T ) and the second inverter 202 is The N-type semiconductor is turned on, so the second logic signal S _G is at the ground level. Subsequently, the second logic signal S _G of the ground level turns on the P-type semiconductor of the first inverter 201, and thus the first logic signal S _F is (V _CC - V _T ).

For the P-type semiconductor of the first inverter 201, the gate-source voltage across the V _GS is (V _CC - V _T ), which is the gate of V _CC when there is no second N-type semiconductor 204 - The source voltage V _GS drops a threshold voltage V _T . Similarly, for the N-type semiconductor of the second inverter 202, the gate-source voltage across the V _GS is also reduced by a threshold voltage V _T compared to when the second N-type semiconductor 204 is absent.

According to an embodiment of the invention, the system voltage V _CC is 1V, the threshold voltage V _{T of the} second N-type semiconductor 204 and the gate-source voltage across the V _GS are different for the process boundary, as detailed in the table. 1.

For example, in the case of a standard process boundary, the threshold voltage V _T is 374.1 mV, that is, the second N-type semiconductor 204 is reduced to 374.1 mV by a system voltage V _{CC of} 1 V in the standby mode. An inverter 201, therefore, the gate-source voltage V _GS of the P-type semiconductor of the first inverter 201 and the N-type semiconductor of the second inverter 202 is 1V - 374.1 mV = 625.9 mV.

Figure 3 is a graph showing the relationship between gate leakage current versus gate-source voltage across an embodiment of the present invention. As shown in Fig. 3, the horizontal axis is the gate-source voltage V _GS , the vertical axis is the gate leakage current I _G , and all the gate leakage current values are gate-source voltage V _{The GS} is 1V gate leakage current value as a standard, so the gate leakage current I _{G of the} vertical axis is expressed as a percentage.

According to Table 1, the gate-source voltage across the V _GS system is between 574.8 and 666.8 mV, which is located in the region 301. It can be seen that the gate leakage current is added after the second N-type semiconductor 204 is added. I _G will be reduced by about 80% to 90%.

Therefore, the present invention can effectively reduce the gate leakage current by as much as 90% while adding only one voltage drop element without additionally increasing the circuit complexity. If there is no step-down element 101 of FIG. 1 and a second N-type semiconductor 204 of FIG. 2, taking the second figure as an example, in the standby mode, the first internal supply voltage V _IC is in a floating state. When the standby mode transitions to the operating mode, the first internal supply voltage V _IC must be charged from approximately 0V to the system voltage V _CC , which will result in additional power consumption and noise generation. In contrast, in the embodiment of FIG. 2, the first internal supply voltage V _IC only needs to be charged to the system voltage V _CC by (V _CC -V _T ), and since the voltage change is reduced, the wake-up time of the circuit from the standby mode to the operation mode is also followed. The reduction can also effectively suppress the situation of instantaneous large current.

The features of many embodiments are described above in the art. Those having ordinary knowledge can clearly understand the form of the present specification. Those having ordinary skill in the art will appreciate that the objectives of the above-described embodiments and/or advantages consistent with the above-described embodiments can be accomplished by designing or modifying other processes and structures based on the present disclosure. It is also to be understood by those skilled in the art that <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt;

100‧‧‧Logical Circuit

101‧‧‧Reducing components

102‧‧‧First logical unit

103‧‧‧First switching element

104‧‧‧Second logic unit

105‧‧‧Second switching element

106‧‧‧ Third switching element

V _CC ‧‧‧ system voltage

V _IC ‧‧‧First internal supply voltage

S _C ‧‧‧First control signal

S _D ‧‧‧second control signal

S _F ‧‧‧first logic signal

S _G ‧‧‧Second logic signal

Claims (8)

A logic circuit includes: a voltage drop component coupled to a system supply power terminal for providing a first internal supply voltage lower than one of the system voltages according to a system voltage supplied by the system supply power supply; a logic unit receiving the first internal supply voltage and outputting a first logic signal; a first switching element, coupling the first logic unit to a ground node according to a first control signal; and a second switching element Providing the system voltage to the first logic unit according to a second control signal, wherein the second control signal is an inversion of the first control signal; a second logic unit coupled to the ground node and The first logic unit outputs a second logic signal according to the first logic signal; and a third switching element, configured to provide the system voltage to the second logic unit according to the second control signal, wherein the first The logic unit and the second logic unit operate in a standby mode and an operation mode, wherein when operating in In the standby mode, the first control signal is a low logic level, the second switching element and the third switching element are not turned on, and the voltage drop element supplies the first internal supply voltage to the first logic unit, The first switching element stops coupling the first logic unit to the ground node. The logic circuit of claim 1, wherein the voltage drop element The device is an N-type semiconductor, comprising a gate terminal coupled to the supply voltage terminal of the system, a drain terminal coupled to the voltage supply terminal of the system, and a source terminal for providing the first internal supply voltage, wherein the first logic unit is In the inverter, the first switching element is an N-type semiconductor, and includes a gate terminal receiving the first control signal, a drain terminal coupled to the first logic unit, and a source terminal coupled to the ground node. The logic circuit of claim 1, wherein when operating in the operation mode, the first control signal is a high logic level, and the first switching element couples the first logic unit to the ground a node, wherein the second switching element supplies the system voltage to the first logic unit and the third switching element provides the system voltage to the second logic unit. The logic circuit of claim 1, wherein the second switching element is a P-type semiconductor, comprising a gate terminal receiving the second control signal, a 汲 terminal coupled to the first logic unit, and a coupling The second logic unit is an inverter, and the third switching element is a P-type semiconductor, and includes a gate terminal for receiving the second control signal and coupled to the second logic. The extremes of the cell and the source terminal that receives the above system voltage. A logic circuit includes: a voltage drop component coupled to a system supply power terminal for providing a first internal supply voltage lower than one of the system voltages according to a system voltage supplied by the system supply power supply; the complex logic Units, including: a plurality of first logic units receiving the first internal supply voltage; and a plurality of second logic units receiving the system voltage and coupled to a ground node, wherein the first logic unit and the second logic element are alternately connected in series; a first switching element, configured to couple the first logic unit to a ground node according to a first control signal; and a second switching element to selectively supply the system voltage to the first logic unit according to a second control signal The second control signal is an inverse of the first control signal; and a third switching element is configured to provide the system voltage to the second logic unit according to the second control signal, wherein the logic unit is switched to a standby mode and an operation mode, wherein when the standby mode is operated, the first control signal is a low logic level, the second switching element and the third switching element are not turned on, and the voltage drop element provides the foregoing An internal supply voltage to the first logic unit, the first switching element is stopped The first logic unit coupled to the ground node. The logic circuit of claim 5, wherein the voltage drop element is an N-type semiconductor, and the gate terminal is coupled to the gate terminal of the supply voltage terminal of the system, and coupled to the 汲 terminal of the system supply voltage terminal. And providing a source terminal of the first internal supply voltage, wherein the logic unit is a complex inverter, the first switching element is an N-type semiconductor, and the gate terminal including the gate terminal receiving the first control signal is coupled to the above The 汲 terminal of the first logic unit and the source terminal coupled to the ground node. The logic circuit as described in claim 5, wherein when operating on In the operation mode, the first control signal is a high logic level, the first switching element couples the first logic unit to the ground node, and the second switching element provides the system voltage to the first logic The unit and the third switching element described above provide the system voltage to the second logic unit. The logic circuit of claim 5, wherein the second switching element is a P-type semiconductor, comprising a gate terminal receiving the second control signal, a 汲 terminal coupled to the first logic unit, and a coupling The second logic unit is an inverter, and the third switching element is a P-type semiconductor, and includes a gate terminal for receiving the second control signal and coupled to the second logic. The extremes of the cell and the source terminal that receives the above system voltage.