TWI569391B - Circuit structure and method of fabricating the same - Google Patents

Description

Line structure and preparation method thereof

The present invention relates to a copper wire technology, and more particularly to a circuit structure and a method of fabricating the same.

With the evolution of semiconductor technology, the linewidth of the nano generation has been reduced to below tens of nanometers. However, when the width of the copper wire is reduced to several tens of nanometers or less, the grain length in the longitudinal direction is still several tens of nanometers due to the limitation of the inner side wall of the trench, even after annealing, a general bamboo-like structure is formed. The average size of copper crystals is still on the order of tens of nanometers. Under such small grains, the scattering of grain boundaries will increase the electrical resistivity of copper wires, and the electromigration of copper wires will become a serious component operation. problem.

The invention provides a circuit structure, wherein the copper wire located in the trench has low resistivity and good anti-electromigration capability, and has great potential for direct application to the damascene and dual damascene of the microelectronic wafer. On the wire.

The invention further provides a circuit structure capable of improving the electromigration resistance of the copper wire.

The invention further provides a method for preparing a line structure, which can prepare a copper wire having a grain length much larger than a line width in the trench.

The invention further provides a method for preparing a line structure, which can produce a copper wire with good electromigration resistance.

The wiring structure of the present invention includes a substrate and a copper wire. The substrate has at least one trench, and the copper wire is formed in the trench of the substrate. The copper wire is formed by connecting a plurality of crystal grains, wherein more than 20% of the surface area of the copper wire contains crystal grains satisfying a length to line width ratio of 5 or more per die.

In an embodiment of the invention, the line width is between 5 nm and 60 μm.

In an embodiment of the invention, the line width is between 5 nm and 50 nm.

In an embodiment of the invention, the line structure may further include a diffusion barrier layer between the trench and the copper wire.

Another wiring structure of the present invention includes a substrate and a copper wire. The copper wire is formed on the substrate, and the copper wire is formed by connecting a plurality of crystal grains, wherein more than 20% of the surface area of the copper wire contains crystal grains satisfying the length of each crystal grain. The line width ratio is above 5.

In another embodiment of the invention, the line width is between 5 nm and 30 μm.

In another embodiment of the invention, the line width is between 5 nm and 50 nm.

In another embodiment of the invention, the wiring structure may further include a diffusion barrier layer between the substrate and the copper wire.

The method for fabricating the wiring structure of the present invention comprises forming at least one trench in a substrate, forming a nano twin copper film on the substrate, and filling the nano twin crystal copper film into the trench. After the heat treatment, the (111) nano twin copper above the trench disappears and grows into large grains, and the crystal grains of the nano twin crystal film filled in the trench grow in the length direction, and then the trench is removed. The nano twin crystal copper film forms a copper wire.

In still another embodiment of the present invention, a diffusion barrier layer may be formed in the trench before forming the nano twin copper film.

Another method for fabricating a line structure of the present invention comprises forming a patterned mask layer on a substrate, wherein the patterned mask layer has at least one trench, and a nano-double copper film is formed on the patterned mask layer. And filling a copper double crystal copper film into the trench to form a copper wire. The patterned mask layer is then removed and heat treated to grow the copper wire.

In still another embodiment of the present invention, a diffusion barrier and a copper seed layer may be sequentially formed on the surface of the substrate before forming the patterned mask layer.

Based on the above, the present invention can achieve a copper wire having a grain length much larger than the line width by first forming a nano twin copper and then performing a heat treatment, thereby reducing the resistance of the copper wire and making the copper wire have a good copper wire. The ability to resist electromigration.

The above described features and advantages of the invention will be apparent from the following description.

Exemplary embodiments of the inventive concept will be described more fully hereinafter with the drawings of the embodiments. However, the invention may be embodied in a variety of different forms and should not be limited to the following embodiments. In addition, the drawings show the general features of the methods, structures, and/or materials used in the various embodiments, and therefore, the drawings are not to be construed as limiting or limiting the scope or properties covered by the embodiments. For example, the relative thickness and location of the layers, regions, and/or structural elements may be reduced or enlarged for clarity.

1 is a perspective view of a wiring structure in accordance with a first embodiment of the present invention.

In FIG. 1, the wiring structure of the first embodiment includes a substrate 100, and the substrate 100 has a trench 102, such as a single crystal germanium or other semiconductor substrate. Although only one trench 102 is shown in the drawing, the present invention is not limited thereto, and a plurality of trenches may be included in accordance with the circuit design. A copper wire 104 is formed in the trench 102, wherein the copper wire 104 is formed by connecting a plurality of crystal grains 106 to each other, wherein the crystal of the copper wire 104 (from the surface) is more than 20% of the surface area. The particles 106 each satisfy the length L of each of the crystal grains 106 and the line width W ratio of 5 or more; preferably, the crystal grains 106 contained in more than 30% of the surface area of the copper wires 104 satisfy the length L of each of the crystal grains 106. The ratio of the line width W to the ratio of the line width W is more than 5; more preferably, the crystal grains 106 contained in the surface area of the copper wire 104 satisfy the length L of each of the crystal grains 106 and the line width W ratio of 5 or more. In addition, a diffusion barrier layer 108 may be disposed between the trench 102 and the copper wire 104, such as Ti, TiN, TaN, or a combination thereof. In the present embodiment, the line width W is, for example, between 5 nm and 60 μm. For example, in the semiconductor process of the nano generation, the above line width W can be between 5 nm and 500 nm.

2 is a perspective view of a line structure in accordance with a second embodiment of the present invention.

In FIG. 2, the wiring structure of the second embodiment includes a substrate 200 and a copper wire 202, such as a single crystal germanium or other semiconductor substrate. The copper wire 202 is formed on the substrate 200, and the copper wire 202 is formed by connecting a plurality of crystal grains 204 to each other, wherein the copper wire 202 has a grain size of more than 20% of the surface area (observed from the surface). 204 satisfies the ratio of the length L to the line width W of each of the crystal grains 204 of 5 or more; preferably, more than 30% of the surface area of the copper wire 202 (observed from the surface) contains crystal grains 204 satisfying each crystal grain. The length L of the 204 is wider than the line width W by 5 or more; more preferably, the crystal grains 204 included in the surface area of the copper wire 202 (observed from the surface) satisfy the length L and the line width of each of the crystal grains 204. The W ratio is above 5. Although only one copper wire 202 is shown in the drawing, the present invention is not limited thereto, and a plurality of copper wires may be included in accordance with the circuit design. When generally applied to a semiconductor device, an insulating material or a dielectric material may be deposited on the copper wire 202. In addition, a diffusion barrier layer 206 (such as a Ti layer) may be disposed between the surface 200a of the substrate 200 and the copper wire 202. In the present embodiment, the line width W is, for example, between 5 nm and 30 μm; if applied to a semiconductor process of the nano generation, the line width W may be between 5 nm and 500 nm.

3A to 3D are schematic cross sectional views showing a manufacturing process of a wiring structure in accordance with a third embodiment of the present invention.

Referring to FIG. 3A, a trench 302 is formed in a substrate 300. The substrate 300 is, for example, a single crystal germanium or other semiconductor substrate. The method for forming the trench 302 is, for example, a photolithography process.

Then, referring to FIG. 3B, a diffusion barrier layer 304 may be formed in the trench 302, wherein the material of the diffusion barrier layer 304 is, for example, Ti, TiN, TaN or a combination thereof. Then, a nano twin copper film 306a is formed on the substrate 300, and the nano twin copper film 306a is filled into the trench 302. However, if the width of the trench 302 is a small line width nanometer, the nano twin crystal Copper may not be filled in. In the present embodiment, the nano twinned copper film 306a can be formed by direct current or pulse current deposition of nano twin crystal by electroplating, and formed, for example, a nano twin crystal copper film having a preferred direction of <111>. . Taking electroplating as an example, a plating solution such as copper sulfate (copper ion concentration of about 20 g/L to 60 g/L), chloride ion (concentration of about 10 ppm to 100 ppm), and methanesulfonic acid (concentration of about 80 g/L) ~120 g / L), and optionally add other surfactants or lattice conditioners (such as BASF Lugalvan 1 ml / L ~ 100 ml / L). Further, the plating solution may further contain an organic acid (for example, methanesulfonic acid) or gelatin or the like.

Subsequently, referring to FIG. 3C, heat treatment 308 is performed. After the heat treatment, the twin crystals will disappear, and the copper crystal grains will grow to become the copper film 306b, and the long crystal grains having a grain length to line width ratio of 5 or more may be (100) Preferred direction or no preferred direction.

The copper film above the trench 302 mostly grows into a large crystal grain, and the crystal grains of the nano-double-crystal copper film 306a filled in the trench 302 grow in the longitudinal direction to form larger crystal grains and are formed from copper wires (as shown in FIG. 1). The crystal grains contained in 20% or more of the surface area of the surface observation satisfy the grain length to line width ratio of 5 or more. In the present embodiment, the temperature of the heat treatment 308 is between about 200 ° C and 450 ° C for about 0.2 hours to 1 hour.

Then, referring to FIG. 3D, the copper film (306b of FIG. 3C) other than the trench 302 is removed, and the copper wire 310 is formed. In the present embodiment, a method of removing the copper film, such as electrolytic polishing or chemical mechanical polishing, is employed.

4A through 4C are schematic cross-sectional views showing a manufacturing process of a wiring structure in accordance with a fourth embodiment of the present invention.

Referring first to FIG. 4A, a patterned mask layer 402 is formed on a substrate 400, wherein the patterned mask layer 402 has a trench 404. The substrate 400 is, for example, a single crystal germanium or another semiconductor substrate, and the patterned mask layer 402 is, for example, a photoresist, so that the trench 404 can be formed via a lithography process. Before this step, a diffusion barrier layer 406 and a copper seed layer 408 may be sequentially formed on the surface of the substrate 400, wherein the diffusion barrier layer 406 is, for example, a Ti layer or a TiW layer. Although the copper seed layer 408 in this figure is only located in the trench 404, the copper seed layer 408 can also be formed entirely on the substrate 400, and unnecessary portions can be removed in subsequent processes.

Then, referring to FIG. 4B, a nano-double crystal copper film 410 is formed in the trench 404 of the patterned mask layer 402. In the present embodiment, the nano-double-crystal copper film 410 can be fabricated by performing a direct current or pulse current deposition nano twin crystal by a copper seed layer 408 by electroplating, and can refer to the process of the third embodiment, so that Narration.

Subsequently, referring to FIG. 4C, the patterned mask layer 402 is removed, and the diffusion barrier layer 406 and the copper seed layer 408 (not required outside the trench 404) can be simultaneously removed. Thereafter, heat treatment 412 is performed to crystallize the nanocrystalline copper film (410 of FIG. 4B) to form a copper wire 414 having a larger crystal grain, and more than 20% of the surface area observed from the surface of the copper wire 414 is contained. The crystal grains all satisfy the grain length to line width ratio of 5 or more. In the present embodiment, the temperature of the heat treatment 412 is between about 400 ° C and 450 ° C for about 0.5 hours to 1 hour. After the heat treatment, the twin crystals will disappear, and the copper crystal grains will grow, and the long crystal grains having a crystal grain length to a line width ratio of 5 or more may have a (100) preferred direction or no preferred direction.

Several experimental examples and comparative examples are listed below to confirm the efficacy of the present invention, but the scope of the present invention is not limited to the following.

<Experimental Example 1>

First, several trenches are fabricated in the germanium wafer, with a trench depth of about 123 nm and a trench width of about 65 nm. Then, a 10 nm thick Ti diffusion barrier layer was formed in the trench by sputtering.

Then, by means of electroplating, direct current electrodeposited nano twin crystals are used to fabricate nano twin copper on the germanium wafer, wherein the electrolyte is a high purity copper sulfate (CuSO ₄ ) solution with a suitable surfactant and 40 ppm. Hydrogen chloride (HCl) was used as a cathode with a 99.99% high purity copper sheet. The direct current was applied at a current density of 0.08 A/cm ² and stirred at 800 rpm by adding a rotating magnet, and a nanocrystalline copper film having a thickness of about 10 μm and having a preferred direction of <111> was electroplated, as shown in FIG.

Then, after heat treatment at 400 ° C for 30 minutes, the nano twin crystals disappear and grow to form large crystal grains having a diameter of about 300 μm as shown in FIG. 6 .

Since the grain growth causes the copper crystal grains in the trench to also grow, a copper wire having a crystal grain length of about 480 nm and a line width of about 65 nm can be observed according to the plan view of FIG. 7, and the lower portion is obtained by TEM bright field and diffraction of the selected region. The diffraction pattern confirms that the copper wire of Figure 7 is a single grain of copper.

<Experimental Example 2>

A copper wire was produced in the same manner as in Experimental Example 1, except that the groove width in the germanium wafer was 2 μm, and the resultant structure is shown in Fig. 8. From the plan view of Fig. 8, a copper wire having a crystal grain length of about 36 μm and a line width of about 2 μm can be observed.

<Experimental Example 3>

A titanium-titanium (TiW) layer with a thickness of about 1200 nm was sputtered on the bottom of the germanium wafer as an adhesion layer, and a 200 nm thick copper crystal was sputtered on the adhesion layer by Oerlikon ClusterLine 300 (OC Oerlikon Corporation AG, Pfäffikon, Switzerland). Layer. Then, a photoresist layer is coated thereon, and a plurality of trenches are formed in the photoresist layer by a lithography process, and the trench width is about 15 μm.

Then, by means of electroplating, direct current electrodeposited nano twin crystals are applied to grow nano twin copper in the trenches on the germanium wafer. In a detailed manner, a high-purity copper sulfate (CuSO ₄ ) solution is added with a suitable surfactant and 40 ppm of hydrogen chloride (HCl) as an electrolyte, and a 99.99% high-purity copper piece is used as a cathode to grow the rotation of the nano-bis-crystal copper. The rate is 600 rpm and the current density is 50 mA cm ^-2 . The experimental period is T _on = 0.02 s and T _off = 1.5 s. The deposition rate was 1.2 nm s ^-1 .

Thereafter, the photoresist layer, the copper seed layer, and the titanium-tungsten layer were removed, and then heat-treated at 400 ° C for 30 minutes to allow the nano twin crystal to disappear and crystal grains to grow to form large crystal grains, and the obtained structure is shown in FIG. A copper wire having a crystal grain length of about 520 μm and a line width of about 15 μm can be observed from the plan view of Fig. 9.

<Experimental Example 4>

A copper wire was produced in the same manner as in Experimental Example 3, but the width of the trench formed by the photoresist layer on the germanium wafer was 35 μm, and the resultant structure is shown in Fig. 10. A copper wire having a crystal grain length of about 440 μm and a line width of about 35 μm can be observed from the plan view of Fig. 10.

<Experimental Example 5>

A copper wire was produced in the same manner as in Experimental Example 3, but the width of the trench formed on the photoresist layer on the germanium wafer was 50 μm, and the resultant structure is shown in Fig. 11. From the plan view of Fig. 11, a copper wire having a crystal grain length of about 400 μm and a line width of about 50 μm can be observed.

In summary, the copper wire of the present invention has a grain length much larger than the line width, so that the grain boundary can be greatly reduced and thus the copper wire has low electrical resistivity and good resistance to electromigration, and is particularly suitable for the nano generation. Semiconductor component.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100, 200, 300, 400‧‧‧ substrates
102, 302, 404‧‧‧ Ditch
104, 202, 310, 414‧‧‧ copper wire
106, 204‧‧‧ grain
108, 206, 304, 406‧‧ ‧ diffusion barrier
200a‧‧‧ surface
306a, 410‧‧‧Nano double crystal copper film
306b‧‧‧ copper film
308, 412‧‧‧ heat treatment
408‧‧‧ copper seed layer
Length of L‧‧‧ grain
W‧‧‧Line width

1 is a perspective view of a wiring structure in accordance with a first embodiment of the present invention. 2 is a perspective view of a line structure in accordance with a second embodiment of the present invention. 3A to 3D are schematic cross sectional views showing a manufacturing process of a wiring structure in accordance with a third embodiment of the present invention. 4A through 4C are schematic cross-sectional views showing a manufacturing process of a wiring structure in accordance with a fourth embodiment of the present invention. 5 is a focused ion beam image (FIB) diagram of a cross section of a nano twin copper film in Experimental Example 1. FIG. Fig. 6 is a FIB image of the nanocrystalline copper film after heat treatment in Experimental Example 1. Fig. 7 is a plan view of a through-hole electron image of a copper wire in Experimental Example 1. Fig. 8 is a plan FIB image of the copper wire in Experimental Example 2. Fig. 9 is a plan FIB image of the copper wire in Experimental Example 3. Fig. 10 is a plan FIB image of a copper wire in Experimental Example 4. Figure 11 is a plan FIB image of a copper wire in Experimental Example 5.

100‧‧‧Substrate

102‧‧‧ Ditch

104‧‧‧ copper wire

106‧‧‧ grain

108‧‧‧Diffusion barrier

Length of L‧‧‧ grain

W‧‧‧Line width

Claims (12)

A circuit structure comprising: a substrate having at least one trench; and a copper wire formed in the trench of the substrate, wherein the copper wire is formed by connecting a plurality of crystal grains, wherein the copper wire The crystal grains contained in more than 20% of the surface area satisfy the length to line width ratio of each of the crystal grains of 5 or more. The line structure as described in claim 1, wherein the line width is between 5 nm and 60 μm. The line structure as claimed in claim 1, wherein the line width is between 5 nm and 500 nm. The circuit structure of claim 1, further comprising a diffusion barrier layer between the trench and the copper wire. A circuit structure comprising: a substrate; and a copper wire formed on the substrate, wherein the copper wire is formed by connecting a plurality of crystal grains, wherein more than 20% of the surface area of the copper wire is included The grains all satisfy the length to line width ratio of each of the crystal grains of 5 or more. The line structure as described in claim 5, wherein the line width is between 5 nm and 30 μm. The line structure as described in claim 5, wherein the line width is between 5 nm and 50 nm. The circuit structure of claim 5, further comprising a diffusion barrier layer between the substrate and the copper wire. A method for preparing a line structure according to claim 1, comprising: forming at least one trench in a substrate; forming a nano twin crystal copper film on the substrate, and forming the nano twin crystal copper film Filled into the trench; heat treatment, the (111) nano twin copper above the trench disappears and the grain grows, and the crystal of the nano twinned copper film filled in the trench grows in the length direction And removing the copper film outside the trench to form a copper wire. The preparation method of claim 9, wherein before forming the nano twin copper film, further comprising: forming a diffusion barrier layer in the trench. A method for fabricating a circuit structure according to claim 5, comprising: forming a patterned mask layer on a substrate, wherein the patterned mask layer has at least one trench; and forming in the at least one trench a nanocrystalline copper film, and the nanocrystalline copper film is filled into the trench; the patterned mask layer is removed; and heat treatment is performed to grow crystal grains of the nano twin crystal film to form Copper wire. The preparation method of claim 11, wherein before forming the patterned mask layer, the method further comprises: forming a diffusion barrier layer and a copper seed layer on the surface of the substrate.