TWI569376B - Static random access memory unit cell structure and static random access memory unit cell layout structure - Google Patents

Description

Static random access memory cell structure and static random access memory cell Layout structure

The present invention relates to a memory structure, and more particularly to a static random access memory cell structure and its layout structure.

A static random access memory (SRAM) device includes a logic circuit and a static random access memory cell unit connected to the logic circuit. In the conventional memory cell structure process, due to the influence of the yellow light process limit, a metal-zero interconnect (which is often in the vertical direction) above the contact (which is often in the vertical direction) ), which is defined in the longitudinal direction of the line length) and the zero-thick metal line across the contact window and the gate line (which is often in the horizontal direction, which is relative to the length of the line) In the longitudinal direction of the foregoing definition, the fabrication must be performed by two microlithography and etching processes, respectively, followed by plating a metal layer into the trench, and then plating a metal layer into the trench. This is done by a chemical mechanical polishing (CMP) process. In other words, in the process, the grooves in the longitudinal direction must be formed by one lithography and etching process, and the grooves in the lateral direction are formed by another lithography and etching process. At the intersection of the longitudinal and lateral directions, that is, where the etching position is repeated, such a position is subjected to secondary etching corrosion, so that local corrosion is invaded to the depth of the substrate, which may be referred to as a stitch. In poorer conditions, such as when such an aggressive nest recess reaches the diffusion of the substrate, junction leakage can be caused, resulting in a decrease in SRAM fabrication yield. This effect is particularly pronounced in substrates using SiGe technology.

Therefore, there is still a need for a novel SRAM cell structure to avoid the problem of junction leakage current as described above.

An object of the present invention is to provide a static random access memory cell structure and a layout structure thereof, which can solve the above problems.

According to an embodiment of the present invention, the present invention provides a static random access memory cell layout structure including a semiconductor substrate, a first gate line, and a first elongated contact contact. . The semiconductor substrate includes a first active area and a second active area parallel to the first active area. The first gate line passes through the first active area and the second active area. The first elongate contact window is disposed on the first active area and the second active area on one side of the first gate line.

According to another embodiment of the present invention, the present invention provides a static random access memory cell structure including a first inverter, a second inverter, a first elongated contact window, and a first A di-shaped contact window, a first zero-level metal wire, and a second zero-thick metal wire. The first inverter includes a first pull-down transistor and a first pull-up transistor. The second inverter includes a second pull-down transistor and a second pull-up transistor. The first elongate contact window spans the drain of the first pull-down transistor and the drain of the first pull-up transistor. The first zero-thick metal wire is placed across the first elongated contact window and the gate line of the second pull-up transistor. The second elongated contact window spans the drain of the second pull-down transistor and the drain of the second pull-up transistor. The second zero-thick metal wire is placed across the second elongated contact window and the gate line of the first pull-up transistor.

The term "zeroth metal wiring" as used herein means that it is located in the interlayer dielectric layer. A metal line formed by the zeroth metal layer (M0). It will be explained in detail later.

Therefore, in the static random access memory cell structure according to the present invention, there is no intersection of the longitudinal and lateral zero-thick metal wires, and there is no corrosion in the same etching process of the substrate at the same place. Avoid the above-mentioned erosion of the nailing area is too deep to cause junction leakage current.

10‧‧‧Static Random Access Memory Unit

12‧‧‧First pull-up crystal

14‧‧‧Second pull-up crystal

16‧‧‧First pull-down transistor

18‧‧‧Second pull-down transistor

20‧‧‧First access transistor

22‧‧‧Second access transistor

24, 26‧‧‧ storage node

28, 30‧‧‧ series circuit

32‧‧‧Voltage source

34‧‧‧Grounding wire

36‧‧‧ character line

38‧‧‧ bit line

40‧‧‧First Inverter

42‧‧‧Second inverter

44‧‧‧Static random access memory cell layout structure

46‧‧‧Semiconductor substrate

47‧‧‧Isolation structure

48, 48'‧‧‧ first gate line

50, 50'‧‧‧ first long contact window

51‧‧‧First interlayer dielectric layer

52, 52'‧‧‧First active area

53‧‧‧Second interlayer dielectric layer

54‧‧‧Second active area

55‧‧‧First groove

56‧‧‧ Third active area

57‧‧‧Second trench

58, 58'‧‧‧ fourth active area

59, 85‧‧‧ trench

60, 60'‧‧‧ second gate line

61, 67‧‧‧ hard mask

62, 62'‧‧‧Second long contact window

63‧‧‧Photoresist layer

64, 64'‧‧‧ first zero-layer metal connection

65, 71, 73‧‧‧ openings

66‧‧‧Second zero-thick metal connection

68‧‧‧3rd gate line

69‧‧‧Photoresist layer

70‧‧‧fourth gate line

72‧‧‧Word line connection pad

74‧‧‧ bit line contact window

76‧‧‧ bit line connection pad

78‧‧‧Long earthing electrode contact window

80‧‧‧Ground electrode connection pad

81‧‧‧ third trench

82, 84‧‧‧ Grounding electrode contact window

83‧‧‧Layer 3 interlayer dielectric layer

86‧‧‧Medium hole

88‧‧‧First metal interconnect

90, 92, 96, 96', 98‧‧ ‧ bungee

91, 91', 94‧‧‧ source

AA', BB', CC'‧‧‧ hatching

FIG. 1 is a schematic circuit diagram of a SRAM cell according to an embodiment of the invention.

FIG. 2 is a diagram showing a layout structure of a static random access memory cell according to an embodiment of the invention.

Figure 3 is a schematic cross-sectional view along line AA' of Figure 2.

Fig. 4 is a schematic cross-sectional view along line BB' of Fig. 2.

Figure 5 is a schematic cross-sectional view along line CC' of Figure 2.

FIG. 6 is a diagram showing a layout structure of a static random access memory cell according to another embodiment of the present invention.

Figure 7 is a schematic cross-sectional view along line CC' of Figure 6.

8 and 9 illustrate a method of fabricating a static random access memory cell structure in accordance with an embodiment of the present invention.

Please refer to FIG. 1. FIG. 1 is a circuit diagram of a SRAM cell according to an embodiment of the present invention, which is mainly presented by a transistor. The SRAM cell 10 is a six-transistor SRAM (6T-SRAM) including a first pull-up transistor 12 and a second pull-up transistor 14, A pull-down transistor 16 and a second pull-down transistor 18 and a first access transistor 20 And a second access transistor 22, wherein the first pull-up transistor 12 and the second pull-up transistor 14 and the first pull-down transistor 16 and the second pull-down transistor 18 form a latch circuit for making data It can be latched on a storage node 24 or 26. The gate that accesses the transistor can also be referred to as a passing gate.

In general, the first pull-up transistor 12 and the second pull-up transistor 14 of the 6T-SRAM memory cell 10 are p-type field effect transistors (pFETs), such as PMOSFETs; and the first pull-down transistor 16, The second pull-down transistor 18, the first access transistor 20, and the second access transistor 22 are then n-type field effect transistors (nFETs), such as nMOSFETs. The first pull-up transistor 12 and the first pull-down transistor 16 constitute a first inverter 40, and the two ends of the series circuit 28 are electrically connected to a supply voltage source, such as a voltage. The source (V _CC ) 32 and the ground line (V _SS ) 34; similarly, the second pull-up transistor 14 and the second pull-down transistor 18 constitute the second inverter 42 , and the two are connected in series The two end points are also electrically connected to a supply voltage source, such as a voltage source 32 and a ground line 34, respectively.

At the storage node 24, a gate of the second pull-down transistor 18 and the second pull-up transistor 14 and a first pull-down transistor 16, a first pull-up transistor 12, and an access transistor are electrically connected, respectively. 20 bungee jumping. Similarly, the storage node 26 is also electrically connected to the first pull-down transistor 16 and the gate of the first pull-up transistor 12, and the second pull-down transistor 18, the second pull-up transistor 14 and the memory. The drain of the transistor 22 is taken. The gates of the access transistors 20 and 22 are electrically connected to the word line 36, and the sources of the access transistors 20 and 22 are electrically connected to the corresponding bit lines, respectively. Line) 38.

For the static random access memory cell layout structure according to an embodiment of the present invention, the circuit shown in FIG. 1 can refer to FIG. 2; the third to fifth graphs respectively show AA' and BB' in FIG. , CC' line is a schematic cross-sectional view to further show the static random access memory Unit structure.

A static random access memory cell layout structure according to an embodiment of the present invention will be described below with reference to FIGS. 1 to 5. The SRAM cell layout structure 44 includes a semiconductor substrate 46, a first gate line 48, and a first elongate contact window 50. The semiconductor substrate 46 includes a first active region 52 and a second active region 54 that is parallel to the first active region 52. The first gate line 48 passes through the first active region 52 and the second active region 54. The first elongated contact window 50 is disposed on the first active region 52 and the second active region 54 on one side of the first gate line 48, as shown in FIGS. 2 and 3.

Therefore, the first pull-down transistor 16 as shown in FIG. 1 may include a gate formed by the first gate line 48 and a pair of drains 90 in the first active region 52 on the two sides of the gate. The first pull-up transistor 12 may include a gate formed by the first gate line 48 and a pair of drains 92 and sources 94 in the second active region 54 on the two sides of the gate. The first elongated contact window 50 acts as a node contact.

In the SRAM cell layout structure 44, the semiconductor substrate 46 may further include a third active region 56 and a fourth active region 58 that are parallel to the second active region 54. The second active area 54 is located between the first active area 52 and the third active area 56, and the third active area 56 is located between the second active area 54 and the fourth active area 58. The SRAM cell layout structure 44 can also include a second gate line 60 and a second elongate contact window 62. The second gate line 60 passes through the third active region 56 and the fourth active region 58. The second elongated contact window 62 spans the third active region 56 and the fourth active region 58 on one side of the second gate line 60, as shown in FIGS. 2 and 3. Each active region is electrically isolated by an isolation structure 47 such as a shallow trench isolation (STI).

Therefore, the second pull-down transistor 18 as shown in FIG. 1 may include a gate formed by the second gate line 60 and a pair of drain electrodes 96 and sources in the fourth active region 58 on the two sides of the gate. The second pull-up transistor 14 may include a gate formed by the second gate line 60 and a pair of drains 98 and sources in the third active region 56 on the two sides of the gate. The second elongated contact window 62 serves as a node contact window.

The SRAM cell layout structure 44 can also include a first zeroth metal interconnect 64 and a second zero metal interconnect 66. The first zero-thick metal connection 64 spans the first elongated contact window 50 and the second gate line 60, as shown in Figures 2 and 4. The second zero-thick metal connection 66 spans the second elongated contact window 62 and the first gate line 48.

As shown in FIG. 2, in order to tightly configure the structure, the first elongate contact window 50 and the second elongate contact window 62 may be disposed substantially in a straight line.

The SRAM cell layout structure 44 can also include a third gate line 68 and a fourth gate line 70. The third gate line 68 passes through the first active region 52 on one side of the first gate line 48 to form the access transistor 20 as shown in FIG. 1; the side and the first elongated contact window 50 on the same side. The first elongated contact window 50 is located between the first gate line 48 and the third gate line 68. The fourth gate line 70 passes through the fourth active region 58 on one side of the second gate line 60 to form the access transistor 22 as shown in FIG. 1; the side and the second elongated contact window 62 on the same side. The second elongated contact window 62 is located between the second gate line 60 and the fourth gate line 70. As shown in Figure 2.

The first elongated contact window 50 forms a local interconnect with the first zero-thick metal connection 64, that is, the gates of the second pull-down transistor 18 and the second pull-up transistor 14, and a pull-down transistor 16, a first pull-up transistor 12, and an access transistor 20 The 汲 is electrically connected to the storage node 24. The second elongated contact window 62 forms a regional inner connection with the second zero-thick metal connection 66, that is, the gate of the first pull-down transistor 16 and the first pull-up transistor 12, and the second pull-down The crystal 18, the second pull-up transistor 14 and the drain of the access transistor 22 are electrically connected to form the storage node 26.

The SRAM cell layout structure 44 can also include a word line connection pad 72 that is coupled to the fourth gate line 70, as shown in FIG. A dielectric hole may be disposed on the word line connection pad 72 to be electrically connected to the word line 36.

The SRAM cell layout structure 44 may also include a bit line contact window 74 that is coupled to a fourth active region 58 located on the other side of the fourth gate line 70. The SRAM cell layout structure 44 may also include a bit line connection pad 76 that is located on the bit line contact window 74. A dielectric hole may be disposed on the bit line connection pad 76 to be electrically connected to the bit line 38.

As shown in Figures 2 and 5, the SRAM cell layout structure 44 can also include a slot form ground electrode contact window 78 that is first active on the other side of the first gate line 48. The area 52 extends over an active area 52' of the adjacent SRAM cell layout structure. The ground electrode connection pad 80 is located on the elongated ground electrode contact window 78. The ground electrode connection pad 80 can be electrically connected to a voltage source such as the ground line 34. In this embodiment, since the shape of the elongated ground electrode contact window 78 is large, the operation window of the process can be large.

2 and 5 show the case of the elongated ground electrode contact window 78 extending across the isolation structure 47, connecting the first active region 52 of one unit structure (drain 91) with the active region 52' of another unit structure (汲Extreme 91'), but not limited to this. Figures 6 and 7 show a pair of split ground electrode contact windows 82 and 84, respectively located on the other side of the first gate line 48. The area 52 (dip pole 91) and the active area 52' (drain 91') of the adjacent static random access memory cell layout structure. A ground electrode connection pad 80 is placed across the pair of separate ground electrode contact windows 82 and 84.

The SRAM cell layout structure 44 can also include a dielectric via 86 on the ground electrode connection pad 80 and a first layer of metal interconnects 88 on the dielectric via 86.

It may be noted that, according to an embodiment of the present invention, the layout structure of the memory cell array of the SRAM may include a plurality of SRAM cell structures as described above, but adjacent The two unit structures are mirror images of each other.

A static random access memory cell structure in accordance with another embodiment of the present invention will now be described with reference to Figs. The static random access memory cell structure includes a first inverter 40, a second inverter 42, a first elongated contact window 50, a second elongated contact window 62, a first zero-thick metal connection 64, and The second zero-thick metal connection 66. The first inverter 40 includes a first pull-down transistor 16 and a first pull-up transistor 12. For example, the first pull-down transistor 16 includes a gate formed by the first gate line 48 and a pair of drains 90 and sources in the first active region 52 on the two sides of the gate; The crystal 12 includes a gate formed by the first gate line 48 and a pair of drains 92 and sources 94 in the second active region 54 on both sides of the gate (refer to FIG. 4 together). The second inverter 42 includes a second pull-down transistor 18 and a second pull-up transistor 14. For example, the second pull-down transistor 18 includes a gate formed by the second gate line 60 and a pair of drain electrodes 96 and sources in the fourth active region 58 on the two sides of the gate; a second pull-up transistor 14 includes a gate formed by the second gate line 60 and a pair of drains 98 and sources in the third active region 56 on the two sides of the gate.

The first elongated contact window 50 spans over the drain 90 of the first pull-down transistor 16 and The first pull-up transistor 12 is on the drain 92. The first zero-layer metal trace 64 spans over the first elongated contact window 50 and the gate line 60 of the second pull-up transistor. The second elongated contact window 62 spans over the drain 96 of the second pull-down transistor 18 and the drain 98 of the second pull-up transistor 14. The second zero-thick metal trace 66 spans over the second elongated contact window 62 and the first gate line 48 of the first pull-up transistor 12.

The upper surface of the first elongated contact window 50 may be substantially the same height as the upper surface of the second gate line 60 of the second pull-up transistor 14 or slightly higher than the upper surface of the second gate line 60. In addition, the upper surface of the second elongated contact window 62 may be substantially the same as the upper surface of the first gate line 48 of the first pull-up transistor 12 or slightly higher than the upper surface of the first gate line 48. In addition, the gate line of the first pull-down transistor 16 and the gate line of the first pull-up transistor 12 are formed by the same first gate line 48. In addition, the gate line of the second pull-down transistor 18 and the gate line of the second pull-up transistor 14 are formed by the same second gate line 60.

Structurally, referring to Figures 2 and 5, the SRAM cell structure 44, as described above, can also include an elongated ground electrode contact window 78 that spans the source of the first pull down transistor 16. The source 91' of the first pull-down transistor on the pole 91 and the adjacent other SRAM cell structure. Additionally, there may be a ground electrode connection pad 80 located on the elongated ground electrode contact window 78. Alternatively, please refer to Figures 6 and 7, which may include a pair of separate ground electrode contact windows 82 and 84, respectively located on the source 91 of the first pull-down transistor 16 and adjacent another static random access memory. The source of the first pull-down transistor on the source 91'. Additionally, there may be a ground electrode connection pad 80 that is placed across the pair of separate ground electrode contact windows 82 and 84. Further, as shown in FIGS. 5 and 7, the dielectric hole 86 may be located on the ground electrode connection pad 80. Additionally, a first layer of metal interconnects 88 may be located on the dielectric apertures 86.

In this paper, as the general method, the first metal layer (Metal-1, M1) and the upper layer a dielectric layer between the metal layers of the second metal layer (Metal-2, M2) or above, referred to as an inter-metal dielectric (IMD), and Can be subdivided into, for example, IMD1, IMD2, IMD3, etc., for example, M1 is located in IMD1, M2 is located in IMD2, and so on; and, dielectric between the first metal layer (M1) and the substrate The layer is called an interlayer dielectric (ILD), and the metal layer in the interlayer dielectric layer is called a zeroth metal layer (Metal-0, M0). As used herein, "zeroth metal wiring" means a metal wiring formed by a zeroth metal layer in an interlayer dielectric layer. Further, in the present invention, a dielectric hole may be further formed in the interlayer dielectric layer, which may be referred to as a zeroth dielectric hole (Via-0). Therefore, the interlayer dielectric layer can be segmented to be defined, for example, as illustrated by the cross-sectional schematic diagrams shown in FIGS. 4, 5, and 7, about the gate of the transistor (for example, the gate shown in FIG. 4). The line 60, 48, 48', 60') is the first interlayer dielectric layer (ILD-1) 51; the zeroth metal layer (for example, the zeroth layer metal layer formed by the zeroth metal layer) Lines 64, 64', ground electrode connection pads 80) are in the second interlayer dielectric layer (ILD-2) 53; Via-0 (eg, dielectric holes 86) are in the third interlayer dielectric layer (ILD-3) 83. In this example, the third interlayer dielectric layer 83 is over M1 (eg, the first metal interconnect 88 formed by M1), and M1 is in IMD1.

In still another embodiment of the present invention, the present invention also provides a method of fabricating a static random access memory cell structure, comprising the following steps. First, a semiconductor substrate is provided. Next, a first inverter is formed on the semiconductor substrate, and includes a first pull-down transistor and a first pull-up transistor. A second inverter is formed on the semiconductor substrate, and includes a second pull-down transistor and a second pull-up transistor. The first inverter and the second inverter are located in a first interlayer dielectric layer. Then, a first elongated contact window is formed in the first interlayer dielectric layer, and electrically connected to the drain of the first pull-down transistor and the drain of the first pull-up transistor, and between the first layer A second elongated contact window is formed in the dielectric layer, and is electrically connected to the drain of the second pull-down transistor and the drain of the second pull-up transistor. A second interlayer dielectric layer is formed covering the first inverter, the second inverter, and the first interlayer dielectric layer. Then, carry out a first The lithography and etching process forms a first trench and a second trench in the second interlayer dielectric layer. The first trench exposes a first elongated contact window located above the drain of the first pull-up transistor and a gate line of the second pull-up transistor. The second trench exposes a second elongated contact window located above the drain of the second pull-up transistor and a gate line of the first pull-up transistor. Then, a first zero-layer metal layer is formed in the first trench and the second trench, and a first zero-thick metal wiring is respectively formed to electrically connect the first elongated contact window and the second pull-up transistor. a gate line, and a second zero-thick metal line to electrically connect the second elongated contact window with the gate line of the first pull-up transistor.

In detail, please refer to FIGS. 2 to 5 together. The present invention provides a method for fabricating a static random access memory cell structure, including the following steps. First, a semiconductor substrate 46 is provided. Next, a first inverter 40 is formed on the semiconductor substrate 46, which includes a first pull-down transistor 16 and a first pull-up transistor 12. A second inverter 42 is formed on the semiconductor substrate 46, which includes a second pull-down transistor 18 and a second pull-up transistor 14. The first inverter 40 and the second inverter 42 are located in the first interlayer dielectric layer 51. Then, a first elongated contact window 50 is formed in the first interlayer dielectric layer 51, and electrically connected to the drain 90 of the first pull-down transistor 16 and the drain 92 of the first pull-up transistor 12, And forming a second elongated contact window 62 electrically connected to the drain 96 of the second pull-down transistor 18 and the drain 98 of the second pull-up transistor 14. A second interlayer dielectric layer 53 is formed which covers the first inverter 40, the second inverter 42, and the first interlayer dielectric layer 51.

Then, a second lithography and etching process is performed on the second interlayer dielectric layer 53 to form a first trench 55 exposing the first elongated contact window located above the drain 92 of the first pull-up transistor 12. 50 and the second gate line 60 of the second pull-up transistor 14, and forming a second trench 57 exposing the second elongated contact window 62 located above the drain 98 of the second pull-up transistor 14 The first gate line 48 of the first pull-up transistor 12. Then, the first trench 55 and the second trench 57 are filled with the zero-th metal layer, and the first zero-thick metal wiring 64 is respectively formed to be electrically Connecting the first elongated contact window 50 with the second gate line 60 of the second pull-up transistor 14, and forming the second zero-thick metal wiring 66 to electrically connect the second elongated contact window 62 with the first upper The first gate line 48 of the transistor 12 is pulled.

Wherein, as described above, the upper surface of the first elongated contact window 50 may be substantially the same height as the upper surface of the second gate line 60 of the second pull-up transistor 14; or the first elongated contact window 50 may be made The upper surface is slightly higher than the upper surface of the second gate line 60. This is because after the gate line is formed, a thin dielectric layer can be formed first, and then the trench of the elongated contact window is formed. The upper surface of the resulting elongated contact window will be slightly higher than the upper surface of the gate line. Similarly, the upper surface of the second elongated contact window 62 may be substantially the same height as the upper surface of the first gate line 48 of the first pull-up transistor 12; or the upper surface of the second elongated contact window 62 may be The surface is slightly above the upper surface of the first gate line 48. In addition, the gate line of the first pull-down transistor 16 and the gate line of the first pull-up transistor 12 may be formed by the same first gate line 48. In addition, the gate line of the second pull-down transistor 18 and the gate line of the second pull-up transistor 14 may be formed by the same second gate line 60.

Further, as shown in FIGS. 2 and 5, the following steps may be further included. While forming the first elongated contact window 50, an elongated ground electrode contact window 78 is formed in the first interlayer dielectric layer 51, respectively on the source 91 of the first pull-down transistor 16 and adjacent thereto. Another static random access memory cell structure is on the source 91' of the first pull down transistor. A second lithography and etching process is additionally performed on the second interlayer dielectric layer 53 to form a third trench 81 that exposes the elongated ground electrode contact window 78. In addition, the third trench 81 is filled with a zero-th metal layer to form a ground electrode connection pad 80 on the elongated ground electrode contact window 78.

Alternatively, the shape of the ground electrode contact window may be a separate pair, as shown in Figures 6 and 7, in this embodiment, the following steps are included. The same as forming the first elongated contact window 50 A pair of separate ground electrode contact windows 82 and 84 are formed in the first interlayer dielectric layer 51, respectively on the source 91 of the first pull-down transistor 16 and adjacent another static random access memory. The source cell structure is on the source 91' of the first pull-down transistor. A second lithography and etching process is additionally performed on the second interlayer dielectric layer 53 to form a third trench 81 that exposes the pair of separate ground electrode contact windows 82 and 84. In addition, the third trench 81 is filled with the zero-th metal layer to form a ground electrode connection pad 80, which is placed across the pair of separate ground electrode contact windows 82 and 84 across the first interlayer dielectric layer 51.

Additionally, the method of fabricating a static random access memory cell structure can further include the following steps. A third interlayer dielectric layer 83 is formed to cover the first zero-thick metal wiring 64, the second zero-thick metal wiring 66, and the ground electrode connection pad 80. The formation dielectric hole 86 is located on the ground electrode connection pad 80 and penetrates the third interlayer dielectric layer 83. A first layer of metal interconnects 88 is formed over the dielectric holes 86.

In the above method for fabricating a static random access memory cell structure, each component can be fabricated by referring to or using conventional materials and methods of formation. For example, the gate line can include a suitable conductive material such as polysilicon or metal germanide or appropriate. Metal materials, such as aluminum or tungsten, may also include high-k materials and work function metals (such as titanium nitride (TiN) for forming pFETs if they are metal gate lines. Titanium aluminide (TiAl) for forming an nFET; the contact window may comprise a suitable conductive material such as tungsten or copper; the zeroth layer or the first metal layer may comprise a suitable conductive material such as aluminum, copper or tungsten, for example The zero metal layer (M0) is made of tungsten, and the first metal layer (M1) is made of copper, but the invention is not limited thereto.

It is worth noting that the horizontal zero-thick metal connection and the longitudinal zero-thick metal connection (or pad) are separately subjected to secondary lithography and etching processes to form trenches, refill metal materials or conductive Materials to make. For example, please refer to Figure 8 for the first lithography and etching process. During the process, a hard mask 61 is formed on the second interlayer dielectric layer 53, and a patterned photoresist layer 63 is formed on the hard mask 61, and has an opening 65. The hard mask 61 is patterned by the opening 65. The photoresist layer 63 is removed, and the second interlayer dielectric layer 53 is etched through the patterned hard mask 61 to form a first trench 55, a second trench 57, and a terminal pad for forming, for example, a word line. Groove 59. When a second lithography and etching process is required for forming a longitudinal zero-thick metal wiring (or pad), as shown in FIG. 9, the formed trench can be covered using, for example, a hard mask 67. A patterned photoresist layer 69 is formed on the hard mask 67, having openings 71 and 73, and the hard mask 67 is patterned by the openings 71 and 73 to remove the photoresist layer 69 via the patterned hard mask 67. The second interlayer dielectric layer 53 is etched to form a third trench 81 and a trench 85 for forming, for example, a voltage source connection pad. The hard mask 67 is removed to expose the grooves. Filling the trenches with a zero-thick metal layer, for example, by conventional sputtering, performing a CMP process to remove excess metal layer portions and planarizing, thereby obtaining a zero-thick metal connection of each lateral and longitudinal shape. Or connect the pads. The order in which the grooves of the lateral and longitudinal shapes are made is not limited.

One of the features of the present invention is that the elongated contact window is connected across the isolation structure to connect the drain of the first pull-down transistor with the drain of the first pull-up transistor as an electrical connection between the two, and thus, The elongated contact window only needs to be provided with a horizontal zero-thick metal connection to connect the elongated contact window with the gate line of the second pull-up transistor, without the lateral zero-thick metal connection and the longitudinal zero-thick layer The intersection or overlap of the metal wires (or pads), therefore, when the horizontal zero-thick metal wires and the longitudinal zero-thick metal wires (or pads) are individually subjected to a secondary lithography and etching process When the trenches required for fabrication are formed, the substrate does not have to be repeatedly etched, and severe pinning recesses can be avoided, so that leakage current can be avoided. Furthermore, since the density of the metal layer of the zeroth layer is lowered, the loading effect can also be reduced. Furthermore, the manufacturing condition of the zero-thick metal connection can be improved, and the formation of gaps or voids in the nailing area can be avoided, which can increase the reliability and increase the yield.

The above description is only a preferred embodiment of the present invention, and the patent application patent according to the present invention Equivalent changes and modifications made by the surrounding are intended to be within the scope of the present invention.

46‧‧‧Semiconductor substrate

47‧‧‧Isolation structure

50‧‧‧First long contact window

51‧‧‧First interlayer dielectric layer

52‧‧‧First active area

53‧‧‧Second interlayer dielectric layer

54‧‧‧Second active area

55‧‧‧First groove

56‧‧‧ Third active area

58, 58'‧‧‧ second gate line

59‧‧‧ trench

62, 62'‧‧‧Second long contact window

64‧‧‧First zero-layer metal connection

66‧‧‧Second zero-thick metal connection

72‧‧‧Word line connection pad

90, 92, 96, 96', 98‧‧ ‧ bungee

AA'‧‧‧ hatching

Claims (15)

A static random access memory cell layout structure includes: a semiconductor substrate including a first active region and a second active region parallel to the first active region; a first gate line, the first Passing through the active area and the second active area; a first elongated contact window spanning the first active area and the second active area on a side of the first gate line; parallel to the first a third active area and a fourth active area of the second active area, the second active area is located between the first active area and the third active area, and the third active area is located in the second active area and the first active area Between the four active regions; a second gate line passing over the third active region and the fourth active region; and a second elongated contact window spanning on a side of the second gate line The third active area and the fourth active area. The static random access memory cell layout structure of claim 1, further comprising: a first zero-thick metal connection, spanning the first elongated contact window and the second gate line; A second zero-thick metal connection is placed across the second elongated contact window and the first gate line. The static random access memory cell layout structure of claim 2, wherein the first elongated contact window and the second elongated contact window are disposed substantially in a line. The static random access memory cell layout structure of claim 2, further comprising: a third gate line passing over the first active area on the side of the first gate line, the first length a contact window is located between the first gate line and the third gate line; and a fourth gate line passes through the fourth active area on the side of the second gate line, the second An elongated contact window is located between the second gate line and the fourth gate line. The static random access memory cell layout structure of claim 4, further comprising: a word line connection pad connected to the fourth gate line; a bit line contact window, and the fourth gate The fourth active area connection on the other side of the line; and a bit line connection pad located on the bit line contact window. The static random access memory cell layout structure of claim 4, further comprising: an elongated ground electrode contact window on the first active region on the other side of the first gate line and extending to the first An active region of the adjacent static random access memory cell layout structure; and a ground electrode connection pad on the elongated ground electrode contact window. The static random access memory cell layout structure of claim 4, further comprising: a pair of separate ground electrode contact windows respectively located on the first active area on the other side of the first gate line and An active area of the adjacent SRAM cell layout structure; and a ground electrode connection pad straddle the pair of separate ground electrode contact windows. The static random access memory cell layout structure of claim 6 or 7, further comprising: a dielectric hole on the ground electrode connection pad; and a first layer metal interconnection on the dielectric hole. A static random access memory cell structure includes: a first inverter comprising a first pull-down transistor and a first pull-up transistor; and a second inverter comprising a second pull-down transistor And a second pull-up transistor; a first elongated contact window spanning the drain of the first pull-down transistor and the drain of the first pull-up transistor; a first zero-thick metal connection a line spanning the first elongated contact window and the gate line of the second pull-up transistor; a second elongated contact window is disposed across the drain of the second pull-down transistor and the drain of the second pull-up transistor; and a second zero-thick metal connection is placed across the second length a contact line on the gate line of the first pull-up transistor, wherein an upper surface of the first elongated contact window is substantially the same height as an upper surface of the gate line of the second pull-up transistor, The upper surface of the second elongated contact window is substantially the same height as the upper surface of the gate line of the first pull-up transistor, and the first zero-thick metal line directly contacts the first elongated contact window The gate line of the second pull-up transistor, and the second zero-thick metal line directly contacts the second elongated contact window and the gate line of the first pull-up transistor. The static random access memory cell structure of claim 9, wherein the gate line of the first pull-down transistor and the gate line of the first pull-up transistor are the same gate line . The static random access memory cell structure of claim 9, wherein the gate line of the second pull-down transistor and the gate line of the second pull-up transistor are formed by the same gate line . The static random access memory cell structure of claim 9, further comprising: a pair of separate ground electrode contact windows respectively located on the source of the first pull-down transistor and adjacent another static random access a source of the first pull-down transistor on the memory cell structure; and a ground electrode connection pad straddle the pair of separate ground electrode contact windows. The static random access memory cell structure of claim 9, further comprising: an elongated ground electrode contact window spanning the source of the first pull-down transistor and another static random access adjacent thereto a source of the first pull-down transistor on the memory cell structure; and a ground electrode connection pad on the elongated ground electrode contact window. A static random access memory cell structure according to claim 12 or 13, wherein a medium The hole is located on the ground electrode connection pad. The static random access memory cell structure of claim 14, wherein a first layer of metal interconnect is located on the dielectric hole.