TWI569149B - Apparatus and method for compensating a misalignment on a synchronous data bus - Google Patents

Description

Apparatus and method for compensating for errors in synchronous data bus

The present invention relates to the field of microelectronics, and more particularly to an apparatus and method for synchronizing data and timing of transmission and reception source synchronous signals.

Today's computer systems use a source synchronous system bus to provide data exchange between bus agents, such as between a microprocessor and a memory hub. The Source Synchronization bus protocol enables data to be transmitted at very high convergent speeds. The operation principle of the source synchronization protocol is that the transmission bus agent places the data on the bus outside the transmission agent in a fixed time interval, and according to the setting of the data (assert) or switching a "flash control" ( The strobe) signal is used to notify the receiving bus agent that the data is valid. The data signal and its corresponding flash control signal are transmitted over the busbars along the equal transmission path (including the physical ground and the electromagnetic ground), thus enabling the receiver to determine fairly when the corresponding flash control signal is detected. The information on the signal is valid. For the purposes of the present invention, the bus agent may be any electronic component that transmits data to/from another bus agent on the source sync bus using the source sync signal. For example, the bus agent can be a central processing unit, a microprocessor, and a memory control The device, the memory hub, the chip set, and the drawing controller are not limited thereto. The source synchronization bus can also be a conventional system bus, a front-end bus, or a back-end bus. The bus agents can be separately packaged, arranged on the motherboard, and interconnected with the wires on the motherboard. In addition, a plurality of bus agents can be arranged in the same package on the motherboard, wherein the plurality of bus agents can be individual die in the package or integrated into the same integrated circuit crystal The particles are connected to each other through wires on the die.

However, source sync data flash control signals and data signals are subject to errors for a variety of different reasons. These errors can come from uncontrollable design safety factors, process tolerance ranges, or environmental factors such as voltage or temperature. In most cases, the best case is that the radially distributed flash control signal is correctly switched over half of the data valid period so that the data seen by the receiver has equal set and hold times. However, errors caused by the above reasons may cause the data signal and/or its flash control signal to shift, so that the reception conditions are not optimized. As a result, the operating frequency of the associated components is limited.

Another source of error may be caused by the path distribution of the radially distributed flash control signals within the receiving element. When the system designer uses a large length to ensure that the flash control signal and its associated data signal are sent along the same transmission path on the system board (or the motherboard), the prior art knows that once the flash control signal Entering the receiving component must be assigned to all internal sync receptors associated with the flash signal. Some techniques for distributing the radially distributed flash control signal to the internal receiver only increase the transmission length required for the flash control signal to the transmit path of the internal receiver, but this transmission length increases the delay in the transmission of the data signal, thus causing synchronous transmission. Phase offset. Updating the flash control signal distribution method will also result in the allocation The radial distribution of the flash control signal buffering, thus further causing the phase shift of the synchronous transmission.

Accordingly, there is a need for an apparatus and method for compensating for misalignment errors in signals and flash control signals on a source synchronous data bus, thereby allowing optimization of the operating frequency of the components.

In addition, a technique is needed to adjust the phase adjustment of the data flash control signal and the corresponding data signal to allow for optimization of the signals on the synchronous bus.

What is more needed is an automatic operation mechanism to allow phase adjustment of the data flash control signal and corresponding data signals in the receiving component to be automatically optimized.

What is more needed is a programmable device at the motherboard level to compensate for process and design errors, voltage variations, and temperature variations in the automatic signal tuning mechanism.

In addition, what is needed is a synchronous receiver to automatically compensate for signal errors on the source sync data bus.

The present invention is to address the above problems and to overcome other problems, disadvantages and limitations of the prior art. In addition, the present invention provides a preferred technique for automatically and dynamically optimizing phase adjustment of data signals received by a source-synchronous bus and associated flash control signals. The invention provides a device for compensating for errors in a synchronous data bus, comprising a one-bit delay controller and a synchronous delay receiver; the bit delay controller measures a transmission time, wherein the transmission time starts from a data flash control signal Setting and terminating the first radial distributed flash control signal among the plurality of radially distributed flash control signals corresponding to the data flash control signal The bit delay controller also generates a value indicating a transmission time on a delay bus; the synchronous delay receiver is coupled to the bit delay controller for receiving the first of the radial distributed flash signals A radially distributed flash control signal and a data bit signal are received, and the registration of the data bit signal is delayed by a delay time.

The present invention provides an apparatus for compensating for errors in a synchronous data bus, comprising a microprocessor, wherein the microprocessor includes a one-bit delay controller and a synchronous delay receiver; and the bit delay controller measures a transmission time in which the transmission The time starts at a setting of a data flash control signal and terminates at a setting of a first radial distributed flash control signal among a plurality of radial distributed flash control signals corresponding to the data flash control signal, the bit delay controller A value indicating a transmission time is also generated on a delay bus; the synchronous delay receiver is coupled to the bit delay controller for receiving the first radial distributed flash control of the radial distributed flash signals And receiving a data bit signal and delaying the registration of the data bit signal by a delay time.

The present invention provides a method of compensating for errors in a synchronous data bus, comprising replicating transmission characteristics of a radial distribution component for a data flash control signal, receiving a first signal, and generating a second signal by replicating transmission characteristics Measuring a transmission time, wherein the transmission time starts from a setting of the first signal and ends at a setting of the second signal; generates a delayed bus line signal to indicate a transmission time; and receives a plurality of radial distributed flash control signals A radially distributed flash control signal and a data bit signal, and a registration of the data bit signal delayed by the transmission time.

The invention provides an apparatus for compensating for errors in a synchronous data bus a replica distribution network, a one-bit delay controller, and a synchronous delay receiver; the replication distribution network receives a first signal and generates a second signal, wherein the replication distribution network includes a data flash control The replication transmission characteristic of the signal replication distribution network; the bit delay controller measures a transmission time, wherein the transmission time starts from the setting of the first signal and ends at the setting of the second signal, and the bit delay controller also has a delay A value indicating a transmission time is generated on the bus bar; the synchronous delay receiver is coupled to the bit delay controller for receiving the first radial distributed flash control signal among the plurality of radially distributed flash control signals and receiving one The data bit signal and a data bit signal are delayed, and the registration of the data bit signal is delayed by a delay time.

The present invention provides an apparatus for compensating for errors in a synchronous data bus, including a microprocessor, wherein the microprocessor includes a replica distribution network, a one-bit delay controller, and a synchronous delay receiver; a first signal and a second signal, wherein the replication distribution network includes a replication transmission characteristic for a replication distribution network of a data flash control signal; the bit delay controller measures a transmission time, wherein the transmission time begins at A signal is asserted and terminated at the second signal setting, the bit delay controller also generates a value indicative of the transmission time on a delay bus; the synchronous delay receiver is coupled to the bit delay controller for receiving the complex number The first one of the radially distributed flash control signals is a radially distributed flash control signal and receives a data bit signal and a data bit signal, and delays registration of the data bit signal by a delay time.

The present invention provides a method for compensating for errors in a synchronous data bus, comprising measuring a transmission time, wherein the transmission time starts from a setting of a data flash control signal and terminates in a plurality of radial distributions of the corresponding data flash control signal. Setting a first radially distributed flash control signal of the control signal; generating a delayed bus line signal for indicating a transmission time; and receiving a first radial distributed flash control signal of the radially distributed flash control signal and a data bit The meta-signal, and the registration of the data bit signal is delayed by the transmission time.

The present invention provides an apparatus for compensating for errors in a synchronous data bus, comprising a one-bit delay controller for measuring a transmission time, wherein the transmission time starts from a setting of a first signal and ends at a setting of a second signal. And generating a first value indicating a tuning transmission time on the delay bus, wherein the bit delay controller includes a delay lock controller, an adjustment logic, and a Gray encoder; the delay lock controller selects the And one of a plurality of consecutive delayed versions of the first signal, and generating a delay selection signal on the delay selection bus to indicate a transmission time, wherein the selected delayed version is consistent with the setting of the second signal, and a second value indicating a transmission time is generated on the delay selection bus; the adjustment logic is coupled to a circuit and the delay selection bus to adjust the second value according to a value specified by the circuit, and generate a a third signal, wherein the third signal is output to an adjustment delay bus; and the Gray encoder performs a lattice on the third signal Encoding a first signal to generate the delay on the bus.

The present invention provides an apparatus for compensating for errors in a synchronous data bus, comprising a microprocessor, wherein the microprocessor includes a one-bit delay controller for measuring a transmission time, wherein the transmission time starts at a first Setting a signal and terminating at a second signal setting, and generating a first value indicating a adjusted transmission time on a delay bus, wherein the bit delay controller includes a delay lock controller, an adjustment logic, and a Gray encoder; delay phase lock The controller selects one of a plurality of consecutive delayed versions of the first signal, wherein the selected delayed version coincides with the setting of the second signal, and generates a second indicative transmission time on a delay selection bus The adjustment logic is coupled to a circuit and the delay selection bus, for adjusting the second value according to the value specified by the circuit, and generating a third signal, wherein the third signal is output to an adjustment delay bus; And, the Gray encoder gray-codes the third signal to generate the first signal on the delayed bus.

The present invention provides a method for compensating for errors in a sync data bus, comprising measuring a transmission time, wherein the transmission time starts at a setting of a first signal and ends at a setting of a second signal, wherein the step of measuring the transmission time comprises Selecting one of a plurality of consecutive delayed versions of the first signal, wherein the selected delayed version is consistent with the setting of the second signal; adjusting the delay time according to a value specified by the circuit to generate an adjusted delay time; and, The delay time is adjusted to Gray code to produce a value on the delayed bus.

100‧‧‧ computer system

101‧‧‧ bus bar agent

102‧‧‧Source Synchronous Bus

200‧‧‧ clock map

201‧‧‧First Situation

202‧‧‧Second situation

300, 400‧‧‧Devices for compensating for errors in synchronous data busbars

301, 311, 411~3N1‧‧‧ nodes

302, 402‧‧‧ Internal Radial Distribution Flash Control Signal

303.1~303.N, 403.1~403.N, 406.1~406.N, 501, 601, 701, 801‧‧‧ delay elements

305, 405‧‧ ‧ bit delay controller

313, 413‧‧‧flash control receiver

303, 403‧‧‧ radial distribution components

304, 404‧‧‧ Synchronous Delay Receiver

312~3N2, 412~4N2, SUB[1:0], SLAG‧‧‧ signals

406‧‧‧Copy radial distribution elements

415‧‧‧Copy flash control receiver

500‧‧‧ bit delay controller

502, 602, 702, 802‧‧‧ multiplexers

503, 603, 703‧‧‧ Delayed Phase Lock Controller

504, 604, 704‧‧ ‧ Gray encoder

600‧‧‧Fuse adjustment bit delay controller

605‧‧‧Value adjuster

606, 706‧‧‧ adjustment logic

700‧‧‧JTAG adjustment bit delay controller

705‧‧‧JTAG interface

800‧‧‧Synchronous delay receiver

803‧‧‧Synchronous Bit Receiver

900‧‧‧Precision delay components

901‧‧‧First multiplexer

902‧‧‧Second multiplexer

ALAG[3:0]‧‧‧ vector signal

BLCK1, BLCK0, BCLK#, BCLK[1:0]‧‧‧ bus time clock

D[15:0]‧‧‧ data bus signal

DATA1~DATAN‧‧‧ data bit signal

DATAX‧‧‧ data bit

DDATAX[15:0]‧‧‧delay bit signal

DSTBPB0, DSTBNB0, DSTROBE1~DSTROBEN, DSTROBEX‧‧‧ radial distribution flash control signals

DSTROBE‧‧‧ data flashing signal

JTAG[N:0]‧‧‧ control signal

K1~K15‧‧‧All opposite

LAG[3:0]‧‧‧delay bus signal

LAGCLK‧‧‧ Delay Time Pulse

LAGPLS‧‧‧Delayed pulse signal

LAGSELECT[3:0]‧‧‧Delay selection signal

LC0~LC31‧‧‧ points

OUT1~OUTN‧‧‧ output signal

RDATAX‧‧‧ Receive Bit Signal

REPS1‧‧‧radially distributed pulse signal

SDATAX‧‧‧Select delay signal

U1A/B~U15A/B‧‧‧Anti-relative

UPDATE‧‧‧ update signal

The following description will be helpful in understanding the advantages, features, and improvements of the present invention. The drawings include: Figure 1 is a block diagram illustrating the synchronization of transmission and reception sources in a current system; Figure 2 is a description of the first Figure 2 shows the clock map of the synchronization signal situation in two systems in the current system. The first scenario is that the data flash control in the receiving component is synchronized with its corresponding data, and the second scenario is that the data flash control and its corresponding data are not synchronized. Figure 3 is a diagram of the local automatic synchronization signal adjustment provided by the present invention. Figure 4 is a block diagram of an apparatus for dynamic automatic synchronization signal adjustment provided by the present invention; and Figure 5 is a block diagram of an embodiment of a bit delay control element provided by the present invention; 6 is a block diagram showing the fuse adjustment bit delay control element provided by the present invention; FIG. 7 is a block diagram showing the JTAG adjustment bit delay control element provided by the present invention; FIG. 8 is provided by the present invention. A block diagram of a synchronous delay receiver is illustrated; FIG. 9 is a block diagram showing the precise delay elements provided by the present invention.

The details of the manner of making and using the embodiments of the present specification are as follows. It is to be particularly noted, however, that the present specification provides many applicable inventive concepts and can be widely implemented in specific content. The specific embodiments discussed are merely illustrative of specific fabrications and implementations of the embodiments of the present invention and are not intended to limit the scope of the invention.

The detailed embodiments are described below in conjunction with the drawings. Wherever possible, the same reference numerals are used in the drawings In the drawings, the shape and thickness are enlarged for clarity and convenience. The following description will specifically address the device of the embodiment of the invention or the forming portion of the component therein. It will be understood that elements not specifically shown or described may be of various different types. Reference throughout the specification to the embodiments means that the specific features, structures, or characteristics mentioned in the present embodiments are included in at least one embodiment of the present invention. Therefore, in an embodiment, throughout the specification, The terminology is not necessarily to be taken as the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined with one or more embodiments in any suitable manner. It is to be understood that the following drawings are not to scale and are merely illustrative.

To illustrate the background in which today's devices use source synchronization signals and related techniques to transmit and receive data, Figures 1 through 2 are used to discuss the shortcomings and limitations of the current technology. Thereafter, Figures 3 through 9 are for discussing the present invention. The present invention provides an operational mechanism capable of overcoming these limitations and disadvantages, the operational mechanism detecting the precise delay of the data flash control signal and its associated data group bits in the receiving component, and providing delay related data group bits in the relevant receiver The technology of the element thus provides correction of the flash control signal and data error caused by various reasons, thereby enabling the throughput between the transmission element and the receiving element to be optimized.

FIG. 1 illustrates a block diagram of two or more bus distributors 101 exchanging data on the source sync bus 102 in today's computer system 100. As described above, the bus agent 101 can be any component (group) in the computer system 100 for transmitting or receiving data through the source sync bus 102. The source synchronization bus 102 can be other known names, such as, but not limited to, a system bus, a front-end bus, and a back-end bus.

For those skilled in the art, the typical bus bar agent 101 can be, for example, a microprocessor or a central processing unit (CPU), a memory hub or a memory controller, a chipset, and a master. Or subordinate peripheral components, direct memory access units, graphics controllers, or other types of bus interface units, but are not limited thereto. Broadly speaking, in order to transmit data, one of the bus schedulers 101 drives a letter on the source sync bus 102. The subset of numbers, while the other bus agent 101 detects and receives the driven signal, thereby obtaining data representative of the state of one or more subsets of signals on the source sync bus 102. One or more bus distributors 101 may be components individually arranged in a separate integrated circuit die and packaged in an element package, wherein the component package is placed on a motherboard (or a system board) in a conventional manner And the source synchronous busbar 102 is placed on the motherboard with metal wiring (or pads). Alternatively, two or more bus bar agents 101 may be individually arranged in separate integrated circuit dies, and the two or more integrated circuit dies are placed on the substrate and packaged in a single package. In the component package, the source synchronous busbar 102 is disposed on the substrate in a metal wiring manner, and the single component package is arranged on the motherboard and coupled to other motherboards through the metal wires of the interactive connection on the motherboard The upper component package, wherein the interconnected metal wiring comprises a source synchronous busbar 102. Further, two or more bus bar agents 101 may be arranged on a single integrated circuit die, wherein the integrated circuit die is packaged in a component package on the motherboard, and the source is synchronized. The row 102 includes metal wiring on a single integrated circuit die to interconnect two or more bus bar agents 101, and the metal wiring on the motherboard is interconnected to the component package or will cover a single integrated circuit die The component package is connected to the component package on the other motherboard.

There are many different bus bar protocols for data transfer between two bus bar agents 101 in the art today, and detailed descriptions of these different techniques are beyond the scope of the present invention. In the present invention, the "data" transmitted between the two or more bus distributors 101 of the busbar interactive transmission includes address information, information about one or more addresses, control information, or status information, but Unlimited It is here. Regardless of the type of data transmitted on the source sync bus 102, the present invention emphasizes that more and more computer systems 100 today use a particular type of bus protocol, commonly referred to as a "source synchronization" protocol, at very high speeds. The bus speed is used for data transmission. Compared with the sample data bus protocol of the previous case, the principle of the source synchronization protocol is that the transmitted bus agent 101 places the data in the convergence time in a fixed time interval (ie, "setup time"). The source outside the agent 101 synchronizes the bus 102 and sets a "flash" signal corresponding to the data to inform the receiving bus agent 101 that the data is valid. The transmission bus agent 101 holds the data on the synchronization bus 102 for a period of time (ie, "hold time"), which is approximately equal to the setup time, so that the receiving bus agent 101 can detect the setting. The time state before the radial distribution of the flash control signal, and the data after the radial distribution of the flash control signal is obtained. Those skilled in the art will appreciate that at very high speeds, the physical and electromagnetic parameters of a set of data and their corresponding radial distributed flash control signals are quite different from the other set of signals on the bus. Transmission path, whether the transmission path is from the transmission element to another receiving element, or the transmission path is from the transmission bus distributor 101 to the same receiving bus agent 101, but to another data group and the group The associated radial distribution flash control signals are consistent. In particular, the transmission path, the bus bar impedance, and the electromagnetic characteristics of the transmission path affect the time during which the data signal is stable (eg, set and hold time), where stable means that the reception is valid for the receiving bus bar agent 101. . For this reason, the source synchronous bus protocol is now the mainstream in this field. In the traditional architecture, the data flashing signal related to the corresponding group (or "group") of the data signal deliberately makes the circuit layout along the same path of the data signal group, thus flashing The control signal will see the same path characteristics as the data signal. If the flash control signal is set during the period when the data is valid (preferably set to be about the same as the holding time), when the receiving bus bar agent 101 detects the effective switching of the flashing signal, the data signal can be fairly determined. It is vaild.

Figure 2 is a transmission process for further describing the signals of the source synchronous bus. The clock diagram 200 depicts the situation in which the two sources synchronize signals in the present system of Figure 1: the first scenario is that the data flash control signal in the receiving component is synchronized with its corresponding data, and the second scenario is data flashing. The signal and its corresponding data are not synchronized. The clock map 200 shows the interaction of the signals in the sample data signal group, wherein the interaction process is used to perform the data phase of the 8-bit burst bus transmission. For clarity of illustration, the signal in clock map 200 is set to a logic low level, although those skilled in the art will appreciate that the setting can also be a logic high level, or a high level and a low level. Switch between. The cycle of the differential bus bar clock BLCK[1:0] is shown at the top of the clock map 200. For x86-compatible microprocessors, bus clocks BLCK[1:0] are routed to all bus agents to facilitate synchronization of the interactions between the bus agents.

The source synchronization protocol provides a 16-bit data bus signal D[15:0] that is supported between the data phases of the 8-bit cache line of the two clock cycles of the bus clock BLCK[1:0]. The transmission is achieved by the use of the radial distribution flash control signals DSTBPB0 and DSTBNB0 of the source synchronization data. The transmission of one byte of the 16-bit data bus signal D[15:0] is a conventional beating, and four heartbeats 1-4, 5-8 are transmitted to the bus clock BCLK[1] :0] every cycle. The routing path of the data bus signal D[15:0] and its corresponding radial distribution flash control signals DSTBPB0 and DSTBNB0, phase Same as the transmission path of each individual bit receiver of the data bus signal D[15:0]. The falling edge of the radial distribution flash control signal DSTBPB0 is used to indicate the validity of the characters 1, 3, 5, 7 on the data bus signal D[15:0]. The falling edge of the radially distributed flash control signal DSTBNB0 is used to indicate the validity of the characters 2, 4, 6, 8 on the data bus signal D[15:0]. It should be noted that the frequency of the radial distribution flash control signals DSTBPB0 and DSTBNB0 is twice the frequency of the bus bar clocks BLCK[1:0], and the two radial distributed flash control signals DSTBPB0 and DSTBNB0 have opposite two-points. A clock cycle phase delay. Thus, the illustrated bus bar protocol supports data transfer for four groups (ie, heartbeats) in a single bus clock cycle. The above signals are used to illustrate the present invention and simplify the interactive transmission of the busbars for clarity of illustration. However, those skilled in the art will understand how to expand the bus to support various numbers of bits.

Those skilled in the art will appreciate that a transport bus agent (such as a microprocessor, chipset, or other bus agent) arranges its data bus signal D[15:0] on the bus and then sets The corresponding flash control signals DSTBPB0 and DSTBNB0 are used to indicate the validity of the data. It is better to pass the half of the data validity period so that the establishment and holding time are approximately equal. Therefore, compared to the older sample data/address bus, the data is arranged on the bus and held for a sampling time, but the current synchronous bus operation mechanism places the data flash control signal in multiple The state of the convergence of the bursts of the flash signal DSTBPB0, DSTBNB0 is used to indicate the validity of each burst. Since the corresponding radial distribution flash control signals DSTBPB0, DSTBNB0 are routed along the same transmission path of the data bus signal D[15:0] associated with them, it is almost certain that the receiver detects the path. When the settings of the distributed flash control signals DSTBPB0, DSTBNB0 are made, the associated data bus signal D[15:0] will be valid.

From the point of view of receiving the bus distributor, the setting of the data/address of the radial distributed flash control signals DSTBPB0, DSTBNB0 seems to be difficult to determine for the setting of the bus clock BCLK#, however, as described above, The period of each of the radially distributed flash control signals DSTBPB0, DSTBNB0 is approximately equal to half of the period of the bus clock BCLK#. As mentioned earlier, the transmission clock of the data and the flash control signal is indeed a function of the bus clock frequency, but in the receiving bus agent, for any intent and purpose, the switching of any given data flash signal is The bus clock BLCK[1:0] is not synchronized. This is because when the bus clock BLCK[1:0] passes through different transmission paths between the clock generator and the receiving bus distributor, the bus clock BLCK[1:0] and the corresponding data flash control will be performed. There is a fixed and unknown phase difference between the transmission of the signal subgroup signals.

It should be noted that in the first scenario, the data bus signal D[15:0] and its associated radial distribution flash control signals DSTBPB0, DSTBNB0 change with the phase of the bus clock BCLK[1:0]. Transition, and in the second scenario, the transition of the data bus signal D[15:0] and its associated radial distributed flash control signals DSTBPB0, DSTBNB0 is independent of the phase transition of the bus clock BCLK[1:0]. These differences may be the way the transport bus agent transmits data on the bus, or the different transmission path lengths from the data bus signal D[15:0] relative to the bus clock BCLK[1:0], Or both from the transmitter characteristics and the length of the transmission path.

As long as the data signal in the data bus signal D[15:0] is correspondingly related to the radial distribution flash control signals DSTBPB0, DSTBNB0 is approximately appropriate The phase is received, and since the setup and holding times are approximately equal, efficient data transmission at a high bus speed can be achieved. This is an embodiment described by the first scenario 201. It should be noted that, at time T1, from the viewpoint of receiving the bus bar agent, when the cluster 1 on the bus bar is active, the radial distributed flash control signal DSTBPB0 is set at half of this period, thus forming a reception. The best conditions for Congxun 1. Similarly, at time T2, from the viewpoint of receiving the bus bar agent, when the cluster 4 on the bus bar is active, the radial distributed flash control signal DSTBNB0 is set at half of this period, thus shaping the receiving burst 4 best conditions.

The conditions of the first situation 201 are ideal but not true. This is because in the high speed corresponding to the current synchronous data bus, even the transmission path and its corresponding load in the receiving component affect each data bus signal D[15:0] and its corresponding radial distribution flash control. The relative offset of signal DSTBPB0 to DSTBNB0. In conventional designs, the data bit signal and the radial distribution flash control signal are routed using brute force techniques such that the data bit signal and the flash control signal cause a minimum delay and load on the transmission path. It may still occur on the die. Since each bit is individually routed to its receiver, the phase difference between the data bit signal and the radially distributed flash control signal will vary with different receivers.

Since these individual transmission paths have internal differences from the receiving elements, the designer typically uses a radial distribution architecture on the radially distributed flash control signal, where an equal transmission path is used for each of the radially distributed flash control signals distributed ( Includes load and buffer). As a result, as seen by the bit receiver, the phase delay between each data bit in the subgroup and its individually distributed radial distribution flash control signals is approximately equal. Therefore, the radial distribution architecture introduces phase delay into the The distributed radial distribution flash control signal causes each receiver within the data group to see the same amount of delay on the individual flash control signals relative to their corresponding data bit signals. From a designer's point of view, the radial distribution architecture is very useful because each data bit in the group can see the same amount of phase delay for its corresponding flash control signal. However, the inventors have found that the radial distribution can limit the operating frequency of the device due to the delay being introduced into the flash control signal, that is, the settling time will be much longer than the holding time, thus limiting the overall operating frequency.

The second scenario 202 describes the case where the data bus signal D[15:0] operates at an extreme such that its associated data bit receiver is inoperable. That is, since the radial distribution flash control signals DSTBPB0 and DSTBNB0 are distributed within the receiving bus distributor according to the radial distribution architecture, the data bit receiver is used for the data bus signal D[15:0], The amount of delay introduced into the distributed flash control signal causes the distributed flash control signal to be set when the data bus signal D[15:0] is no valid. Carefully speaking, this is not a pleasure. For example, at time T3, the radial distributed flash control signal DSTBPB0 is set when the burst 5 on the bus is inactive from the point of view of the bit receiver, thus eliminating any chance of receiving the burst 5. It should also be noted that at time T4, the radial distribution is set by the flash control signal DSTBNB0 when the burst 8 on the busbar is deactivated, thus eliminating any chance of receiving the burst 8.

As described above, in order to compensate for the error of the data bit signal and its corresponding data flash control signal, various techniques in this field use the phase delay of the data bit in the subgroup or the acceleration of the radial distribution of the data. The signal (when the radial distribution of the flash control signal occurs) is optimally tuned. However, all of these mechanisms require experimentation, testing, connecting circuits to the outside of the component, and/or including Steps to program components on the motherboard system. The inventor noticed that when the phase difference mainly comes from the radial distribution of the data radial distribution of the flash signal in the given receiving component, each design must be individually structured to compensate the data radial distribution of the phase of the flash control signal and its associated data bits. The differences in the elements make these experiments, tests, circuits, and/or stylization limited.

Furthermore, the inventors have noted that although the length of any particular transmission path for radially distributing the flash control signal is known, in the radial distribution configuration, the clock of the path (and the resulting phase delay) will be due to voltage, The temperature, as well as the process conditions, change dynamically. Therefore, as described in the prior art, the introduction of a specific phase delay amount to the data bits in the subgroup is currently the best secondary compensation technique.

The present invention overcomes the above limitations and disadvantages and provides a mechanism for automatically and dynamically adjusting the phase of the data flash control signal and the associated data bit signals in its receiving elements. The present invention dynamically adjusts the correction of these signals as environmental factors (e.g., voltage, temperature, and process) in the host device change. Figures 3 through 10 will be used to discuss the present invention.

The block diagram shown in FIG. 3 is used to illustrate the apparatus 300 for compensating for errors in the synchronization data bus for automatic local sync signal tuning as provided by the present invention. Preferably, the means 300 for compensating for errors in the sync data bus is disposed in a receiving component (e.g., a bus bar agent) that is coupled to the source sync bus as described above. In one embodiment, the receiving component includes an x86 compatible microprocessor disposed in a die in the integrated circuit package, wherein the integrated circuit package body is physically coupled to the motherboard or system board. In another embodiment, the receiving component comprises an x86 compatible microprocessor, wherein the x86 compatible microprocessor is configured One or a plurality of x86 compatible microprocessors on a single die in an integrated circuit package. The receiving component may include one or more means 300 for compensating for errors in the synchronization data bus to synchronize with one or more data groups and their corresponding radially distributed flash control signals, regardless of the type of data used (eg data, address or control). The means 300 for compensating for errors in the sync data bus includes a radial distribution element 303 for the data flash signal DSTROBE, which will be discussed in further detail later. The radial distribution component 303 will equalize all transmission paths (including load and buffer) when the data flash signal DSTROBE is distributed. As noted above, the data flash signal DSTROBE is received from a transmission component (e.g., a bus distributor) (not shown).

The apparatus 300 for compensating for errors in the synchronization data bus may have a plurality of synchronous delay receivers 304 to receive the radial distributed flash control signals DSRTOBE1 to DSTROBEN with phase alignment and load matching and one or more data bit signals DATA1 to DATAN, in which the radial distribution flash control signals DSRTOBE1 to DSTROBEN are derived from the data flash control signal DSTROBE. The first data bit signal DATA1 of the plurality of data bit signals enters the receiving element at the first node 311, and the first signal 312 is routed to the first synchronous delay receiver 304. The last data bit signal DATAN of the plurality of data bit signals enters the receiving element at the last node 3N1, and the last signal 3N2 is routed to the corresponding synchronous delay receiver 304. The synchronous delay receiver 304 outputs the received output signals OUT1 to OUTN, respectively.

The data flash control signal DSTROBE enters the component at node 301 where there is an internal radial distribution flash control signal 302 routed to the flash control receiver 313 and the flash control receiver 313 receives the internal radial distribution flash control signal 302. Flash control receiver The output of 313 is coupled to the radial distribution element 303. The radial distribution component 303 includes a plurality of delay elements 303.1 through 303. N, wherein each delay element is associated with a corresponding one of the plurality of synchronous delay receivers 304. Each of the plurality of delay elements 303.1 through 303.N introduces a portion of the radial transmission path to the data flash signal DSTROBE as the data flash signal DSTROBE is routed from the radial distribution element 303 to the corresponding synchronous delay receiver 304. The transmission path. In an embodiment, the radial transmission path may include a path that is the worst embodiment for load, path length, and buffering, wherein the path is related to a plurality of distributed radial distribution flash control signals DSRTOBE1 to DSTROBEN. one. A portion of the radial transmission path corresponding to the synchronous delay receiver 304 introduces an additional transmission path, load and buffer associated with the corresponding radial distributed flash control signals DSRTOBE1 to DSTROBEN, the load and the buffer, such that the corresponding radial distribution The cumulative length, load and buffer of the flash control signals DSRTOBE1 to DSTROBEN are equal to the radial transmission path described above. Therefore, in terms of the synchronous delay receiver 304, the corresponding radial distributed flash control signals DSRTOBE1 to DSTROBEN delay their corresponding signals 312 to 3N2 by a phase amount, wherein the delayed phase quantities are the same as the predetermined data subgroup. The amount of phase seen by all other sync delay receivers 304 in the group.

The means 300 for compensating for errors in the synchronization data bus also includes a bit delay controller 305 for receiving one of the internal radial distributed flash control signal 302, the update signal UPDATE, and the plurality of radially distributed flash control signals DSTROBEN. In one embodiment, the bit delay controller 305 generates a 4-bit delayed bus signal LAG[3:0] to indicate that the assigned radial distribution flash control signals DSRTOBE1 to DSTROBEN are compared to the received data flash signal DSTROBE. The amount of phase delay. The delayed bus signal LAG[3:0] is routed to each of the sync delay receivers 304 in the data subgroup.

In terms of operation, when the update signal UPDSTE is set, the bit delay controller 305 sets the setting of the data flash control signal DSTROBE and the setting of the radial distribution flash control signal DSTROBEN when the receiving component receives the data flash signal DSTROBE. The delay between the delays and the delay is indicated by the value of the delayed bus signal LAG[3:0]. The synchronous delay receiver 304 can log in the value of the delayed bus signal LAG[3:0] and introduce an equal amount of delay into its corresponding signal 312 to 3N2 when the data flash signal DSTROBE is set in the subsequent data clock cycle. . Therefore, the phase delay amount in the assigned radial distributed flash control signals DSRTOBE1 to DSTROBEN is updated in each data clock cycle, and this delay is implemented in the next data clock cycle, and each synchronous delay receiver 304 will introduce this same amount of delay into its corresponding signal 312 to 3N2 such that the assigned radial distributed flash control signals DSRTOBE1 through DSTROBEN are concentrated during the signal 312 to 3N2 active period. Accordingly, the present invention delays each of the signals 312 through 3N2 with a value indicated by the delayed bus signal LAG[3:0] to provide the same setup and hold time for each of the synchronous delay receivers 304, thereby enabling Provides higher frequency bus transmissions than is known.

A 4-bit delayed bus signal LAG[3:0] is used to provide an acceptable amount of resolution in the amount of delay. However, increasing or decreasing the complexity of the bit delay controller 305, the number of bits of the delayed bus signal LAG[3:0], and the complexity of the delay delay receiver 304 introducing the delay to achieve higher or lower Resolution.

Based on various known reasons including reset state, sleep state, The power update control, etc., the update signal UPDATE can be deasserted. In an embodiment, when the update signal UPDATE is not set, the bit delay controller 305 may not update the value of the delayed bus signal LAG[3:0] and synchronize the delay receiver 304 at all subsequent information clocks. The previous value is used in the cycle until the update signal UPDATE is reset.

Those skilled in the art will appreciate that the worst case transmission path (and the resulting delay) will vary due to voltage, temperature, and process conditions (different between die and die, and point-to-point location on the die). Change) and change dynamically. This has the advantage that since the amount of delay measured by the bit delay controller 305 can be replicated by each of the synchronous delay receivers 304, the value indicated by the delayed bus signal LAG[3:0] will also be a function of the above variation. Dynamically adjusted.

The apparatus 300 for compensating for errors in the synchronization data bus is provided by the present invention for performing the functions and operations discussed above. It should be noted that the apparatus 300 for compensating for errors in the synchronization data bus includes logic, circuitry, or microcode, or a combination of the above logic, circuitry, or microcode, or can be used to execute the present. The equivalent of the functions and operations of the invention. The means for performing the functions and operations in the apparatus 300 for compensating for errors in the synchronization data bus can be shared with other circuits, microcode, etc. to perform other functions and/or operations in the receiving element.

The means 300 for compensating for errors in the sync data bus provides a mechanism for directly measuring the delay between the received data flash signal DSTROBE and its assigned radial distributed flash signal DSRTOBE1 to DSTROBEN, thus providing a simple technique Compensate for radial flicker delays in a specific data subgroup late. However, the inventors have noted that another embodiment of the present invention can perform a replica radial distribution mechanism when measuring delays offline to adjust the delay more instantaneously and dynamically. That is, in accordance with another embodiment, wherein when the sync bus is activated, the delay can be measured and distributed to the complex delay receiver in a manner that is not synchronized to the delay receivers. Accordingly, attention is now directed to FIG. 4, which is used to illustrate the apparatus 400 for compensating for errors in the synchronization data bus for automatic local sync signal tuning as provided by the present invention.

As described above, the means 400 for compensating for errors in the sync data bus is preferably disposed in the receiving component, wherein the receiving component is coupled to the source sync bus. In one embodiment, the receiving component includes an x86 compatible microprocessor as a die in the integrated circuit package, wherein the integrated circuit package system is physically coupled to the motherboard or system board. In another embodiment, the receiving component comprises an x86 compatible microprocessor, the x86 compatible microprocessor being one or a plurality of x86 compatible microarrays arranged on a single die in the integrated circuit package processor. The receiving component may include one or more means 400 for compensating for errors in the synchronization data bus for synchronizing one or more data groups and their corresponding radial distribution flash control signals, regardless of the data used What is the type (such as data, address or control). As shown in FIG. 3, the apparatus 300 for compensating for errors in the synchronization data bus, the apparatus 400 for compensating for errors in the synchronization data bus shown in FIG. 4 includes a radial distribution element 403 for the data flash signal DSTROBE. This will be discussed in further detail later. The radial distribution element 403 equalizes all transmission paths (including load and buffer) when the data flash signal DSTROBE is distributed. As mentioned above, the data flash signal DSTROBE is received from a transmission element (not shown).

The means 400 for compensating for errors on the synchronization data bus can have complex A plurality of synchronous delay receivers 404, along with phase-aligned and load-matched radial distributed flash control signals DSRTOBE1 through DSTROBEN to receive one or more data bit signals DATA1 through DATAN, wherein the radially distributed flash control signals DSRTOBE1 to DSTROBEN comes from the data flash signal DSTROBE. The first of the plurality of data bit signals DATA1 enters the receiving element at the first node 411, and the first signal 412 is routed to the first synchronous delay receiver 404. The last of the plurality of data bit signals DATA1 enters the receiving element at the last node 4N1, and the last signal 4N2 is routed to the corresponding synchronous delay receiver 404. The synchronous delay receiver 404 outputs the received output signals OUT1 to OUTN, respectively.

The data flash control signal DSTROBE enters the component at node 401 and routes the internally radially distributed flash control signal 402 to the flash control receiver 413, wherein the flash control receiver 413 receives the internal radial distributed flash control signal 402. The output of the stroboscopic receiver 413 is coupled to a radial distribution element 403. The radial distribution component 403 includes a plurality of delay elements 403.1 through 403.N, each of which is associated with a corresponding one of the plurality of synchronous delay receivers 404. Each of the plurality of delay elements 403.1 through 403.N introduces a portion of the radial transmission path to the data flash signal DSTROBE as the data flash signal DSTROBE is routed from the radial distribution element 403 to the corresponding synchronous delay receiver 404. The transmission path. In an embodiment, the radial transmission path may include a path of the worst-case embodiment in terms of load, path length, and buffering, wherein the radial path is related to a plurality of distributed radial distribution flash control signals DSRTOBE1 to DSTROBEN One of them. Part of the radial transmission path reference corresponding to the synchronous delay receiver 404 is related to the length, load and delay of the corresponding radial distribution flash control signals DSRTOBE1 to DSTROBEN Additional transmission paths, loads and buffers outside of the impulse are such that the cumulative length, load and buffer of the corresponding radial distributed flash control signals DSRTOBE1 to DSTROBEN are equal to the radial transmission paths described above. Thus, in terms of synchronous delay receiver 404, its corresponding radial distributed flash control signals DSRTOBE1 through DSTROBEN delay their corresponding signals 412 through 4N2, wherein the delayed phase quantities are the same as all other synchronizations in a given data subgroup. The amount of phase seen by the receiver 404 is delayed.

The means 400 for compensating for errors in the synchronization data bus also includes a replica strobe receiver element (PERPCVR) 415 for receiving the delayed pulse signal LAGPLS. In an embodiment, the delayed pulse signal LAGPLS may be an internal clock signal. The copy strobe receiving element 415 is a matching copy of the strobe receiver 413. The output of the replica flash control receiving component 415 is coupled to a replica radial distribution component 406, wherein the replica radial distribution component 406 is a replica of the radial distribution component 403, including matching circuit structure, transmission path length, load, and buffering. The replica radial distribution component 406 includes a plurality of delay elements 406.1 through 406.N, each of the replica delay elements 406.1 through 406. N being associated with one of the corresponding plurality of sync delay receivers 404. Each of the plurality of replica delay elements 406.1 through 406.N introduces a portion of the radial transmission path to the data flash control signal as the data flash signal DSTROBE is routed from the radial distribution component 403 to the corresponding synchronous delay receiver 404. DSTROBE transmission path. In an embodiment, the radial transmission path may include a path of the worst-case embodiment in terms of load, path length, and buffering, wherein the path is related to a plurality of distributed radial distribution flash control signals DSRTOBE1 to DSTROBEN One. In another embodiment, the copy radial distribution component 406 can include only one copy delay element 406.X to replicate the worst embodiment path. Copy radial distribution element 406 One of the radial distributed pulse signals REPS1 is coupled to the bit delay controller 405 to generate a delayed bus signal LAG[3:0] coupled to each of the synchronous delay receivers 404. The update signal UPDATE and the delayed pulse signal LAGPLS are also coupled to the bit delay controller 405. In one embodiment, the bit delay controller 405 generates a 4-bit delayed bus signal LAG[3:0] to indicate the amount of phase of the radially distributed pulse signal REPS1 behind the delayed pulse signal LAGPLS. Since the combination of the copy flash control receiving element 415 and the replica radial distribution element 406 completely replicates the transmission path displayed by the flash control receiver 413 and the radial distribution element 403, it should be noted that the delay bus signal LAG[3:0] The indicated phase delay amount represents the same phase delay that the flash control receiver 413 has with the radial distribution element 403, and thus is substantially identical to the distributed radial distribution flash control signal DSTROBE1 to DSTROBEN backward data flashing signal DSTROBE The amount of phase.

In terms of operation, when the update signal UPDSTE is set, the bit delay controller 405 measures the delay between the setting of the data flash signal DSTROBE and the setting of the radial distribution flash control signal DSTROBEN, and the delay is delayed by the bus signal LAG The value of [3:0] is indicated. In an embodiment, the delayed pulse signal LAGPLS is derived from a continuous signal of a core processor clock signal (not shown). In an embodiment, the update signal UPDATE is set with every 64 clock cycles of the core processor clock signal. Other embodiments for ensuring that the clock of the delayed bus signal LAG[3:0] can be updated in real time can also be considered when processing or power is not burdened on other components of the bus distributor. The synchronous delay receiver 404 can log in the value of the delayed bus signal LAG[3:0] and introduce an equal amount of delay into its corresponding signal 412 to 4N2 when the data flash signal DSTROBE is set in the subsequent data clock cycle. . Therefore, the distribution of the radial distribution flashes The amount of phase delay in the control signals DSRTOBE1 through DSTROBEN is updated in each data clock cycle, as replicated by the delayed pulse signal LAGPLS through the replica flash control receiving component 415 and the replica radial distribution component 406, and This delay is used for the next data clock cycle, and all data clock cycles will generate this delay until the next periodic update of the bus signal LAG[3:0] is delayed, with each synchronous delay receiver 404 This same amount of delay is introduced to its corresponding received signals 412 through 4N2 such that the assigned radial distributed flash control signals DSRTOBE1 through DSTROBEN are concentrated during the period in which signals 412 through 4N2 are active. Thus, the present invention delays each of the signals 412 through 4N2 by the amount indicated by the delayed bus signal LAG[3:0] to provide the same setup and hold time to each of the synchronous delay receivers 404, thereby providing a ratio The higher case bus transmission of the previous case.

Compared with the apparatus 300 for compensating for the error on the synchronous data bus of FIG. 3, the apparatus 400 for compensating for the error on the synchronous data bus of FIG. 4 does not rely on the setting of the data flash signal DSTROBE to measure and mark the radial direction. The distribution of the flash control signals DSRTOBE1 to DSTROBEN delays the amplitude of the data flash control signal DSTROBE.

A 4-bit delayed bus signal LAG[3:0] is used to provide an acceptable amount of resolution in the amount of delay, however, increasing or decreasing the complexity of the bit delay controller 405, delaying the bus signal LAG[3:0 A higher or lower resolution can be achieved with the number of bits on the top and the complexity of the synchronous delay receiver 404.

The update signal UPDATE can be unset based on various known reasons including reset status, sleep state, power control, and the like. When the update signal UPDATE is not set, the bit delay controller 405 may not update the delay sink. The value of the stream signal LAG[3:0] is streamed, and the sync delay receiver 404 uses the previous value in the subsequent data clock cycle.

The apparatus 400 for compensating for errors in the synchronization data bus is provided by the present invention for performing the functions and operations discussed above. It should be noted that the apparatus 400 for compensating for errors in the synchronization data bus includes logic, circuitry, or microcode, or a combination of the above logic, circuitry, or microcode, or can be used to perform the present invention. The equivalent of the function and operation. The means for performing these functions and operations among the means 400 for compensating for errors in the sync data bus can be shared with other circuits, microcode or the like for performing other functions and/or operations in the receiving element.

The block diagram shown in FIG. 5 is used to illustrate a detailed embodiment of the bit delay controller 500 provided by the present invention. The bit delay controller 500 can be implemented in the embodiments of FIGS. 3 and 4. The bit delay controller 500 includes a delay element 501 coupled to the multiplexer 502. The multiplexer 502 is coupled to the delay lockout controller 503 via the signal SLAG. The delay lockout controller 503 generates a 4-bit delay select signal LAGSELECT[3:0], wherein the delay select signal LAGSELECT[3:0] is coupled to the multiplexer 502 and the Gray encoder 504. The update signal UPDATE is coupled to the Gray encoder 504, wherein the Gray encoder 504 generates a Gray coded 4-bit delay bus signal LAG[3:0] for indicating matching to the matched inverter pair U1A/B. The number of U15A/B, where this amount causes the radial distributed pulse signal REPS1 to lag behind the delay amount of the delay time pulse LAGCLK.

The delay element 501 and the delay lock-in controller 503 receive the delay time pulse LAGCLK. The delay lockout controller 503 also receives the radially distributed pulse signal REPS1. In the embodiment of Figure 3, the data flash signal DSTROBE represents The delay time pulse LAGCLK, the radial distribution flash control signal DSTROBEN represents the radial distribution pulse signal REPS1. In the apparatus 400 for compensating for errors in the sync data bus on FIG. 4, the delayed pulse signal LAGPLS represents the delay time pulse LAGCLK, and the radial distributed pulse signal REPS1 is represented by the same name. Delay element 501 includes a plurality of inverse relatives U1A/B through U15A/B. The contact points LC0 to LC15 are coupled to each of the opposite sides U1A/B to U15A/B, and the contact points LC0 to LC15 are coupled to the multiplexer 502. In the embodiment of Figure 5, the 15 opposite U1A/B to U15A/B are matched inverses, that is, each of the opposite U1A/B to U15A/B inverters has 20 picoseconds. (picosecond) delay (that is, each anti-relative U1A/B to U15A/B has a delay of 40 picoseconds), which is acceptable for measuring the phase delay of a receiving element operating at a speed of approximately 500 MHz to 1.5 GHz. Accepted resolution. Other embodiments may consider using different numbers of inverse relative U1A/B to U15A/B based on appropriate applications. The anti-relative U1A/B to U15A/B having a delay of 40 picoseconds is commensurate with a receiving element fabricated in accordance with the 28 nm CMOS process and operating in the above frequency range. It should be noted that the architecture shown in FIG. 5 is used to reveal the present invention, and can be modified according to different processes and different operating frequencies to improve accuracy and resolution.

As described above, the Gray encoder 504 generates a Gray coded 4-bit delayed bus signal LAG[3:0] for indicating the phase delay of the radially distributed pulse signal REPS1 after the delay time pulse LAGCLK, which time It is the time required for the data flash signal provided by the present invention to be transmitted to the data bit receiver through the radial distribution network.

In terms of operation, as described above, the update signal UPDATE will enable or disable the operation of the enable bit delay controller 500. When the update signal UPDATE When set, based on the setting of the delay time pulse LAGCLK, a subsequent delayed version of the delay time pulse LAGLCK is generated by the delay element 501 and supplied to the multiplexer 502 at the contact points LC0 to LC15. The delay lock-in controller 503 increases or decreases the value of the delay selection signal LAGSELECT[3:0] to select one of the contact points LC0 to LC15 on the signal SLAG such that the value of the signal SLAG is equal to the delay time pulse LAGLCK setting. The pulse signal RESP1 is distributed radially. Therefore, the operation of the delay lock-in controller 503 is substantially similar to the delay-locked loop for converge to a phase delay that is inversely relative to U1A/B to U15A/B less than the corresponding inverse relative U1A/B. Delay of U15A/B. In an embodiment, to provide stability of the bit delay controller 500, once the phase delay is locked, the delay lockout controller 503 increments/decreases the delay selection signal LAGSELECT[3:0] with the selected value, The change in measurement delay is changed by only one bit.

In an embodiment, the measurement of the phase delay operates independently and is asynchronous to the setting of the update signal UPDATE. When the update signal UPDATE is set, the Gray coded value of the delay selection signal LAGSELECT[3:0] is placed on the delay bus signal LAG[3:0]. Therefore, the 4-bit value of 0011 on the delay selection signal LAGSELECT[3:0] can indicate that the radial distributed pulse signal RESP1 is delayed by 120 microseconds after the delay time pulse LAGCLK under the conditions of specific temperature, voltage and frequency. . Since the present invention is used to provide automated and dynamic phase delay measurements, as well as the same clock adjustments in the data bit receiver, the value of the delay selection signal LAGSELECT[3:0] is more accurately described as the path. The delay to the distributed pulse signal RESP1 in three opposite phases U1A/B to U15A/B lags behind the delay time pulse LAGCLK. Due to this Each of the data bit receivers provided by the invention has matching replicas of the opposite U1A/B to U15A/B, and the "delayed" phase can be replicated at each data bit receiver to provide optimal reception of the data.

A Gray coded 4-bit delayed bus signal LAG[3:0] is assigned to each data bit receiver, wherein the data bit receiver is associated with the measured radial distribution network. In general, these will include all data bit receivers in a particular data subgroup, each data bit receiver being driven by the same synchronous data radial distribution flash control signal. In an embodiment, different bit delay controllers 500 can be used for each of the different radially distributed networks. In another embodiment, the Gray encoder 504 can be deleted and the delayed selection signal LAGSELECT[3:0] is transmitted directly to the receiver. In this type of embodiment, the provision must be changed to adjust the glitch in the delay selection signal LAGSELECT[3:0].

The apparatus 500 provided by the present invention is used to perform the functions and operations discussed above. It is to be noted that apparatus 500 includes logic, circuitry, or microcode, or a combination of the above logic, circuitry, or microcode, or equivalent components that can be used to perform the functions and operations described herein. . The components of apparatus 500 for performing these functions and operations may be shared with other circuitry, microcode, etc. for performing other functions and/or operations in the receiving component.

The block diagram shown in Fig. 6 is used to illustrate a detailed embodiment of the fuse adjustment bit delay controller 600 provided by the present invention. The fuse adjustment bit delay controller 600 is configured to enable the delay lockout controller 603 to indicate the amount of delay through the delay selection signal LAGSELECT[3:0] to compensate for wafer lot variations, process variations, and other host components. Other customary factors during or after manufacturing Prime. The fuse adjustment bit delay controller 600 can be implemented in the embodiments of Figures 3 and 4. The fuse adjustment bit delay controller 600 includes a delay element 601 coupled to the multiplexer 602. The multiplexer 602 is coupled to the delay lock-in controller 603 via the signal SLAG. The delay lockout controller 603 generates a 4-bit delay select signal LAGSELECT[3:0], wherein the delay select signal LAGSELECT[3:0] is coupled to the multiplexer 602 for adjusting the logic 606. The adjustment logic 606 is coupled to the Gray encoder 604. The adjustment logic 606 is also coupled to the adjustment valuer (ADJVAL) 605 via the signal SUB[1:0]. The update signal UPDATE is coupled to the Gray encoder 604. When the value represented by the signal SUB[1:0] is adjusted, the Gray encoder 604 generates a Gray coded 4-bit delayed bus signal LAG[3:0]. To indicate the number of matching relative U1A/B to U15A/B, where the number will cause the radial distributed pulse signal REPS1 to lag behind the delay time pulse LAGCLK.

The delay element 601 and the delay lock phase controller 603 receive the delay time pulse LAGCLK. The delay lock-in controller 603 also receives the radially distributed pulse signal REPS1. In the embodiment of FIG. 3, the data flash control signal DSTROBE represents the delay time pulse LAGCLK, and the radial distribution flash control signal DSTROBEN represents the radial distribution pulse signal REPS1. In the apparatus 400 for compensating for errors in the sync data bus on FIG. 4, the delayed pulse signal LAGPLS represents the delay time pulse LAGCLK, and the radial distributed pulse signal REPS1 is represented by the same name. The delay element 601 includes a plurality of inverse relative U1A/B to U15A/B. The contact points LC0 to LC15 are coupled to each of the opposite sides U1A/B to U15A/B, and the contact points LC0 to LC15 are coupled to the multiplexer 602. In the embodiment of Fig. 6, 15 anti-relative U1A/B to U15A/B are matched anti-relatives, that is, each of the inverse U1A/B to U15A/B inverters has 20 picoseconds. Delay (ie each counter) Both U1A/B to U15A/B have a delay of 40 picoseconds), which is an acceptable resolution for measuring the phase delay in a receiving element with an operating speed of approximately 500 MHz to 1.5 GHz. Other embodiments may consider using different numbers of inverse relative U1A/B to U15A/B based on appropriate applications. The anti-relative U1A/B to U15A/B having a delay of 40 picoseconds is commensurate with a receiving element fabricated in accordance with the 28 nm CMOS process and operating in the above frequency range. It should be noted that the architecture shown in FIG. 5 is used to reveal that the present invention can be modified according to different processes and different operating frequencies to improve accuracy and resolution.

The Gray encoder 604 generates a Gray coded delayed bus signal LAG[3:0] when the value represented by the vector signal ALAG[3:0] is adjusted to indicate that the phase of the radially distributed pulse signal REPS1 lags behind The time of the LAGCLK, which is the adjustment time required for the data flash control signal provided by the present invention to be transmitted to the data bit receiver through the radial distribution network.

In terms of operation, as described above, the update signal UPDATE may enable or disable the operation of the enable fuse adjustment bit delay controller 600. When the update signal UPDATE is set, based on the setting of the delay time pulse LAGCLK, a subsequent delayed version of the delay time pulse LAGLCK is generated by the delay element 601 and supplied to the multiplexer 602 at the contact points LC0 to LC15. The delay lock-in controller 603 increases or decreases the value of the delay selection signal LAGSELECT[3:0] to select one of the contact points LC0 to LC15 on the signal SLAG such that the value of the signal SLAG is equal to the delay time pulse LAGLCK The radially distributed pulse signal RESP1 is set. Therefore, the operation of the delay lock-in controller 603 is substantially similar to the delay-locked loop to converge to a phase delay which is an inverse relative U1A/B to U15A/B less than the corresponding inverse relative U1A/B to U15A /B The delay is provided to provide stability of the fuse adjustment bit delay controller 600. Once the phase delay is locked, the delay lock-in controller 603 increments/decreases the delay selection signal LAGSELECT[3:0] with the selected value so that the change in measurement delay changes by only one bit.

In terms of operation, in one embodiment, adjustment logic 606 receives the compensation value on signal SUB[1:0] and performs a subtraction operation on delay selection signal LAGSELECT[3:0]. The value of the signal SUB[1:0] indicates the amount subtracted by the delay selection signal LAGSELECT[3:0], wherein the signal of the signal SUB[1:0] is from the value adjuster 605. In one embodiment, SUB[1:0] indicates the number of bits of the delay selection signal LAGSELECT[3:0] that are shifted to the right. Then, the adjustment logic 606 subtracts the delay selection signal LAGSELECT[3:0] of the delay selection signal LAGSELECT[3:0] to the right to generate a 4-bit vector signal ALAG[3:0 for adjustment. ]. In one embodiment, the number of bits of the right offset delay selection signal LAGSELECT[3:0] is displayed in the first table.

In one embodiment, the value adjuster 605 includes one or more metal or polysilicon fuses, wherein the fuses are burned in the process of the component or IC. In another embodiment, the adjustment logic 606 can be a programmable device or an IC And the memory of reading only. In another embodiment, the value adjuster 605 can be external to the device or IC and provide the signal SUB[1:0] as a signal for transmission to an I/O pin (not shown) on the device or IC. In other embodiments of the numerical adjuster 605, the signal SUB[1:0] signal is more or less than two signals, but is not limited thereto. By the value adjuster 605 and the adjustment logic 606, the designer can adjust the delay amount indicated by the delay lock controller 603 through the delay selection signal LAGSELECT[3:0] to compensate for wafer batch variation, process variation, and Other conventional factors during or after the manufacture of the IC. The adjustment logic 606 subtracts the value of the delay selection signal LAGSELECT[3:0] from the rightward offset of the delay selection signal LAGSELECT[3:0] according to the indication of SUB[1:0] to generate an adjustment for 4-bit vector signal ALAG[3:0].

In an embodiment, the measurement of the phase delay operates independently and is asynchronous to the setting of the update signal UPDATE. When the update signal UPDATE is set, the Gray coded value of the delay selection signal LAGSELECT[3:0] is placed in the delay bus signal LAG[3:0]. Therefore, the 4-bit value of 0011 on the delay selection signal LAGSELECT[3:0] can be indicated under certain temperature, voltage and frequency conditions, and RESP1 is delayed by 120 microseconds after the delay time pulse LAGCLK. Since the present invention is used to provide automated and dynamic phase delay measurements, as well as adjustment of the same clock in the data bit receiver, the value of the delay selection signal LAGSELECT[3:0] is more accurately described as radial The distributed pulse signal RESP1 lags behind the delay time pulse LAGCLK by three anti-relative U1A/B to U15A/B delays. Since each of the data bit receivers provided by the present invention has these matching copies of the opposite U1A/B to U15A/B, the "delayed" phase can be copied at each data bit receiver to provide data. The best reception. The value of 01 on signal SUB[1:0] indicates that adjustment logic 606 offsets the value of delay selection signal LAGSELECT[3:0] one bit to the right, and the true value of self-delay selection signal LAGSELECT[3:0] (For example, 0011) Subtract the value of the rightward offset (for example, 0001), thus presenting that the value of the delayed bus signal LAG[3:0] is 0010, indicating that the radial distributed pulse signal RESP1 lags behind only 80 picoseconds. The delay time pulse LAGCLK, rather than the delayed selection signal LAGSELECT[3:0], should be 120 microseconds.

Gray coded 4-bit delay bus signal LAG[3:0] is assigned to each data bit receiver, where the data bit receiver is associated with the measured radial distribution network. In general, these will include all data bit receivers in a particular data subgroup, each data bit receiver being driven by the same synchronous data radial distribution flash control signal. In an embodiment, different fuse adjustment bit delay controllers 600 can be used for each of the different radial distribution networks. In another embodiment, the Gray encoder 604 can be detected and the vector signal ALAG[3:0] is directly transmitted to the receiver. In another type of embodiment, the configuration must be changed to adjust the disturbance in the delay selection signal LAGSELECT[3:0].

The fuse adjustment bit delay controller 600 provided by the present invention is used to perform the functions and operations discussed above. It is to be noted that the fuse adjustment bit delay controller 600 includes logic, circuitry, or microcode, or a combination of the above logic, circuitry, or microcode, or can be used to perform the present invention. The equivalent of function and operation. Elements of the fuse adjustment bit delay controller 600 for performing these functions and operations may be shared with other circuits, microcode, etc. for performing other functions and/or operations in the receiving elements.

The block diagram shown in FIG. 7 is used to illustrate a detailed embodiment of the Joint Test Action Group (JTAG) adjustment bit delay controller 700 provided by the present invention. The JTAG adjustment bit delay controller 700 is configured to enable the delay lockout controller 703 to delay the amount of delay indicated by the delay selection signal LAGSELECT[3:0] to compensate for wafer lot variations, process variations, and other host components. Other conventional factors during or after manufacturing. The JTAG adjustment bit delay controller 700 can be implemented in the embodiments of Figures 3 and 4. The JTAG adjustment bit delay controller 700 includes a delay element 701 coupled to the multiplexer 702. The multiplexer 702 is coupled to the delay lock controller 703 via the signal SLAG. The delay lockout controller 703 generates a 4-bit delay select signal LAGSELECT[3:0], wherein the delay select signal LAGSELECT[3:0] is coupled to the multiplexer 702 and the adjustment logic 706. The adjustment logic 706 is coupled to the Gray encoder 704. Adjustment logic 706 is also coupled to JTAG interface 705 via signal SUB[1:0]. The JTAG interface 705 receives the control signal JTAG[N:0] on the standard JTAG bus, wherein the control signal JTAG[N:0] provides information that the delay lock controller 703 determines the delay adjustment. The update signal UPDATE is coupled to the Gray encoder 704, wherein the Gray encoder 704 generates a Gray coded 4-bit delayed bus signal LAG[3:0 when the value represented by the signal SUB[1:0] is adjusted. ], to indicate the number of matching inverses U1A/B to U15A/B, where the number causes the radial distributed pulse signal REPS1 to lag behind the delay time pulse LAGCLK.

The delay element 701 and the delay lock-in controller 703 receive the delay time pulse LAGCLK. The delay lock-in controller 703 also receives the radially distributed pulse signal REPS1. In the embodiment of FIG. 3, the data flash control signal DSTROBE represents a delay time pulse LAGCLK, and the radial distribution flash control signal DSTROBEN represents a path. The distributed pulse signal REPS1. In the apparatus 400 for compensating for errors in the sync data bus of FIG. 4, the delayed pulse signal LAGPLS represents the delay time pulse LAGCLK, and the signal of a similar name represents the radial distributed pulse signal REPS1. The delay element 701 includes a plurality of inverse relative U1A/B to U15A/B. The contact points LC0 to LC15 are coupled to each of the opposite sides U1A/B to U15A/B, and the contact points LC0 to LC15 are coupled to the multiplexer 702. In the embodiment of Fig. 7, 15 anti-relative U1A/B to U15A/B are matched inverses, that is, each of the anti-relative U1A/B to U15A/B inverters has 20 picoseconds. The delay (i.e., each of the inverse U1A/B to U15A/B has a delay of 40 picoseconds), which is acceptable for measuring the phase delay in a receiving element having an operating speed of approximately 500 MHz to 1.5 GHz. Resolution. Other embodiments may consider using different numbers of inverse relative U1A/B to U15A/B based on appropriate applications.

The Gray encoder 704 generates a Gray coded delayed bus signal LAG[3:0] when the value represented by the vector signal ALAG[3:0] is adjusted to indicate that the phase of the radially distributed pulse signal REPS1 lags behind The time of the LAGCLK, which is the adjustment time required for the data flash control signal provided by the present invention to be transmitted to the data bit receiver through the radial distribution network.

In terms of operation, as described above, the update signal UPDATE may enable or disable the operation of the JTAG adjustment bit delay controller 700. When the update signal UPDATE is set, based on the setting of the delay time pulse LAGCLK, a subsequent delayed version of the delay time pulse LAGLCK is generated by the delay element 701 and supplied to the multiplexer 702 at the contact points LC0 to LC15. The delay lock controller 703 increases or decreases the value of the delay selection signal LAGSELECT[3:0] to select one of the contact points LC0 to LC15 on the signal SLAG, so that the signal The value of SLAG is equal to the radial distributed pulse signal RESP1 that is behind the delay time pulse LAGLCK. Therefore, the operation of the delay lock-in controller 703 is substantially similar to the delay-locked loop to converge to a phase delay which is an inverse relative to U1A/B to U15A/B less than the corresponding inverse relative U1A/B to U15A. The delay of /B provides the stability of the JTAG adjustment bit delay controller 700. Once the phase delay is locked, the delay lock-in controller 703 increments/decreases the delay selection signal LAGSELECT[3:0] with the selected value such that the change in measurement delay changes by only one bit.

In terms of operation, the conventional JTAG stylization technique is used to indicate the correct amount of compensation via the signal SUB[1:0] through stylization. Stylized settings are made when the host is in a state that allows JTAG to be stylized, such as the RESET state. If it is not in this state, the signal SUB[1:0] indicates the value of the compensation. As shown in Figure 7, the JTAG adjusts the bit delay controller 700, the adjustment logic 706 receives the compensation value on the signal SUB[1:0] and performs the subtraction function on the delay selection signal LAGSELECT[3:0]. The value of the signal SUB[1:0] indicates the amount of subtraction from the delayed selection signal LAGSELECT[3:0]. In one embodiment, the signal SUB[1:0] indicates the number of bits of the delayed selection signal LAGSELECT[3:0] that are shifted to the right. Then, the adjustment logic 706 subtracts the delay selection signal LAGSELECT[3:0] of the delay selection signal LAGSELECT[3:0] to the right to generate a 4-bit vector signal ALAG[3:0] for adjustment. . In one embodiment, the number of bits of the right offset delay selection signal LAGSELECT[3:0] is displayed in the second table.

Embodiments of other JTAG interfaces 705 include, but are not limited to, more or less than two signals for the SUB[1:0] signal. Through the JTAG interface 705 and the adjustment logic 706, the designer can adjust the delay amount indicated by the delay lock controller 703 through the delay selection signal LAGSELECT[3:0] to compensate for wafer lot variations, process variations, and others. Other conventional factors during or after the manufacture of the IC. The adjustment logic 706 thus subtracts the value of the delay selection signal LAGSELECT[3:0] from the rightward offset of the delay selection signal LAGSELECT[3:0] to produce a 4-bit vector signal ALAG[3: 0].

In an embodiment, the measurement of the phase delay operates independently and is asynchronous to the setting of the update signal UPDATE. When the update signal UPDATE is set, the Gray coded value of the delay selection signal LAGSELECT[3:0] is placed on the delay bus signal LAG[3:0]. Therefore, the 4-bit value of 0011 on the delay selection signal LAGSELECT[3:0] can be marked under the condition of specific temperature, voltage and frequency, and the radial distributed pulse signal RESP1 lags behind the delay time pulse LAGCLK by 120 picoseconds. . Since the present invention is used to provide automated and dynamic phase delay measurements, as well as adjustment of the same clock in the data bit receiver, the value of the delay selection signal LAGSELECT[3:0] is more accurately described as radial The distributed pulse signal RESP1 lags behind the delay time pulse LAGCLK by three anti-relative U1A/B to U15A/B delays. Since each of the data bit receivers provided by the present invention has these matching copies of the opposite U1A/B to U15A/B, the "delayed" phase can be received at each data bit. The device is copied to provide optimal reception of the data. The value of 01 on signal SUB[1:0] indicates that adjustment logic 706 offsets the value of delay selection signal LAGSELECT[3:0] one bit to the right, and the true value of self-delay selection signal LAGSELECT[3:0] (For example, 0011) Subtract the value of the rightward offset (for example, 0001), thus presenting that the value of the delayed bus signal LAG[3:0] is 0010, indicating that the radial distributed pulse signal RESP1 lags behind only 80 picoseconds. The delay time pulse LAGCLK, rather than the delayed selection signal LAGSELECT[3:0], should be 120 microseconds.

Gray coded 4-bit delay bus signal LAG[3:0] is assigned to each data bit receiver, where the data bit receiver is associated with the measured radial distribution network. In general, these will include all data bit receivers in a particular data subgroup, each data bit receiver being driven by the same synchronous data radial distribution flash control signal. In one embodiment, a different JTAG adjustment bit delay controller 700 is used for each of the different radially distributed networks. In another embodiment, Gray encoder 704 can be detected and vector signal ALAG[3:0] is transmitted directly to the receiver.

The JTAG adjustment bit delay controller 700 provided by the present invention is used to perform the functions and operations discussed above. It is to be noted that the JTAG adjustment bit delay controller 700 includes logic, circuitry, or microcode, or a combination of the above logic, circuitry, or microcode, or can be used to perform the functions described herein. The equivalent of the operation. Elements of the JTAG adjustment bit delay controller 700 for performing these functions and operations may be shared with other circuits, microcode, etc. for performing other functions and/or operations in the receiving element.

Figure 8 is a diagram of the synchronous delay receiver 800 provided by the present invention. Block diagram. The synchronous delay receiver 800 can be implemented in the embodiments of FIGS. 3 to 4 to introduce a transmission path delayed to the data bit DATAX, wherein the data bit DATAX is from a transmission element, and the delay is delayed. As indicated by the bus signal LAG[3:0], as shown in Figures 3 through 8, the delayed bus signal LAG[3:0] is updated in accordance with the bit delay control element proposed by the present invention.

Synchronization delay receiver 800 includes a delay element 801 for receiving data bit DATAX. The delay element 801 is coupled to the multiplexer 802 via a delay bit signal DDATAX[15:0]. The delayed bus signal LAG[3:0] is coupled to the multiplexer 802. The multiplexer 802 is coupled to the sync bit receiver 803 via a select delay signal SDATAX. The sync bit receiver 803 receives the selection delay signal SDATAX and the radial distribution flash control signal DSTROBEX. As shown in Figures 3 through 4, the radially distributed flash control signal DSTROBEX is distributed by radial distribution elements 303 and 403. The sync bit receiver 803 generates a receive bit signal RDATAX.

In terms of operation, the bit delay controller provided by the present invention is used to update the value of the delayed bus signal LAG[3:0] so that the data bit DATAX related to the phase of the flash control signal DSTROBEX can be optimal. Received in the status. In one embodiment, this optimum condition is during a period of approximately halfway after the radial distribution of the flash control signal DSTROBEX is set. Other embodiments are to modify the location of the data bit DATAX in order to increase its setup time or reduce its holding time. The delay element 801 is a copy of the delay elements 501, 601, 701, 801 described in Figures 1 through 8, and includes fifteen matching inverses (not shown). Thus, in one embodiment, the delay bit signal DDATAX[15:0] includes data The sixteen consecutive delayed versions of the bit DATAX range from no delay to through all fifteen inverse relative delays.

The multiplexer 802 uses the value of the delayed bus signal LAG[3:0] to select one of the delay bit signals DDATAX[15:0]. The selected signal is routed to the sync bit receiver 803 and becomes the select delay signal SDATAX. When the radial distribution flash control signal DSTROBEX is switched, the sync bit receiver 803 registers the value of the selection delay signal SDATAX and outputs this value to become the received bit signal RDATAX. The received bit signal RDATAX represents the reception state of the data bit DATAX.

Figure 9 is a block diagram of a precision delay element 900 provided by the present invention. The precision delay element 900 can be replaced with the delay elements 501, 601, 701, 801 shown in Figures 5 through 8 to provide a finer resolution of delay measurement and delay introduction in embodiments of the present invention. The precision delay element 900 includes a first multiplexer 901 having a first input belonging to a low logic level (e.g., 0) and a second input belonging to a high logic level (e.g., 1). In an embodiment, the high logic level includes a core voltage (eg, supply voltage VDD) and the low logic level includes a reference voltage (eg, ground). In another embodiment, other embodiments may be employed. The first multiplexer 901 uses the delay time pulse LAGCLK as a signal selection to select the signal of the first input or the signal of the second input. The precision delay element 900 also includes a second multiplexer 902 having a first input belonging to 1 and a second input belonging to 0, the architecture of which is opposite to that of the first multiplexer 901. The delay time pulse LAGCLK is also coupled to the select input of the second multiplexer 902. In the embodiments described in FIGS. 5 to 7, the delay time pulse LAGCLK represents a signal for measuring a transmission delay or a signal of another similar name or the like. In the embodiment described in FIG. 8, when delaying The inter-pulse LAGCLK represents the delayed data bit DATAX.

The precision delay element 900 includes a first group of fifteen delay inverters (U0A to U14A) connected in series, wherein the output of the first multiplexer 901 is coupled to the input of the inverter U0A, and the inverter U14A The output is coupled to the most delayed signal on tap point LC31. The precision delay element 900 also includes a second group of 15 delay inverters (U0B to U14B) connected in series, wherein the output of the second multiplexer 902 is coupled to the input of the inverter U0B, and the inverter U14B The output is coupled to the next most delayed signal on tap point LC30.

The outputs of all delay-like inverters (such as U0A and U0B, U5A and U5B) are coupled together by full keeper inverter pairs K1 to K15. The outputs of the even-numbered inverters (eg, U0A, U2A, etc.) in the first group of fifteen delay inverter pairs are coupled to subsequent delayed signals on the odd-numbered tap points (LC1, LC3 to LC31). The inputs of the even inverters (e.g., U0B, U2B, etc.) in the second group of fifteen delay inverters are coupled to subsequent delayed signals on the even-numbered taps (LC0, LC2 to LC30). Each of the inverting delays U0A to U14A, U0B to U14B is matched. In one embodiment, the delay of each inverter is substantially 20 picoseconds, and therefore, the most delayed signal at tap point LC31 represents a delay of approximately 300 picoseconds in the delay time pulse LAGLCK.

In terms of operation, although a high level is used in the operational discussion, any state of the delay time pulse LAGCLK can be used to generate a subsequent delayed version and serve as the output of tap points LC0 through LC31. Therefore, in one embodiment, when the delay time pulse LAGCLK is 1, the input of the inverter U0A is 0 and the input of the inverter U0B is 1. Therefore, the tap point LC0 is 1, and the output of the inverter U0A As 1, the output of the inverter U0B is 0, and the value of the tap point LC1 is 1 after the delay of the inverter until the most delayed version of the delay time pulse LAGCLK appears at the tap point LC31. The function of the full counter-relative K1 to K15 is to ensure that the state change on the tap points LC1 to LC31 is synchronized with the state change of its corresponding similarly encoded anti-relative U0[A:B] to U14[A:B].

The precision delay element 900 proposed by the present invention can be implemented on any of the multiplexers 502, 602, 702, 802, 902 described above. However, the width of the associated delay signal must be increased by one bit to accommodate the increased resolution.

Portions of the present invention and corresponding detailed descriptions thereof are presented in software, or algorithms and symbolic representations of the operation of data bits in a computer memory. The nature of these descriptions and representations is communicated between those of ordinary skill in the art. The algorithm referred to herein, as it is generally cited, is a series of steps envisioned to result in self-consistency of the expected results. These steps require physical manipulation of the physical device. Generally, though not necessarily, these devices are stored, transferred, combined, compared, and otherwise manipulated in the form of optical, electrical, or magnetic signals. In principle, reference to such bits, values, elements, symbols, characteristics, terms, numbers or other signals has proven to be temporally convenient for common use.

However, it should be noted that all of these and similar terms will be linked to appropriate physical devices, which are merely convenient labels for these devices. Unless specifically described or clearly stated, such terms as "processing" or "computing" or "computing" or "judgement" or "display" or other terms are used to describe computer systems, microprocessors, central processing units. Or the processing and behavior of other electronic computing devices. The above electronic computing device will appear as a scratchpad or memory of the computer system The physical or electronic unit in operation or conversion becomes a similar material that is present in a physical unit of a computer system memory, scratchpad, or other information storage, transmission or display device.

It is to be noted that the software implementation of the present invention is typically encoded in some type of stylized storage medium or in some types of transmission media. Stylized storage media can be electronic (eg, read-only memory, flash-read only memory, electronically programmable read-only memory), random access magnetic memory (such as floppy or hard disk), or optical (such as compact disk read-only memory, or CD ROM), and can be read-only or random access. Similarly, the transmission medium can be a metal wire, a twisted wire pair, a coaxial wire, an optical fiber, or other conventionally suitable transmission medium. The invention is not limited to these aspects of the disclosed embodiments.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can be modified, replaced and retouched without departing from the spirit and scope of the invention. . For example, those skilled in the art can readily appreciate that many of the features, functions, processes, and materials described herein can be modified within the scope of the invention.

300‧‧‧Devices for compensating for errors in synchronous data busbars

301, 311‧‧‧ nodes

302‧‧‧Internal radial distribution flash control signal

303.1~303.N‧‧‧ delay element

305‧‧‧ bit delay controller

313‧‧‧Flash Control Receiver

303‧‧‧ Radial distribution elements

304‧‧‧Synchronous delay receiver

312~3N2‧‧‧ signal

DATA1~DATAN‧‧‧ data bit signal

DSTROBE1~DSTROBEN‧‧‧radially distributed flash control signal

DSTROBE‧‧‧ data flashing signal

LAG[3:0]‧‧‧delay bus signal

OUT1~OUTN‧‧‧ output signal

UPDATE‧‧‧ update signal

Claims (42)

An apparatus for compensating for errors in a synchronous data bus, comprising: a replica distribution component for receiving a delayed pulse signal and generating a replica flash control signal, wherein the replica distribution component includes a radial for a data flash control signal a replica transmission characteristic of the distributed component; a one-bit delay controller for measuring the time between the delayed pulse signal and the duplicated flash control signal, and generating a delayed busbar signal on a delayed bus bar to indicate the time; a synchronous delay receiver coupled to the bit delay controller for receiving a first radial distributed flash control signal and receiving a data bit signal among the radially distributed flash control signals, and This time delays the registration of the data bit signal. The apparatus for compensating for an error in a synchronous data bus as described in claim 1, wherein the data flash signal and the data bit signal are received by a corresponding device, and the radial distribution flash control signal and the data The bit signal is sent by a transmission element. The apparatus for compensating for errors in a synchronous data bus as described in claim 2, wherein the corresponding device comprises an x86 compatible microprocessor. The apparatus for compensating for an error in a synchronization data bus as described in claim 1, wherein the bit delay controller includes a plurality of first matching inverses, and the time is expressed as the first matching inverse Zero or at least one function. The apparatus for compensating for an error in a synchronous data bus as described in claim 4, wherein the synchronous delay receiver includes a plurality of second matching inversions Yes, and the second matching inverse relatives are copies of the first matching inverse counterparts. The apparatus for compensating for errors in a synchronization data bus as described in claim 5, wherein the synchronous delay receiver delays registration of the data bit signal by using zero or at least one of the second matching inverses, and The number of such second matching inverses used is indicated by the delayed bus signal. The device for compensating for the error in the synchronization data bus as described in claim 1 further includes: a radial distribution component for receiving the data flash control signal and generating the radial distribution flash control signal, wherein the Each of the plurality of synchronous delay receivers corresponding to the radial distribution flash control signal receives one of the radially distributed flash control signals, and each of the radial distributed flash control signals has a corresponding The synchronous flashing receivers have equal transmission characteristics of the data flash control signal. An apparatus for compensating for errors in a synchronous data bus, comprising: a microprocessor comprising: a replica distribution component for receiving a delayed pulse signal and generating a copy flash control signal, wherein the replica distribution component comprises a a replica transmission characteristic of a radial distribution component of the data flash control signal; a one-bit delay controller for measuring the time between the delayed pulse signal and the replicated flash control signal and generating a delayed convergence on the delay bus a signal to indicate the time; a synchronous delay receiver coupled to the bit delay controller for receiving A first one of the radially distributed flash control signals radially distributes the flash control signal and receives a data bit signal, and delays registration of the data bit signal by the time. The apparatus for compensating for an error in a synchronous data bus as described in claim 8 wherein the data flash signal and the data bit signal are received by the microprocessor, and the radial distributed flash control signal and the The data bit signal is sent by a transmission element. The apparatus for compensating for errors in a synchronous data bus as described in claim 9 wherein the microprocessor comprises an x86 compatible microprocessor. The apparatus for compensating for an error in a synchronization data bus as described in claim 8 wherein the bit delay controller includes a plurality of first matching inverses, and the time is expressed as the first matching inverse Zero or at least one function. The apparatus for compensating for an error in a synchronous data bus as described in claim 11, wherein the synchronous delay receiver includes a plurality of second matching inverses, and the second matching inverses are the first matching inverses Relative to copying. The apparatus for compensating for an error in a synchronous data bus as described in claim 12, wherein the synchronous delay receiver delays registration of the data bit signal by using zero or at least one of the second matching The number of such second matching inverse relatives used is indicated by the delayed bus signal. The device for compensating for the error in the synchronous data bus as described in claim 8 of the patent scope further includes: a radial distribution component for receiving the data flash control signal and generating the radial distribution flash control signal, wherein each of the plurality of synchronous delay receivers corresponding to the radial distribution flash control signals is received by the synchronous delay receiver Each of the radially distributed flash control signals radially distributes the flash control signal, and each of the radially distributed flash control signals has a transmission characteristic equal to the data flash control signal of the corresponding synchronous delay receiver . A method for compensating for errors in a synchronous data bus, comprising: replicating a transmission characteristic of a radial distribution component for a data flash control signal by a replica distribution component; receiving a delayed pulse signal; Transmitting characteristics, generating a copying flash control signal; measuring a time between the delayed pulse signal and the copying the flashing signal by a one-bit delay controller, wherein the transmission time begins with the setting of the first signal and ends with Setting the second signal; generating a delay bus signal on a delay bus to indicate the transmission time; receiving a first radial distribution flash of the plurality of radial distribution flash signals by a synchronous delay receiver a control signal and a data bit signal; and delaying the registration of the data bit signal by the time. The method for compensating for errors in a synchronization data bus as described in claim 15 wherein the data flash signal and the data bit signal are received by a corresponding device and are transmitted by a transmission component. A method for compensating for errors in a synchronous data bus as described in claim 16 wherein the corresponding device comprises an x86 compatible microprocessor. A method for compensating for errors in a synchronization data bus as described in claim 15 wherein the time is expressed as a function of zero or at least one of the plurality of first matching inverses. The method for compensating for the error on the synchronization data bus as described in claim 18, further comprising: replicating the first matching inverses by using a plurality of second matches. The method for compensating for an error in a synchronization data bus as described in claim 19, wherein the step of delaying registration of the data bit signal comprises: transmitting the data bit by using zero or at least one of the second matches A meta-signal, and the number of the second matching inverse relatives used is labeled to the delayed bus signal. The method for compensating for the error of the synchronization data bus on the fifteenth item of the patent application scope includes: generating the radial distribution flash control signals, and distributing the radial distribution flash control signals to a plurality of corresponding synchronous delay receiving And each of the radially distributed flash control signals has a transmission characteristic equal to the data flash control signal of the corresponding synchronous delay receivers. An apparatus for compensating for errors in a synchronous data bus, comprising: a replica distribution component for receiving a first signal and generating a second signal, wherein the replica distribution component includes a radial distribution for a data flash control signal a replication transmission characteristic of the component, and the replication distribution component equalizes all transmission paths of the data flash signal distribution; a one-bit delay controller for measuring a transmission time and generating a delay bus on a delay bus Signal to indicate the transmission time, where The transmission time starts from the setting of the first signal and ends at the setting of the second signal, and the delayed bus line signal is used to indicate a transmission time, wherein the bit delay controller comprises: a delay phase lock controller And selecting one of a plurality of subsequent delayed versions of the first signal, and generating a delay selection signal on a delay selection bus to indicate the transmission time, wherein the selected delayed version and the second signal are Alignment; an adjustment logic coupled to a circuit and the delay selection bus for adjusting the delay selection signal according to a value specified by the circuit to generate a vector signal, wherein the vector signal is output to an adjustment delay a bus; and a Gray encoder that gray-codes the vector signal to generate the delayed bus signal. The apparatus for compensating for an error in a synchronous data bus as described in claim 22, wherein the delay lock controller selects an output state by increasing or decreasing a complex number of a multiplexer, and the first signal is One of the subsequent delayed versions is selected, wherein the subsequent delayed versions are inputs to the multiplexer. The apparatus for compensating for an error in a synchronization data bus as described in claim 23, wherein the bit delay controller further comprises: a plurality of first matching inverses, and the transmission time is expressed as the first matching A function of zero or at least one of the opposite. The device for compensating for the error in the synchronous data bus as described in claim 24 of the patent scope further includes: a synchronous delay receiver coupled to the bit delay controller for receiving a data bit signal and one of the plurality of radially distributed flash control signals, and delaying the registration of the data bit signal by the delay time . A device for compensating for errors in a synchronous data bus as described in claim 22, wherein the circuit includes at least one fuse. The apparatus for compensating for errors in a synchronous data bus as described in claim 22, wherein the circuit comprises a programmable read only memory. A device for compensating for errors in a synchronous data bus as described in claim 22, wherein the circuit includes an external component coupled to an input/output pin of the device. An apparatus for compensating for errors in a synchronous data bus, comprising: a microprocessor comprising: a replica distribution component for receiving a first signal and generating a second signal, wherein the replica distribution component comprises a data a replica transmission characteristic of a radial distribution component of the flash control signal, and the replication distribution component equalizes all transmission paths of the data flash control signal distribution; a one-bit delay controller for measuring a transmission time and generating a delayed convergence Aligning one of the delay bus signals to indicate the transmission time, wherein the transmission time begins with a setting of a first signal and ends with a second signal setting, and a radial distribution component generates the second signal as the a delayed version of the first signal, the delayed version being part of a radial transmission path corresponding to a data flash control signal, wherein the bit delay controller comprises: a delay lock phase controller for selecting the first One of a plurality of subsequent delayed versions of a signal, and one delay selection on a delay selection bus Selecting a signal to indicate the transmission time, wherein the selected delayed version is consistent with the setting of the second signal; an adjustment logic coupled to a circuit and the delay selection bus to be used according to the value specified by the circuit The delay selection signal is adjusted to generate a vector signal, wherein the vector signal is output to an adjustment delay bus; and a Gray encoder that gray-codes the vector signal to generate the delayed bus signal. The apparatus for compensating for an error in a synchronous data bus as described in claim 29, wherein the delay phase lock controller selects the first signal by increasing or decreasing a state of the selected output on a multiplexer. One of a plurality of subsequent delayed versions, wherein a plurality of subsequent delayed versions are inputs to the multiplexer. The apparatus for compensating for an error in a synchronization data bus as described in claim 30, wherein the bit delay controller further comprises: a plurality of first matching inverses, and the transmission time is expressed as the first matching A function of zero or at least one of the opposite. The device for compensating for the error in the synchronization data bus as described in claim 31, further comprising: a synchronous delay receiver coupled to the bit delay controller for receiving a data bit signal and a plurality of One of the flash control signals is radially distributed, and the registration of the data bit signal is delayed by the delay time. A device for compensating for errors in a synchronous data bus as described in claim 29, wherein the circuit includes at least one fuse. The apparatus for compensating for errors in a synchronous data bus as described in claim 29, wherein the circuit comprises a programmable memory. A device for compensating for errors in a synchronous data bus as described in claim 29, wherein the circuit includes an external component coupled to an input/output pin of the device. A method of compensating for errors in a synchronous data bus, comprising: receiving a first signal by a replica distribution component, and generating a second signal, wherein the replica distribution component includes a radial distribution for a data flash control signal a replication transmission characteristic of the component, and the replication distribution component equalizes all transmission paths of the data flash signal distribution; measuring a transmission time, wherein the transmission time starts at a setting of a first signal and ends at a second signal The setting, wherein the measuring the transmission time comprises: selecting one of a plurality of subsequent delayed versions of the first signal, wherein the selected delayed version is consistent with the establishment of the second signal; according to a value specified by the circuit Adjusting a delay selection signal to generate a vector signal; and gray coding the vector signal to generate a delayed bus line signal on a delayed bus. The method for compensating for errors in a synchronous data bus as described in claim 36, wherein the step of selecting one of a plurality of subsequent delayed versions of the first signal further comprises: increasing or decreasing on a multiplexer The state of the output is selected, wherein a plurality of subsequent delayed versions are inputs to the multiplexer. The method for compensating for errors in a synchronization data bus as described in claim 37, wherein the step of measuring the transmission time further comprises: indicating the transmission time as zero or at least one of the first matching inverses. The function. The method for compensating for the error in the synchronous data bus as described in claim 38, further comprising: coupling the delay bus to a synchronous delay receiver, wherein the synchronous delay receiver is configured to receive a data bit signal and a plurality of One of the radial distribution flash control signals, and the registration of the data bit signal is delayed by the delay time. A method of compensating for errors in a synchronous data bus as described in claim 36, wherein the circuit includes at least one fuse. A method of compensating for errors in a synchronous data bus as described in claim 36, wherein the circuit includes a programmable memory. A method of compensating for errors in a synchronous data bus as described in claim 36, wherein the circuit includes an external component coupled to an input/output pin of the device.