TWI566255B - Five transistor static random access memory - Google Patents

Description

5T static random access memory

The invention relates to a single port static random access memory (SRAM), in particular to an effective improvement of the standby performance of the 單埠SRAM, and can effectively improve the reading speed and effectively reduce Leakage current and can solve the problem that SRAM is difficult to write logic 1 with a single bit line.

As is shown in FIG. 1a, the static random access memory (SRAM) mainly includes a memory array, which is composed of a plurality of memory blocks (memory block, MB _1). , MB _{2 ,} etc., each memory block is composed of a plurality of columns of memory cells and a plurality of columns of memory cells. Each column of memory cells and each row of memory cells each include a plurality of memory cells; a plurality of word lines (word line, WL ₁ , WL _{2 ,} etc.), each word line corresponding to a plurality of columns of memory One of the body cells; and a plurality of bit line pairs (BL ₁ , BLB ₁ ... BL _m , BLB _{m ,} etc.), each bit line pair corresponding to a plurality of rows of memory cells One row, and each bit line pair is composed of one bit line (BL ₁ ... BL _m ) and one complementary bit line (BLB ₁ ... BLB _m ).

Figure 1b shows a 6T單埠 static random access memory (SRAM) cell A circuit diagram in which PMOS transistors (P11) and (P12) are called load transistors, NMOS transistors (N11) and (N12) are called driving transistors, and NMOS transistors ( N13) and (N14) are called access transistors, WL is a word line, and BL and BLB are bit lines and complementary bit lines, respectively. Since the 單埠SRAM cell requires six transistors, and when the logic 0 is read, in order to avoid the initial operation of the other driver transistor in the initial operation of the read operation, the driver transistor and the access transistor must be driven. The current drive capability ratio (i.e., cell ratio) is set between 2.2 and 3.5, resulting in a high accumulation difficulty and a high price.

The HSPICE transient analysis results of the 6T單埠 SRAM cell shown in Figure 1b during the write operation, as shown in Figure 2, are simulated using the TSMC 90 nm CMOS process parameters.

One way to reduce the number of transistors in a 6T static random access memory (SRAM) cell is disclosed in FIG. Figure 3 shows a circuit diagram of a 5T 單埠 SRAM cell with only a single bit line, compared to the 6T 單埠 SRAM cell of Figure 1b. The random access memory cell has one transistor and one less bit line than the 6T static random access memory cell, but the 5T單埠 SRAM cell does not change the PMOS transistor (P11). And (P12) and NMOS transistor (N11), (N12) and (N13) channel width to length ratio (that is, maintain the same transistor channel width to length ratio as the 6T SRAM cell) to maintain the static noise margin (Static In the case of Noise Margin, SNM), there is a problem that writing logic 1 is quite difficult. Considering that the node A on the left side of the memory cell originally stores logic 0, since the charge of node A is only transmitted from the bit line (BL) alone, it is difficult to write the logic 0 previously written in node A. The cover is written as a logic 1. Figure 5 shows the results of the HSPICE transient analysis simulation of the 5T SRAM cell during the write operation. As shown in Figure 4, it is simulated using the TSMC 90 nm CMOS process parameters. The simulation results confirm that it is quite difficult to write logic 1 in a 5T SRAM cell with a single bit line.

The method for solving the above-mentioned 5T static random access memory cell writing logic 1 is as follows. The first method is to pull the voltage level supplied to the memory cell lower than the power supply voltage when writing. (VDD), so that when writing logic 1 (assuming node A originally stores logic 0, and now wants to write logic 1), by increasing the on-resistance of the driving transistor NMOS transistor (N11) during the write operation The operation of writing the logic 1 can be performed by turning on the driving transistor NMOS transistor (N12), for example, the "Memory System" proposed in Patent Document 1 (US Pat. No. 7,706, 062 B2, April 27, 1999), Patent Document 2 ( "SRAM" for reducing the power supply voltage during write operation, as proposed in TWI426515 B of February 11, 103, and "Write operation" proposed in Patent Document 3 (TWI426514 B, February 11, 103) "Static Static Random Access Memory with Reduced Power Supply Voltage", Patent Document 4 (TWI419162 B, December 11, 102), "Static Static Random Access Memory with Discharge Path" and Patent Literature 5 (Five Transistor, proposed by US2014/0029333 A1 on January 30, 103) SRAM Cell" and so on, these patents can effectively solve the problem of writing logic 1 difficult, but because these patents need to set dual power and / or discharge paths, and the patents must be supplied to the patent The voltage level of the memory cell is pulled lower than the power supply voltage (VDD) and the voltage level supplied to the memory cell is restored to the power supply voltage (VDD) after the writing is completed, thus causing unnecessary The power consumption, in addition, these patents have not considered the problem of reducing the standby power and the reading speed of the 45 nm operating voltage will be reduced to 1.1 ± 30%, so there is still room for improvement.

The second method is to redesign the channel width to length ratio of the PMOS transistors (P11) and (P12) and the NMOS transistors (N11), (N12) and (N13), for example, Non-Patent Document 6 (Satyan and Nalam et al., "5T SRAM with asymmetric sizing for improved read stability", IEEE Journal of Solid-State Circuits ., Vol. 46. No. 10, pp 2431-2442, Oct. 2011.), due to PMOS transistors (P11) and ( The channel width to length ratio of P12) is no longer the same and the channel width to length ratio of NMOS transistors (N11) and (N12) are no longer the same, thus reducing the static noise margin (SNM) and not reducing the standby power. And when the operating voltage of 45 nm is reduced to 1.1±30%, the reading speed is reduced, so there is still room for improvement.

The third method is to increase the word line (WL) voltage level of the access transistor (N13) gate supplied to the memory cell to a voltage higher than the power supply voltage (VDD) for writing. Logic 1 (assuming node A originally stores logic 0, but now wants to write logic 1), by driving the on-resistance of the access transistor (N13) to write the initial instant (initial instant) can drive the transistor NMOS The transistor (N12) is turned on, and the operation of writing the logic 1 is completed. For example, Patent Document 7 (No. TWI404065, August 1, 102) proposes to increase the voltage level of the word line during the write operation. Random access memory, but the word line (WL) voltage level of the access transistor (N13) gate supplied to the memory cell is pulled higher than the power supply voltage (VDD) due to writing. Increased write disturb, and does not take into account the problem of reduced read speed caused by a 45 nm operating voltage drop of 1.1 ± 30%, so there is still room for improvement.

The fourth method is to raise the source voltage level of the driving transistor NMOS transistor (N11) above the ground voltage during writing so as to write logic 1 (assuming that node A originally stores logic 0, and now wants Write logic 1), by increasing the gate voltage level of the driving transistor NMOS transistor (N11), so that the driving transistor NMOS transistor (N12) can be turned on at the initial writing speed, and the writing logic 1 is completed. The operation is, for example, "High-performance static random access memory" proposed in Patent Document 8 (TWI451414, September 1, 103), Patent Document 9 (September 1, 103) "5T單埠SRAM" proposed by the Japanese Patent No. TWI451414, "High-performance Static Random Access Memory", Patent Document 10 (TWI 436359, May 1, 103), Patent Document 11 (103) "5T Static Random Access Memory" proposed by TWI433151 on April 1st, and "Standard Static Current Memory with Low Standby Current" as proposed in Patent Document 12 (TWI425510, February 1, 103) Take memory, but since these patents do not take into account the problem of reduced read speed caused by a 45 nm operating voltage drop of 1.1 ± 30%, there is still room for improvement.

The fifth method is to increase the threshold voltage of the driving transistor NMOS transistor (N11) while reducing the threshold voltage of the access transistor (N13) by writing back gate bias technology. When writing logic 1 (assuming node A originally stores logic 0, but now wants to write logic 1), by increasing the gate voltage level of the driving transistor NMOS transistor (N11), the initial instant energy can be written. The drive transistor NMOS transistor (N12) is turned on to complete the operation of writing logic 1, but the method requires the use of a split well to increase process complexity and is therefore rarely used.

The sixth method is to redesign the connection relationship between the PMOS transistors (P11) and (P12) and the NMOS transistors (N11), (N12) and (N13), for example, Non-Patent Document 13 (Chua-Chin Wang et al) , "A single-ended disturb-free 5T loadless SRAM with leakage sensor and read delay compensation using 40 nm process", 2014 International Symposium on Circuits and Systems, pp 1126-1129, June 2014.) and non-patent document 14 (Shyam Akashe et al., "High density and low leakage current based 5T SRAM cell using 45 nm technology", 2011 International Conference on Nanoscience, Engineering and Technology (ICONSET), pp 346-350, Nov. 2011.), due to these The non-patent literature does not consider the problem of a reduction in reading speed caused by a 45 nm operating voltage drop of 1.1 ± 30%, so there is still room for improvement.

Next, it is discussed to reduce the standby operation by increasing the source voltage of the NMOS transistors (N11) and (N12) in all the memory cells from the original ground voltage to a predetermined voltage higher than the ground voltage. A technology for power consumption, for example, "Double-band static random access memory with discharge path" proposed in Patent Document 15 (No. TW M393773, December 1, 1999), Patent Document 16 (March 21, 1998) "Static random access memory" proposed by TW I307890), "Static random access memory (SRAM) with clamped source potential in standby mode" (Patent Document 17 (June 3, 1997, US Pat. No. 7,382,674 B2) "Static random access memory device and method of reducing standby current", Patent Document 19 (No. US7110317 B2, September 19, 1995), which is proposed in the patent document 18 (No. 7,725,085 B2, August 7, 196) "SRAM employing virtual rail scheme stable against various process-voltage-temperature variations", Non-Patent Document 20 (Tae-Hyoung Kim et al.," A Voltage Scalable 0.26 V, 64 kb 8T SRAM With Vmin Lowering Techniques and Deep Sleep Mode", IEEE Journal of Solid-State Circuits ., Vol. 64, pp 1785-1795, 2009.) 8T SRAM and Non-Patent Document 21 (Ding-Ming Kwai, " Modeling of SRAM Standby Current By Three-Parameter Lognormal Distribution", Design, and Testing, 2009. MTDT '09. IEEE International Workshop on Memory Technology, pp 77-82, Aug. 31 2009-Sept. 2009.), etc. In the standby operation, the literature or the non-patent literature improves the source voltage of the driving transistor (ie, the NMOS transistors N1 and N2 of FIG. 1b) from the original ground voltage to all the memory cells. The predetermined voltage is higher than the ground voltage to reduce the power consumption of the standby operation. However, since the ground voltage of the patent documents or the non-patent literature is higher than the ground voltage, the predetermined voltage is only caused by the leakage current of the transistor. The charging of parasitic capacitance causes the static random access memory to enter the standby mode at a very slow speed, and thus leads to a reduction in the lack of standby performance: that is, the patent documents or non-patent literature Lack of standby start circuit to cause static random-access memory quickly into standby mode, so there is still room for improvement.

In view of this, the main object of the present invention is to provide a 5T static random access memory capable of changing the source of the driving transistor close to the bit line from the original ground voltage by reading the initial instant (initial instant). In order to be lower than the grounding voltage, the driving transistor with a smaller channel width to length ratio can be configured to complete the reading operation, and the logic transistor 0 is not caused to instantaneously turn on the driving transistor away from the bit line. However, the reading operation is hindered, and the writing can also effectively avoid the problem that it is quite difficult to write the logic 1 in the SRAM with a single bit line.

A secondary object of the present invention is to provide a 5T static random access memory capable of effectively causing the SRAM to quickly enter the standby mode by the standby start circuit, thereby effectively improving the standby performance of the SRAM.

Still another object of the present invention is to provide a 5T static random access memory capable of effectively reducing leakage current in a standby mode by a control circuit.

Another object of the present invention is to provide a 5T static random access memory capable of effectively increasing the reading speed by the control circuit.

Another object of the present invention is to provide a 5T static random access memory that can be controlled by two stages to improve the reading speed while avoiding unnecessary power consumption.

The invention provides a 5T static random access memory, which mainly comprises a memory array, a plurality of control circuits (2), a plurality of precharge circuits (3) and a standby start circuit (4), the memory array system It consists of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells is provided with a control circuit, and each memory cell (1) is packaged. a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor N11) and a second inverter (from a second PMOS transistor P12 and a second NMOS transistor) N12 is composed of) and an access transistor (composed of the third NMOS transistor N13). Each control unit (2) is connected to a source of the first NMOS transistor (N11) of each memory cell of the corresponding column memory cell and a source of the second NMOS transistor (N12) In order to control the source voltage of the first NMOS transistor (N11) and the source voltage of the second NMOS transistor (N12) in response to different operation modes. In the first stage of the read mode, the source of the first NMOS transistor (N11) close to the bit line (BL) is changed from the original ground voltage to be lower than the ground voltage, and the configuration is smaller. The first NMOS transistor (N11) and the second NMOS transistor (N12) of the channel width-to-length ratio can complete the read operation, and the logic line 0 is not caused to be far from the bit line (BL). The second NMOS transistor (N12) blocks the read operation due to the instantaneous turn-on, and in the second phase of the read mode, the source of the first NMOS transistor (N11) is further removed from the ground voltage. Low setting back to ground voltage to reduce unnecessary power consumption; in the write mode, the source of the first NMOS transistor (N11) close to the bit line (BL) maintains the original ground voltage, due to the configuration The small channel has a width-to-length ratio of the first NMOS transistor (N11), so that it is practically possible to avoid the problem that it is quite difficult to write the logic 1 in the SRAM with a single bit line; in the standby mode, the leakage can be effectively reduced. Current, while maintaining the original electrical characteristics in the hold mode. Moreover, the design of the standby start circuit (4) is effective to prompt the 單埠SRAM to quickly enter the standby mode, and thus effectively improve the standby performance of the 單埠SRAM.

BLB ₁ ^... BLB _m ‧‧‧complementary bit line

BLB‧‧‧complementary bit line

MB ₁ ^... MB _k ‧‧‧ memory block

WL ₁ ^... WL _n ‧‧‧ character line

BL ₁ ^... BL _m ‧‧‧ bit line

I ₁ , I ₂ , I ₃ ‧‧‧ leakage current

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧Standby start circuit

P11‧‧‧First PMOS transistor

P12‧‧‧Second PMOS transistor

N11‧‧‧First NMOS transistor

N12‧‧‧Second NMOS transistor

N13‧‧‧ Third NMOS transistor

A‧‧‧ storage node

B‧‧‧ Inverting storage node

V _DD ‧‧‧Power supply voltage

BL‧‧‧ bit line

WL‧‧‧ character line

S‧‧‧Standby mode control signal

/S‧‧‧Inverted standby mode control signal

VL1‧‧‧ first low voltage node

VL2‧‧‧ second low voltage node

N21‧‧‧4th NMOS transistor

N22‧‧‧ fifth NMOS transistor

N23‧‧‧ sixth NMOS transistor

N24‧‧‧ seventh NMOS transistor

N25‧‧‧ eighth NMOS transistor

N26‧‧‧Ninth NMOS transistor

RC‧‧‧ read control signal

RGND‧‧‧Accelerated reading voltage

INV‧‧‧ third inverter

D1‧‧‧First delay circuit

P31‧‧‧ Third PMOS transistor

P‧‧‧Precharge signal

N41‧‧‧ tenth NMOS transistor

P41‧‧‧4th PMOS transistor

D2‧‧‧second delay circuit

Figure 1a shows a conventional static random access memory; Figure 1b shows a schematic circuit diagram of a conventional 6T static random access memory cell; and Fig. 2 shows a conventional 6T static random access memory cell. The write operation timing chart; the third figure shows the circuit diagram of the conventional 5T static random access memory unit cell; the fourth figure shows the write operation timing chart of the conventional 5T static random access memory unit cell; 5 is a schematic circuit diagram showing a preferred embodiment of the present invention; FIG. 6 is a simplified circuit diagram showing a preferred embodiment of the present invention in FIG. 5 during writing; and FIG. 7 is a view showing the fifth drawing; FIG. 8 is a simplified circuit diagram showing a preferred embodiment of the present invention in the fifth embodiment of the present invention; and FIG. 9 is a preferred embodiment of the present invention shown in FIG. Simplified circuit diagram during standby.

According to the above main object, the present invention provides a 5T static random access memory, which mainly comprises a memory array, which is composed of a plurality of columns of memory cells and a plurality of rows of memory cells, each column. The memory cell and each row of memory cells comprise a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits (3) Each row of memory cells is provided with a precharge circuit (3); and a standby start circuit (4).

For convenience of explanation, the static random access memory shown in FIG. 5 has only one memory cell (1), one word line (WL), one bit line (BL), and one control circuit (2). A precharge circuit (3) and a standby start circuit (4) are described as embodiments. The memory cell (1) includes a first inverter (composed of a first PMOS transistor P11 and a first NMOS transistor N11) and a second inverter (by a second PMOS) a first NMOS transistor (N13), wherein the first NMOS transistor and the second NMOS transistor are in an inter-coupled connection, that is, the first The output of the inverter (ie node A) is connected to the input of the second inverter, and the output of the second inverter (ie node B) is connected to the input of the first inverter, and the first The output of the inverter (node A) is used to store the data of the SRAM cell, and the output of the second inverter (node B) is used to store the inverted data of the SRAM cell.

Referring to FIG. 5 again, the control circuit (2) is composed of a fourth NMOS transistor (N21), a fifth NMOS transistor (N22), a sixth NMOS transistor (N23), and a seventh NMOS device. a crystal (N24), an eighth NMOS transistor (N25), a ninth NMOS transistor (N26), a read control signal (RC), a third inverter (INV), and a first delay circuit ( D1), an accelerated read voltage (RGND), a standby mode control signal (S), and an inverted standby mode control signal (/S). a source, a gate and a drain of the fourth NMOS transistor (N21) are respectively connected to a ground voltage, the inverted standby mode control signal (/S) and a second low voltage node (VL2); a source, a gate and a drain of the NMOS transistor (N22) are respectively connected to the second low voltage node (VL2), the standby mode control signal (S) and a first low voltage node (VL1); The source of the six NMOS transistor (N23) is connected to the ground voltage, and the gate is connected to the drain and connected to the first low voltage node (VL1); the source of the seventh NMOS transistor (N24) The gate and the drain are respectively connected to the drain of the eighth NMOS transistor (N25), the read control signal (RC) and the first low voltage node (VL1); the eighth NMOS transistor (N25) The source, gate and drain are connected to the accelerated read a voltage (RGND), an output of the first delay circuit (D1) and a source of the seventh NMOS transistor (N24); the first delay circuit (D1) is connected to the third inverter (INV) The output is coupled to the gate of the eighth NMOS transistor (N25); the input of the third inverter (INV) is for receiving the read control signal (RC), and the output is coupled to the first delay circuit (D1) input; the source, gate and drain of the ninth NMOS transistor (N26) are respectively connected to a ground voltage, the inverted standby mode control signal (/S) and the first low voltage node ( VL1). It is worth noting here that the inverted standby mode control signal (/S) is obtained by the standby mode control signal (S) via an inverter.

The control circuit (2) is designed to control the voltage level of the first low voltage node (VL1) and the second low voltage node (VL2) according to different operation modes, and select the unit cell in the write mode. The source voltage of the driving transistor (ie, the first NMOS transistor N11) closer to the bit line (BL) (ie, the first low voltage node VL1) is set to a ground voltage, and another cell in the selected cell will be selected The source voltage of the driving transistor (ie, the second NMOS transistor N12) (ie, the second low voltage node VL2) is set to a ground voltage.

In the first phase of the read mode, the source voltage of the driving transistor (ie, the first NMOS transistor N11) closer to the bit line (BL) in the cell is selected (ie, the first low voltage node VL1) Setting the accelerated read voltage (RGND) lower than the ground voltage, the accelerated read voltage (RGND) being lower than the ground voltage can effectively increase the read speed, and in the second stage of the read mode And setting a source voltage of a driving transistor (ie, the first NMOS transistor N11) closer to the bit line (BL) in the selected unit cell to a ground voltage, so as to reduce unnecessary power consumption, wherein the read mode is The second phase is separated from the first phase by the equalization of the read control signal (RC) from a logic low level to a logic high level, and to the eighth NMOS The gate voltage of the transistor (N25) is sufficient to turn off the eighth NMOS transistor (N25), and the value thereof can be decreased by the delay time of the third inverter (INV) and the first delay circuit (D1) The delay time provided is adjusted.

In the standby mode, the source voltage of the driving transistor in all the memory cells is set to the predetermined voltage higher than the ground voltage to reduce the leakage current; and in the hold mode, the driving power in the memory cell is The source voltage of the crystal is set to the ground voltage to maintain the original retention characteristics. The detailed operating voltage levels are shown in Table 1.

The read control signal (RC) in Table 1 is the result of the AND operation of a Read Enable (RE) signal and a corresponding Word Line (WL) signal. It is worth noting here that the unselected word line and the unselected positioning element line are set to a floating state, and the read control signal (RC) is set to the acceleration during the non-read mode. The level of the read voltage (RGND) is read to prevent leakage current of the seventh NMOS transistor (N24).

Referring to FIG. 5, the precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P), and the source and gate of the third PMOS transistor (P31). Connected to the power supply voltage (V _DD ), the pre-charge signal (P) and the corresponding bit line (BL), respectively, to facilitate the pre-charging signal by logic low level during pre-charging ( P), pre-charging the corresponding bit line (BL) to the level of the power supply voltage (V _DD ).

Referring to FIG. 5 again, the standby starting circuit (4) is composed of a fourth PMOS transistor (P41), a twelfth NMOS transistor (N41), a second delay circuit (D2), and the reverse standby. The mode control signal (/S) is composed of. The source, the gate and the drain of the fourth PMOS transistor (P41) are respectively connected to a power supply voltage (V _DD ), the inverted standby mode control signal (/S) and the twelfth NMOS transistor ( a drain of N41); a source, a gate and a drain of the twelfth NMOS transistor (N41) are respectively connected to the output of the first low voltage node (VL1) and the second delay circuit (D2) a drain of the fourth PMOS transistor (P41); an input of the second delay circuit (D2) is coupled to the inverted standby mode control signal (/S), and an output of the delay circuit (D2) is coupled to the The gate of the twelfth NMOS transistor (N41).

The working principle of the preferred embodiment of the present invention in FIG. 5 is as follows:

(I) write mode

Before the start of the write operation, the standby control signal (S) is at a logic low level, and the inverted standby control signal (/S) is at a logic high level, such that the ninth NMOS transistor (N26) is turned "ON", and The first low voltage node (VL1) is brought to a ground voltage.

During the write operation period, the standby control signal (S) is at a logic low level, and the inverted standby control signal (/S) is at a logic high level, so that the ninth NMOS transistor (N26) is turned on (ON). And the first low voltage node (VL1) is still grounded, because the channel width to length ratio of the first NMOS transistor (N11) is designed to be a channel of the prior art driving transistor (N11) of FIG. 1b. The aspect ratio is also small, so it is effective to avoid the difficulty of writing logic 1. Figure 6 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during writing.

Next, how the write operation of the preferred embodiment of the present invention in FIG. 6 is completed depends on the four write states of the SRAM.

(1) Node A originally stores a logic 0, but now wants to write a logic 0:

Before the write operation occurs (the word line WL is a ground voltage), the first NMOS transistor (N11) is turned "ON". Since the first NMOS transistor (N11) is ON, the word line (WL) is turned from Low (ground voltage) to High (power supply voltage V _DD ) when the write operation starts. When the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (N13) (ie, the access transistor), the third NMOS transistor (N13) is turned from off (OFF) to on ( ON), at this time, since the bit line (BL) is the ground voltage, the node A is discharged, and the logic 0 write operation is completed until the end of the write cycle.

(2) Node A originally stores logic 0, but now wants to write logic 1:

Before the write operation occurs (the word line WL is a ground voltage), the first NMOS transistor (N11) is turned "ON". Since the first NMOS transistor (N11) is ON, when the write operation starts, the word line (WL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the node A It will rise following the voltage of the word line (WL).

When the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (N13), the third NMOS transistor (N13) is turned from OFF to ON, because The bit line (BL) is High (the power supply voltage V _DD ), and because the first NMOS transistor (N11) is still ON and the node B is still at a voltage level close to the power supply voltage (V _{DD )} The initial state of the voltage level, so the first PMOS transistor (P11) is still off (OFF), and the node A is rapidly charged toward a divided voltage level, the divided voltage level is equal to (R _N11 )/(R _N13 + R _N11 ) is multiplied by the power supply voltage (V _DD ), wherein the R _N13 represents an on-resistance equivalent of the third NMOS transistor (N13), and the R _N11 represents the first NMOS The on-resistance equivalent resistance of the crystal (N11) is small because the channel width-to-length ratio of the first NMOS transistor (N11) is designed to be smaller than that of the prior art drive transistor (N11) of FIG. 1b. Not only does it not hinder the read operation, but also enables the voltage division voltage level to be higher than the threshold voltage of the second NMOS transistor (N12), thereby enabling the second NMOS transistor (N1) 2) conducting, so that the node B is discharged to a lower voltage level, and the lower voltage level of the node B causes the conduction equivalent resistance (R _N11 ) of the first NMOS transistor (N11) to be higher. The resistance value, the higher resistance value of the first NMOS transistor (N11) will obtain a higher voltage level at the node A, and the higher voltage level of the node A will pass through the second inverter ( The second PMOS transistor P12 and the second NMOS transistor N12 are formed, so that the node B exhibits a lower voltage level, and the lower voltage level of the node B is again passed through the first inverter (by The first PMOS transistor P11 and the first NMOS transistor N11 are formed, so that the node A obtains a higher voltage level, and according to the cycle, the node A can be charged to the power supply voltage (V _DD ). The logic 1 write operation is completed.

(3) Node A originally stores logic 1, but now wants to write logic 1:

Before the write operation occurs (the word line WL is a ground voltage), the first PMOS transistor (P11) is turned "ON". When the word line (WL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (N13), The third NMOS transistor (N13) is turned from OFF to ON; at this time, since the bit line (BL) is High (the power supply voltage V _DD ), and because the first PMOS transistor (P11) is still ON, so the voltage of the node A will be maintained at the voltage level of the power supply voltage (V _DD ) until the end of the write cycle.

(4) Node A originally stores logic 1, but now wants to write logic 0:

Before the write operation occurs (the word line WL is a ground voltage), the first PMOS transistor (P11) is turned "ON". When the word line (WL) is turned from Low (ground voltage) to High (the power supply voltage V _DD ), and the voltage of the word line (WL) is greater than the threshold voltage of the third NMOS transistor (N13), The third NMOS transistor (N13) is turned from off (OFF) to on (ON). At this time, since the bit line (BL) is Low (ground voltage), the node A and the first low voltage are The node (VL1) is discharged to complete the write operation of logic 0 until the end of the write cycle.

The simplified circuit diagram of the preferred embodiment of the present invention shown in FIG. 6 shows the HSPICE transient analysis simulation result during the write operation, as shown in FIG. 7, which is simulated using the TSMC 90 nm CMOS process parameters. The simulation results show that the 5T static random access memory proposed by the present invention can increase the voltage level of the node A during the writing by configuring the first NMOS transistor (N11) with a smaller channel aspect ratio. It is quite difficult to avoid the existence of a single bit line and the static random access memory cell has difficulty in writing logic 1.

(II) Read mode (read mode)

Before the reading operation starts, the read control signal (RC) and the standby mode control signal (S) are both logic low levels, so that the ninth NMOS transistor (N26) is turned on (ON), and The first low voltage node (VL1) is at a ground voltage. On the other hand, since the read control signal (RC) is at a logic low level, the seventh NMOS transistor (N24) is turned off (OFF), and the eighth NMOS transistor (N25) is turned "ON".

The preferred embodiment of the present invention shown in FIG. 5 is controlled by two stages to improve the reading speed while avoiding unnecessary power consumption. In the first stage of the reading operation, the reading control The signal (RC) is at a logic high level, so that the seventh NMOS transistor (N24) is turned on. Since the eighth NMOS transistor (N25) is still turned on at this time, the first low voltage node (VL1) is at a ground voltage. To lower the accelerated read voltage (RGND), the accelerated read voltage (RGND), which is lower than the ground voltage, can effectively increase the read speed.

In the second stage of the read operation, although the read control signal (RC) is still at a logic high level, the seventh NMOS transistor (N24) is still turned on, but since the eighth NMOS transistor (at this time) N25) is turned off, so that the first low voltage node (VL1) is grounded via the turned-on ninth NMOS transistor (N26), thereby effectively reducing unnecessary power consumption. It is worth noting here that the second phase of the read operation is separated from the first phase by a time equal to the read control signal (RC) transitioning from a logic low level to a logic high level, and to the The gate voltage of the eight NMOS transistor (N25) is sufficient to turn off the eighth NMOS transistor (N25), and the value thereof can be decreased by the delay time of the third inverter (INV) and the first delay circuit. (D1) The delay time provided is adjusted. Furthermore, the ninth NMOS transistor (N26) is in an on state regardless of the first phase of the read operation or the second phase (since the gate of the ninth NMOS transistor (N26) is substantially the power supply voltage V _DD The standard). Figure 8 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during reading.

(III) Standby mode

First, how the standby start circuit (4) of Fig. 5 causes the 單埠SRAM to quickly enter the standby mode to effectively improve the standby performance of the SRAM: (1) the reverse standby mode control signal (/S) before entering the standby mode. Is logic High, the logic high inversion standby mode control signal (/S) causes the fourth PMOS transistor (P41) to be turned off (OFF), and causes the twelfth NMOS transistor (N41) to be turned on (ON) (2) After entering the standby mode, the inverted standby mode control signal (/S) is logic Low, and the inverted standby mode control signal (/S) of the logic Low causes the fourth PMOS transistor (P41) Turned on (ON), but during the initial period of the standby mode (the initial period is equal to the inverted standby mode control signal (/S) from logic high to logic Low, to the twelfth NMOS transistor (N41) The gate voltage is sufficient to turn off the twelfth NMOS transistor (N41), which can be adjusted by a delay time provided by the second delay circuit (D2), the twelfth NMOS transistor ( N41) is still turned on (ON), so the first low voltage node (VL1) can be quickly charged to reach the sixth NMOS transistor (N2) 3) The voltage level of the threshold voltage (V _TN23 ), that is, the 單_埠 SRAM can quickly enter the standby mode. It is worth noting here that after the initial period of the standby mode, the twelfth NMOS transistor (N41) is turned off and the supply current is stopped.

Referring to FIG. 5, in the standby mode, the standby mode control signal (S) is a logic high level, and the inverted standby mode control signal (/S) is a logic low level, and the logic low level is the reverse standby. The mode control signal (/S) may cause the fourth NMOS transistor (N21) in the control circuit (2) to be turned off (OFF), and the logic high level of the standby mode control signal (S) causes the fifth The NMOS transistor (N22) is turned on (ON), and the fifth NMOS transistor (N22) is used as an equalizer, so that the fifth NMOS transistor (N22) in an on state can be used. So that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to the sixth NMOS transistor (N23) The voltage level of the threshold voltage (V _TN23 ). Figure 9 is a simplified circuit diagram of the preferred embodiment of the invention of Figure 5 during standby.

Next, how to reduce leakage current in the standby mode of the present invention will be described. Referring to FIG. 9, FIG. 9 depicts a leakage current I ₁ generated when the embodiment of the present invention is in the standby mode. I ₂ , I ₃ , wherein it is assumed that the output of the first inverter (ie, node A) in the SRAM cell is a logic Low (it is worth noting here that the second low voltage node (VL2) due to the standby mode The voltage level is maintained at the voltage level of the threshold voltage (V _TN23 ) of the sixth NMOS transistor (N23), so the voltage level of the node A is the logic Low and is maintained at the voltage level of the V _TN23 ) And the output of the second inverter (ie, node B) is a logic high (power supply voltage V _DD ). Referring to the prior art of FIG. 1b and the embodiment of the present invention of FIG. 9, the comparison between the static random access memory of the present invention and the 6T SRAM of FIG. 1b in terms of leakage current is first described. The leakage current I _{1 of the} third NMOS transistor (N13) is maintained at the voltage level of the V _{TN 23 due to} the voltage level of the node A in the standby mode, and the word line (WL) is assumed to be in the standby mode. The ground voltage is set, and the bit line (BL) is set to the power supply voltage (V _DD ) in the standby mode, so the gate-source voltage (V _GS ) of the third NMOS transistor (N13) of the present invention is set. Negative value, in contrast to the standby mode, the gate-source voltage (V _GS ) of the prior art NMOS transistor (N3) of Fig. 1b is equal to 0, according to the Gate Induced Drain Leakage (GIDL) effect. Or, as shown in the results of Figures 3(A) and 3(B) of the US Pat. No. 6,865,119, issued March 8, 2005, it is known that for an NMOS transistor, the sub-critical current of the gate-source voltage is -0.1 volt is approximately the gate. The source voltage is 1% of the subcritical current at 0 volts, and thus is caused by the GIDL effect and flows through the present invention. The leakage current I _{1 of} the third NMOS transistor (N13) is much smaller than that of the prior art NMOS transistor (N3) of FIG. 1b; further, the threshold voltage of the third NMOS transistor (N13) of the present invention ( V _DS ) _deducts the voltage level of the V _{TN 23} for the power supply voltage (V _DD ), and the source voltage of the NMOS transistor (N3) of the conventional 1b to 6T static random access memory in the standby mode. (V _DS ) is equal to the power supply voltage (V _DD ), according to the Drain-Induced Barrier Lowering (DIBL) effect, the third NMOS transistor flowing through the present invention due to the DIBL effect The leakage current I _{1 of} (N13) is also smaller than that of the prior art NMOS transistor (N3) of FIG. 1b; as a result, the leakage current I1 flowing through the third NMOS transistor (N13) of the present invention is much smaller than that of the previous FIG. NMOS transistor (N3).

Next, regarding the leakage current I ₂ flowing through the first PMOS transistor (P11), the source of the first PMOS transistor (P11) is the power supply voltage (V _DD ) due to the standby mode, and the first The drain of the PMOS transistor (P11) is maintained at the voltage level of the V _TN23 , so the source drain voltage (V _SD ) of the first PMOS transistor (P11) of the present invention is the power supply voltage (V). _DD ) deducting the voltage level of the V _TN23 , and in the standby mode, the source drain voltage (V _SD ) of the prior art PMOS transistor (P1) of FIG. 1b is equal to the power supply voltage (V _DD ), according to The DIBL effect, therefore, the leakage current I ₂ flowing through the first PMOS transistor (P11) of the present invention will be smaller than that of the prior art PMOS transistor (P1) of Figure 1b.

Finally, regarding the leakage current I ₃ flowing through the second NMOS transistor (N12), since the voltage level of the second low voltage node (VL2) is maintained at the voltage level of the V _TN23 in the standby mode, the node A The voltage level is also maintained at the voltage level of the V _TN23 , and the voltage level of the node B is equal to the power supply voltage (V _DD ) and the base of the second NMOS transistor (N12) is the ground voltage, so The base-source voltage (V _BS ) of the second NMOS transistor (N12) is negative, and the 汲 source voltage (V _DS ) of the second NMOS transistor (N12) is the power supply voltage (V) _DD ) deducting the voltage level of the V _TN23 , in contrast to the standby mode, the base-source voltage (V _BS ) of the prior art NMOS transistor (N2) of FIG. 1b is equal to 0, and the NMOS transistor (N2) The source voltage (V _DS ) is equal to the power supply voltage (V _DD ). According to the body effect and the DIBL effect, the leakage current I ₃ flowing through the second NMOS transistor (N12) of the present invention is much smaller than the first 1b is a prior art NMOS transistor (N2). It can be seen from the above analysis that the 單埠 static random access memory proposed by the present invention has a lower leakage current than the prior art of Fig. 1b.

(IV) hold mode

In the hold mode, since the first low voltage node (VL1) and the second low voltage node (VL2) are both set to a ground voltage, the working principle is the same as that of the conventional 5T SRAM cell with a single bit line in FIG. This is not repeated here.

【Effects of invention】

The static random access memory proposed by the present invention has the following effects: (1) avoiding the problem of writing logic 1: the 5T static random access memory proposed by the present invention can be borrowed during a write operation. By configuring the first NMOS transistor (N11) with a small channel aspect ratio so as to avoid obstructing the read operation, it is quite difficult to avoid the existence of writing logic 1 in the SRAM with a single bit line. (2) Quick entry standby mode: Since the 5T static random access memory proposed by the present invention is provided with a standby start circuit (4) to prompt the SRAM to quickly enter the standby mode, and thereby seek Improve the standby performance of the SRAM; (3) High read speed and avoid unnecessary power consumption: The 5T static random access memory system proposed by the present invention adopts a two-stage read operation and borrows in the first stage of the read operation. Setting the first low voltage node (VL1) to the accelerated read voltage (RGND) lower than the ground voltage to effectively increase the read speed, and in the second stage of the read operation, the first The low voltage node (VL1) is set back to the ground voltage to reduce unnecessary power consumption; (4) low standby current: since the 5T static random access memory proposed by the present invention is in the standby mode, it can be turned on. The fifth NMOS transistor (N22) is such that the voltage level of the first low voltage node (VL1) is equal to the voltage level of the second low voltage node (VL2), and the voltage levels are equal to The threshold voltage of the sixth NMOS transistor (N23) is such that the static random access memory proposed by the present invention also has the effect of low standby current; (5) the number of low transistors: for 1024 columns For the 1024-line SRAM array, the traditional 1b Figure 6T is still A total of 1024×1024×6=6,291,456 transistors are required for the random access memory array, and the static random access memory proposed by the present invention only needs at least 1024×1024×5+1024×14+6=5,257,222 transistors. , which reduces the number of transistors by 16.4%.

While the invention has been particularly shown and described, the embodiments of the invention may Therefore, all changes in the relevant technical scope are included in the scope of the patent application of the present invention.

1‧‧‧SRAM cell

2‧‧‧Control circuit

3‧‧‧Precharge circuit

4‧‧‧Standby start circuit

P11‧‧‧First PMOS transistor

P12‧‧‧Second PMOS transistor

N11‧‧‧First NMOS transistor

N12‧‧‧Second NMOS transistor

N13‧‧‧ Third NMOS transistor

A‧‧‧ storage node

B‧‧‧ Inverting storage node

V _DD ‧‧‧Power supply voltage

BL‧‧‧ bit line

WL‧‧‧ character line

S‧‧‧Standby mode control signal

/S‧‧‧Inverted standby mode control signal

VL1‧‧‧ first low voltage node

VL2‧‧‧ second low voltage node

N21‧‧‧4th NMOS transistor

N22‧‧‧ fifth NMOS transistor

N23‧‧‧ sixth NMOS transistor

N24‧‧‧ seventh NMOS transistor

N25‧‧‧ eighth NMOS transistor

N26‧‧‧Ninth NMOS transistor

RC‧‧‧ read control signal

RGND‧‧‧Accelerated reading voltage

INV‧‧‧ third inverter

D1‧‧‧First delay circuit

P31‧‧‧ Third PMOS transistor

P‧‧‧Precharge signal

N41‧‧‧ tenth NMOS transistor

P41‧‧‧4th PMOS transistor

D2‧‧‧second delay circuit

Claims (7)

A 5T static random access memory comprising: a memory array consisting of a plurality of columns of memory cells and a plurality of rows of memory cells, each column of memory cells and each row of memory cells The cell comprises a plurality of memory cells (1); a plurality of control circuits (2), each column of memory cells is provided with a control circuit (2); a plurality of precharge circuits (3), each row of memory cells Providing a pre-charging circuit (3); and a standby starting circuit (4), the standby starting circuit (4) prompting the 5T static random access memory to quickly enter the standby mode to effectively improve the 5T static random access memory The standby performance of the body; wherein each memory cell (1) further comprises: a first inverter consisting of a first PMOS transistor (P11) and a first NMOS transistor (N11), The first inverter is connected between a power supply voltage (V _DD ) and a first low voltage node (VL1); and a second inverter is connected to a second PMOS transistor (P12) a second NMOS transistor (N12) connected to the power supply voltage (V _DD ) and Between a second low voltage node (VL2); a storage node (A) formed by the output of the first inverter; and an inverted storage node (B) by the second inverter Formed at the output end; a third NMOS transistor (N13) is connected between the storage node (A) and a corresponding bit line (BL), and the gate is connected to a corresponding word line ( WL); wherein the first inverter and the second inverter are connected in an alternating coupling manner, that is, an output end of the first inverter (ie, the storage node A) is connected to the second inversion The input end of the second inverter is connected to the input end of the first inverter; and each control circuit (2) further comprises: a first Four NMOS transistors (N21), a fifth NMOS transistor (N22), a sixth NMOS transistor (N23), a seventh NMOS transistor (N24), an eighth NMOS transistor (N25), a first Nine NMOS transistor (N26), a read control signal (RC), a third inverter (INV), a first delay circuit (D1), an accelerated read voltage (RGND), a standby mode control signal (S) and an inverted standby mode control No. (/S); wherein the source, the gate and the drain of the fourth NMOS transistor (N21) are respectively connected to a ground voltage, the reverse standby mode control signal (/S) and the second low voltage a node (VL2); a source, a gate and a drain of the fifth NMOS transistor (N22) are respectively connected to the second low voltage node (VL2), the standby mode control signal (S) and the first low a voltage node (VL1); a source of the sixth NMOS transistor (N23) is connected to a ground voltage, and a gate is connected to the drain and connected to the first low voltage node (VL1); the seventh NMOS a source, a gate and a drain of the transistor (N24) are respectively connected to the drain of the eighth NMOS transistor (N25), the read control signal (RC) and the first low voltage node (VL1); The source, the gate and the drain of the eighth NMOS transistor (N25) are respectively connected to the accelerated read voltage (RGND), the output of the first delay circuit (D1), and the seventh NMOS transistor (N24) a source of the first delay circuit (D1) connected between the output of the third inverter (INV) and the gate of the eighth NMOS transistor (N25); the third inverter ( INV) input for receiving Reading a control signal (RC), and the output is connected to an input of the first delay circuit (D1); the source, the gate and the drain of the ninth NMOS transistor (N26) are respectively connected to a ground voltage, An inverted standby mode control signal (/S) and the first low voltage node (VL1); wherein the read control signal (RC) during the non-read mode is set to the accelerated read voltage (RGND) Leveling to prevent leakage current of the seventh NMOS transistor (N24) during the non-read mode; further, the standby starting circuit (4) is designed to enter an initial period of one of the standby modes, The parasitic capacitance at a low voltage node (VL1) is rapidly charged to the voltage level of the threshold voltage (V _TN23 ) of the sixth NMOS transistor (N23). The 5T static random access memory according to claim 1, wherein the inverted standby mode control signal (/S) is obtained by the standby mode control signal (S) via an inverter. The 5T static random access memory as described in claim 2, the read control signal (RC) is the result of an AND gate operation of a Read Enable (RE) signal and the corresponding word line (WL) signal, that is, only the read enable (RE) When the signal and the corresponding word line (WL) signal are both at a logic high level, the read control signal (RC) side is at a logic high level. The 5T static random access memory according to claim 3, wherein each precharge circuit (3) is composed of a third PMOS transistor (P31) and a precharge signal (P); The source, the gate and the drain of the third PMOS transistor (P31) are respectively connected to a power supply voltage (V _DD ), the precharge signal (P) and the corresponding bit line (BL), In order to facilitate the precharge period, the pre-charge signal (P) is logically low-level to pre-charge the corresponding bit line (BL) to the level of the power supply voltage (V _DD ). The 5T static random access memory according to claim 4, wherein the standby starting circuit (4) is a fourth PMOS transistor (P41), a tenth NMOS transistor (N41), and a a second delay circuit (D2) and the inverted standby mode control signal (/S); wherein the source, the gate and the drain of the fourth PMOS transistor (P41) are respectively connected to a power supply voltage ( V _DD ), the inverted standby mode control signal (/S) and the drain of the tenth NMOS transistor (N41); the source, the gate and the drain of the tenth NMOS transistor (N41) are respectively connected Up to the first low voltage node (VL1), the output of the second delay circuit (D2) and the drain of the fourth PMOS transistor (P41); the input of the second delay circuit (D2) is connected to the inversion The standby mode control signal (/S), and the output of the delay circuit (D1) is connected to the gate of the tenth NMOS transistor (N41). The 5T static random access memory according to claim 5, wherein the initial period of the standby start circuit (4) entering the standby mode is equal to the inverted standby mode control signal (/S) being logic high The quasi-transition is a logic low level, until the gate voltage of the tenth NMOS transistor (N41) is sufficient to turn off the tenth NMOS transistor (N41), which can be performed by the second delay circuit (D2) Provide one of the delay times to adjust. The 5T static random access memory according to claim 6, wherein the read operation system can be subdivided into two stages, and the first stage of the read operation is performed by the first low power The voltage node (VL1) is set to be lower than the ground voltage by the accelerated read voltage (RGND) to effectively increase the read speed, and in the second phase of the read operation by the first low voltage node (VL1) Setting back to the ground voltage to reduce unnecessary power consumption, the second phase of the read operation is separated from the first phase by the read control signal (RC) from a logic low level to a logic high level Calculating, until the gate voltage of the eighth NMOS transistor (N25) is sufficient to turn off the eighth NMOS transistor (N25), which can be delayed by the third inverter (INV) The other delay time provided by the first delay circuit (D1) is adjusted.