TWI565190B - Battery protection circuit package - Google Patents

Description

Battery protection circuit package Related patent applications

The present application claims the benefit of the Korean Patent Application No. 10-2014-0112405 filed on Jan. 27, 2014, to the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. .

Field of invention

The present invention relates to a battery protection circuit package and, more particularly, to a battery protection circuit package capable of ensuring the stability of a battery.

Background of the invention

Batteries are commonly used in portable devices such as mobile phones and personal digital assistants (PDAs). Like most batteries used on such portable devices, a lithium-ion battery has the risk of explosion and performance degradation when overcharge, overdischarge, and/or overcurrent occurs. Accordingly, a device for detecting and overcharging, overdischarging, and/or overcurrent of a battery is continuously required.

<Prior technology>

1. KR 10-2014-0032596 (March 17, 2014)

Summary of invention

The present invention provides a battery protection circuit package capable of ensuring the stability of a battery. However, the scope of the invention is not limited to this.

According to a feature of the invention, a battery protection circuit package capable of being electrically connected to a battery cell is provided, the package comprising a substrate having a plurality of external connections and a plurality of internal connections, and a protective integrated wafer (IC), one or more field effect transistors (FETs), and one or more passive devices on the substrate, wherein the protection IC includes an electrical signal via the external connection terminals One of the inputs can be forced to block the independent IC structure of the discharge or charge of the battery cell by turning off the FETs.

The FETs may include a pair of FETs having a common drain and being constructed as a first FET and a second FET, and the protection IC may include an end for applying a charge and discharge voltage and detecting a battery voltage. (VDD), a reference terminal (VSS) for providing a reference voltage of an internal operating voltage, a detecting terminal (V-) for detecting a charge/discharge and an overcurrent state, and one for overdischarging Turning off the discharge signal output terminal (DOUT) of the first FET, a charge completion signal output (COUT) for turning off the second FET in an overcharge state, and constructing to receive the electrical signal The forced blocking end (CP) that blocks the discharge or charging of the battery cell by turning off the FETs.

The electrical signal can include a high level and a low level A quasi electrical signal, and the independent IC structure can include a NOT gate.

The protection IC can be stacked on the FETs.

The protection IC may not be stacked on the FETs but may be disposed adjacent to the FETs and separated from them.

The substrate may include a first internal connection terminal and a second internal connection terminal having the electrode ends independently disposed at both side edges and electrically connectable to the battery cell, and disposed at the first and second ends Between the internal connection terminal pins, the external connection terminal pins for constructing the external connection terminals, and a mounting pin for mounting the protection IC, the FETs, and at least a part of the passive devices Lead frame. In this case, at least one selected from the group consisting of the protection IC and the FETs is not inserted and fixed to the lead frame in the form of a semiconductor package, but may be unsealed. The form of the sealed wafer die is mounted and secured to at least a portion of the surface of the leadframe using surface bonding techniques. In addition, at this time, the battery protection circuit package may further include an electrical connection component for electrically interconnecting the two selected from the protection IC, the FETs, and the groups of the pins. This builds a battery protection circuit that does not use a printed circuit board.

The protection IC, the FETs, and the passive devices can be buried in a secondary package and then disposed on the substrate.

The substrate can include a printed circuit board (PCB).

10‧‧‧Battery protection circuit

50‧‧‧ lead frame

60‧‧‧Substrate

60-1,60-2‧‧‧Under the exposed end

70‧‧‧Terminal lead frame

70-1,70-6‧‧‧Internal connection pin

70-2 to 70-5‧‧‧ External connection pin

110‧‧‧ Field Effect Crystal

120‧‧‧Protective integrated circuit

122‧‧‧NOT gate

124‧‧‧Oscillator

126‧‧‧Counter Logic

140‧‧‧Electrical connection elements

250‧‧‧Sealant

300‧‧‧Battery protection circuit package

302‧‧‧ device package

304‧‧‧Battery protection circuit package

400‧‧‧ battery case

410‧‧‧Negative end

420‧‧‧shims

430‧‧‧cap cover

500‧‧‧ cover

550‧‧‧through holes

600‧‧‧Battery pack

B+‧‧‧First internal connection

B-‧‧‧Second internal connection

P+‧‧‧first external connection

CF‧‧‧Second external connection

P-‧‧‧ third external connection

R1, R2, R3‧‧‧ resistors

V1‧‧‧ varistor

C1, C2‧‧‧ capacitor

N1‧‧‧ first node

N2‧‧‧ second node

VSS‧‧‧ reference

V-‧‧‧Detector

DOUT‧‧‧Delete the signal output

COUT‧‧‧End of the signal output

CP‧‧‧forced blocking end

CNT‧‧‧fourth external connection

A1‧‧‧First internal connection area

A2‧‧‧External connection area

A3‧‧‧ device area

A4‧‧‧ wafer area

A5‧‧‧Second internal connection area

L1 to L6‧‧‧ Passive device pins

FET1, FET2‧‧‧ field effect transistor

G1, G2‧‧‧ gate extreme

S1, S2‧‧‧ source extreme

The above and other features and advantages of the present invention will become more apparent from the detailed description of the exemplary embodiments BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a battery protection circuit of a battery protection circuit package according to some embodiments of the present invention; and FIG. 2 is a protection product shown in a battery protection circuit package of some embodiments of the present invention. FIG. 3 is a schematic diagram showing the structure of a lead frame of a battery protection circuit package according to an embodiment of the present invention; FIG. 4 is a battery protection showing an embodiment of the present invention. FIG. 5 is a schematic diagram showing the structure of a protection IC and FETs in a battery protection circuit package in a modified embodiment of the present invention; FIG. 6 is a perspective view showing a battery protection circuit package of an embodiment of the present invention; FIG. 7 is an exploded perspective view of a battery pack including a battery protection circuit package according to an embodiment of the present invention; and FIG. 8 is a view of the present invention. FIG. 9 is an exploded perspective view of a battery protection circuit package according to another embodiment of the present invention; FIG. 10 is a view showing a battery pack of the battery protection circuit package of the embodiment; FIG. An exploded perspective view of a structure of a protection IC, FETs, and a passive device in a battery protection circuit package according to another embodiment of the present invention; and FIGS. 11 and 12 are diagrams of a battery protection circuit package according to another embodiment of the present invention. Stereo picture.

Detailed description of the preferred embodiment

The invention will now be described in more detail in conjunction with the drawings, and embodiments of the invention are shown in the drawings.

The invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Instead, the embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In these figures, the thickness or size of the layers is exaggerated for clarity.

It will be understood that when an element, such as a layer, an area, or a substrate, is referred to as "on another element," "connected to another element," or "coupled to another element," It may be directly on the other element, directly connected to the other element or directly coupled to the other element or intervening element. In contrast, when an element is referred to as “directly on another element or layer”, “directly connected to another element or layer” or “directly coupled to another element or layer,” presence. The same reference numerals indicate the same elements from beginning to end. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

It will be understood that the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or Layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section may be referred to as a second element, component, region, layer or section without departing from the teachings of the example embodiments.

Spatially relative terms, such as "above", "above", "below", "below", "below", etc., may be used herein to make the description as shown in the drawings. The description of the relationship of one element or feature to another element or feature is easy. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the drawings. For example, elements that are described as "under other elements or features" or "under other elements or features" or "an" Therefore, the example vocabulary "above.." can encompass the orientation above and below. The device can be additionally positioned (rotated 90 degrees or at other orientations) and the spatial relative description used herein is interpreted accordingly.

The specific terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting. The singular forms "a", "the", and "the" It will be further understood that the terms "comprises" and/or "comprises", when used in the specification, are used to describe the presence of the features, things, steps, operations, components, and / or components, but not Exclusions or additions of one or more other features, things, steps, operations, components, components, and/or groups thereof are excluded.

Example embodiment A fit is a cross-sectional view of a schematic illustration of an example embodiment (and intermediate structure) as described herein. If yes, because of For example, differences in the shapes of the illustrations caused by manufacturing techniques and/or errors are contemplated. Thus, the example embodiments should not be construed as being limited to the particular shapes of the regions depicted herein, but may include variations in shape, for example, by manufacture.

In an embodiment of the invention, the lead frame is an element in which the pin end is patterned on a metal frame, and is structurally or thickly disposed with a metal wire layer disposed therein. A printed circuit board (PCB) on an insulated core is different.

1 is a circuit diagram of a battery protection circuit 10 of a battery protection circuit package according to some embodiments of the present invention, and FIG. 2 is a protective integrated circuit shown in a battery protection circuit package of some embodiments of the present invention. Schematic diagram of the structure of (IC) 120.

Referring to Figures 1 and 2, in a battery protection circuit package of some embodiments of the present invention, first and second internal terminals B+ and B- to be connected to a battery cell, and to be connected to A charger is provided for charging and first to third external terminals P+, CF, and P- to be connected to an electronic device (for example, a portable device) operated by battery power for discharging A portion of the battery protection circuit 10. Here, among the first to third external connection terminals P+, CF, and P-, the first and third external connection terminals P+ and P- are used to supply power and the other second external connection terminal CF It is used to detect the type of battery and perform charging according to the type of battery. Further, the second external connection terminal CF can be provided as a thermistor for detecting the battery temperature when charging, and can be used as an end having another function.

Additionally, the protection IC 120, one or more field effect transistors (FETs) 110, and one or more passive devices form another portion of the battery protection circuit 10. The passive devices may include, for example, resistors R1, R2, and R3, varistor V1, and capacitors C1 and C2. The FETs 110 can include, for example, a pair of FETs having a common drain and configured as a first FET FET1 and a second FET FET2.

The protection IC 120 has a first internal connection terminal B+ connected to the (+) pole of the battery via a resistor R1, a charging or discharging voltage applied through a first node n1, and a battery voltage detected. a reference terminal (eg, VSS) for supplying a reference voltage of the internal operating voltage of the protection IC 120, a detection terminal (eg, V-) for detecting a charge/discharge and an overcurrent state, and a The overdischarged state turns off the discharged electrical signal output (eg, DOUT) of the first FET FET1, and a charge-down signal output (eg, COUT) for turning off the second FET FET2 in an overcharged state.

Here, the protection IC 120 includes a reference voltage setter, a comparator for comparing a reference voltage with a charge/discharge voltage, an overcurrent detector, and a charge/discharge detector. Here, the reference voltage for determining the state of charge and discharge can be changed according to the specifications required by the user, and the charge and discharge states are based on detecting the voltage difference between the ends of the protection IC 120. These reference voltages are determined.

The protection IC 120 is constructed in such a manner that the terminal DOUT is changed to the LOW state in the overdischarged state, and the first FET FET1 can be turned off, and the terminal COUT is changed to the LOW state in the overcharged state. The second FET FET 2 can be turned off and the second FET FET 2 is turned off when charging in an overcurrent state and turned off when discharged.

According to this architecture, the function for preventing discharge or charging of the battery cells depends on the voltage of the battery cells, for example, overcharge or overdischarge, to control discharge and charge.

In addition to this architecture, the present invention uses the protection IC 120 that further includes a forced blocking terminal CP. The forced blocking terminal CP can implement a forced discharging or charging blocking function for forcing a blocking discharge or charging by turning off the FETs 110 when a specific low/high level electrical signal is input. A fourth external connection CNT connected to the forced blocking terminal CP can be additionally used to input the specific electrical signal to the forced blocking terminal CP of the protection IC 120.

The protection IC 120 includes a separate IC structure that can forcibly block discharge or charging of battery cells by turning off the FETs 110 when the particular electrical signal is input. The independent IC structure can be understood as a new IC called a forced blocking IC and can include, for example, a NOT gate 122. For example, the specific electrical signal input to the low/high level of the forced blocking terminal CP can pass through the NOT gate 122, an oscillator 124, and a counter logic 126 and can be forcibly turned off through the terminal DOUT or COUT. The FETs 110 thereby implement a forced blocking function for blocking discharge or charging of the battery cells.

At the same time, the resistor R1 and the capacitor C1 are stabilized in the change in the power supply of the protection IC 120. The resistor R1 is connected to the first node n1 as a power supply (V1) supply node of the battery, and the end of the protection IC 120 Between VDD, the capacitor C1 is connected between the terminal VDD and the terminal VSS of the protection IC 120. Here, the first node n1 is connected to the first internal connection terminal B+ and the first external connection terminal P+. If the resistor R1 has a high resistance value, when a voltage is detected, the detected voltage is increased due to the current flowing into the protection IC 120. If so, the resistance value of the resistor R1 is set to a suitable value equal to or less than 1 K?. Further, for stable operation, the capacitor C1 has a suitable value equal to or greater than 0.01 μF.

The resistors R1 and R2 function as a current limiter if a charger provides a high voltage that exceeds the maximum rating of the protection IC 120 or if the charger is mis-connected. The resistor R2 is connected between the terminal V- of the protection IC 120 and a second node n2 connected to the source S2 of the second FET FET2. Since the resistors R1 and R2 are closely related to power consumption, the sum of the resistance values of the resistors R1 and R2 is set to be greater than 1 kΩ. Further, if the resistance value of the resistor R2 is excessively large, since the recovery does not occur after the overcharge blocking, the resistance value of the resistor R2 is set to a value equal to or smaller than 10 K?.

The capacitor C2 is connected between the second node n2 (or the third external connection terminal P-) and the source S1 of the first FET FET1 (or the terminal VSS or the second internal connection terminal B-). The capacitor C2 does not have a strong influence on the product characteristics of the battery protection circuit 10, but is added at the request of the user or for stability. This capacitor C2 is used to achieve system stability by improving the tolerance of voltage variations or external noise.

The resistor R3 and the varistor V1 are devices for electrostatic discharge (ESD) and surge protection, and are connected in parallel to each other at the second external connection terminal CF and the second node n2 (or the first Between the three external terminals P-). The varistor V1 is a device for reducing the resistance of an overvoltage when it occurs, and can minimize, for example, circuit damage due to overvoltage.

The present invention encloses a substrate including the external connection terminals P+, P-, CF, and CNT and the internal connection terminals B+ and B-, and a protection IC 120, FETs 110, and Passive device to implement a battery protection circuit package.

The above battery protection circuit 10 of some embodiments of the present invention is merely an example, and the number and position of the FETs 110, the protection IC 120, and the passive devices are appropriately changed depending on the function of the battery protection circuit 10. of.

3 is a schematic view showing the structure of a lead frame 50 of a battery protection circuit package according to an embodiment of the present invention.

Referring to FIG. 3, the substrate of the battery protection circuit package of one embodiment of the present invention may include the lead frame 50. The substrate may include only the lead frame 50.

The lead frame 50 may have, for example, a first inner connecting end area A1, an outer connecting end area A2, a device area A3, a wafer area A4, and a second inner connecting end area A5.

The first and second internal connection end regions A1 and A5 are disposed on both side edges of the package module, and are respectively disposed on the upper side of the package module The function is a first internal connecting pin B+ connected to a first internal connecting end of the battery case accommodating the bare cell, and a second internal connecting end pin B- acting as a second internal connecting end. The external connection end region A2 is provided with first to fourth external connection terminal pins P+, CF, P-, and CNT acting as a plurality of external connection terminals and separated from each other. The order of the first to fourth external connection terminals P+, CF, P-, and CNT can be variously changed.

The device area A3 is a region for the passive devices R1, R2, R3, C1, C2, and V1 of the battery protection circuit 10 and may be provided thereon as being provided as a plurality of mutually separated conductive lines. To the sixth passive device pins L1, L2, L3, L4, L5, and L6. The wafer area A4 is an area for the protection IC 120 and the FETs 110 of the battery protection circuit 10, and a plurality of pins which are separated from each other can be disposed thereon as needed. The pin of the device area A3 and the chip area A4 can be understood as a mounting pin for mounting the protection IC 120, the FETs 110, and at least a portion of the passive devices.

The number and position of the first internal connection end area A1, the external connection end area A2, the device area A3, the wafer area A4, and the second internal connection end area A5 are depicted for illustrative purposes only. And based on the function of the battery protection circuit 10, it can be appropriately changed.

4 is a schematic diagram showing the structure of a protection IC 120 and FETs 110 in a battery protection circuit package in accordance with an embodiment of the present invention. The lead frame 50 shown in Fig. 4 is a variation of the device area A3 and the wafer area A4 shown in Fig. 3.

Referring to FIG. 4, the protection IC 120 can be stacked on the On the FETs 110. For example, the protection IC 120 can be stacked on the upper surface of a dual FET wafer 110.

The dual FET wafer 110 includes two FETs, that is, first and second FETs FET1 and FET2 having a common drain structure, and the first gate terminal G1 and the first source terminal S1 of the first FET FET1 and the first The second gate terminal G2 and the second source terminal S2 of the two FET FETs 2 are disposed as external terminals on the upper surface of the dual FET wafer 110. In addition, a common 汲 extreme can be disposed on the lower surface of the dual FET wafer 110.

If the protection IC 120 is stacked on the upper surface of the dual FET wafer 110, the protection IC 120 is stacked on an area other than the region where the external ends are disposed on the dual FET wafer 110 (for example, the center On the area). In this case, an insulating layer for insulation may be disposed between the protection IC 120 and the dual FET wafer 110, and the protection IC 120 and the dual FET wafer 110 may be bonded to each other by an insulating adhesive. .

After the protection IC 120 is stacked on the upper surface of the dual FET wafer 110, the end DOUT of the protection IC 120 is electrically connected to the first gate terminal G1 through a wire, and the end COUT of the protection IC 120 is a transmission wire Electrically connected to the second gate terminal G2.

By using the protection IC 120 and the dual FET wafer 110 having the above-described stacked structure, one of the mounting regions on the substrate can be reduced and thus a small or high-capacity battery can be realized.

The FETs 110 are not inserted into and fixed to the lead frame 50 in a semiconductor package, but can be mounted and fixed to the lead die by a surface bonding technique in a pattern of the wafer die not sealed by the sealant. wire At least a portion of the surface of the frame 50.

The battery protection circuit 10 further includes an electrical circuit for electrically interconnecting any one selected from the group comprising the protection IC 120, the FETs 110, and the pins, without using a PCB. The connecting element 140 can be constructed. The electrical connection component 140 can include, for example, a bonding wire or a bonding ribbon.

Since the battery protection circuit 10 is constructed on the lead frame 50 by providing an electrical connection member 140 such as a bonding wire or a metal strip, a process for designing and manufacturing the lead frame 50 of the battery protection circuit 10 Can be simplified. According to a variant embodiment of the invention, if the electrical connection element is not used in the battery protection circuit 10, the structure of the pins of the lead frame 50 can be very complicated and therefore the lead frame 50 will not be properly and Set efficiently.

FIG. 5 is a schematic diagram showing the structure of the protection IC 120 and the FETs 110 in the battery protection circuit package of the modified embodiment of the present invention.

The structure of FIG. 5 is the same as that of FIG. 4 except that the protection IC 120 is not stacked on the FETs 110 but is disposed adjacent to the FETs 110, and thus is repeatedly described therebetween. This is not provided.

According to some embodiments of the present invention, the substrate includes only the lead frame 50, and the protection IC 120 and/or the FETs 110 are not inserted and fixed into the lead frame 50 in a manner that the semiconductor package is taken. But will use the surface adhesion technique to be in the form of a wafer die that is not sealed by a sealant. Mounted and secured to at least a portion of the surface of the leadframe 50. Here, the wafer die refers to an independent process that is not sealed by a sealant but is performed by performing a cutting process on a wafer having an array formed of a plurality of structures (for example, protection ICs and FETs). structure. That is, since the protection IC 120 and/or the FETs 110 are mounted on the lead frame 50 in an unsealed state and then sealed with the sealant 250 (see FIG. 6), only one sealing process is necessary to achieve The battery protects the circuit package. Conversely, if the passive devices, the protection IC 120, and/or the FETs 110 are inserted and fixed or mounted into a PCB, each component will initially require a molding process and then be fixed or mounted. Another molding process is additionally required after the PCB, thereby causing a complicated process and high manufacturing cost.

FIG. 6 shows a perspective view of a battery protection circuit package 300 in accordance with an embodiment of the present invention. Specifically, (a) of FIG. 6 shows a first surface of the battery protection circuit package 300 of the embodiment of the present invention, and (b) of FIG. 6 shows a second surface of the battery protection circuit package 300. The second surface of the battery protection circuit package 300 exposes the external connection terminals P+, CF, CNT, and P-.

The battery protection circuit package 300 shown in FIG. 6 may be mounted on the lead frame 50 of FIG. 3 by the protection IC 120, the FETs 110, and the passive devices, and then sealed with a sealant 250. They are implemented. A portion of at least one of the first and second inner connecting end pins B+ and B- exposed without being sealed by the sealant 250 can be bent into a gull.

Although not shown in Figure 6, the passive devices can be set 俾 interconnecting at least some of the legs of the leadframe 50 that are separated from one another. Moreover, the battery protection circuit 10 can be used without using an electrical connection element for electrical interconnection from either the protection IC 120, the FETs 110, or any combination of the pins. It is constructed using a PCB.

7 is an exploded perspective view of a battery pack 600 including a battery protection circuit package 300 of an embodiment of the present invention, and FIG. 8 is a perspective view of a battery pack 600 including a battery protection circuit package 300 of an embodiment of the present invention. .

Referring to FIGS. 7 and 8, the battery protection circuit package 300 is inserted between the upper surface of the battery cell housed in a battery case 400 and the cover 500, thereby constituting the battery pack 600. The cover 500 is formed of a plastic material and has a through hole 550 exposing the external connection ends P+, CF, CNT, and P-. The battery pack 600 can be understood as a battery that is commonly used in mobile phones or portable devices.

The battery cell includes an electrode assembly and a cap assembly. The electrode assembly may include a positive electrode plate formed by coating a positive electrode active material on a positive electrode current collector, a negative electrode plate formed by coating a negative electrode active material on a negative electrode current collector, and a negative electrode plate An separator between the positive electrode plate and the negative electrode plate to prevent short circuit therebetween and to allow lithium ions to move. A positive tap bonded to the positive plate and a negative tap bonded to the negative plate project from the electrode assembly.

The cap assembly includes a negative end 410, a spacer 420, and a cap cover 430. The cap cover 430 can function as a positive terminal. The negative end 410 can also be referred to as a negative cell or an electrode cell. The spacer 420 may be formed of an insulating material such that the negative terminal 410 and the cap plate 430 are isolated from each other. Accordingly, the electrode end of the battery cell may include the negative terminal 410 of the cap plate 430. A portion of the lead frame 50 of the battery protection circuit package 300 of the embodiment of the present invention can be directly adhered to the electrode terminals 410 and 430 of the battery cell. The lead frame 50 may be formed using nickel (Ni) or a copper (Cu) plate plated with Ni, and the first and second internal connection terminals B+ and B- of the lead frame 50 may be used, for example, Laser welding, resistance welding, or conductive epoxy is adhered to the electrode ends 410 and 430 of the battery cell.

The electrode end of the battery cell includes a plate 430 having a first polarity (e.g., positive polarity) and an electrode cell 410 having a second polarity (e.g., a negative polarity) and disposed at the center of the plate 430, and The first internal connection terminal B+ can be directly adhered and electrically connected to the board 430 having a first polarity (eg, positive polarity) and the second internal connection terminal B- can be directly adhered and electrically connected to The electrode cell 410 has a second polarity (eg, a negative polarity). In this case, the length of the battery protection circuit package 300 may correspond to one electrode from the one end having the first polarity (for example, positive polarity) 430 to the electrode having the second polarity (for example, the negative polarity). The length of 410 is L/2. According to this embodiment, since the battery protection circuit package 300 is mounted using only a one-sided area from the electrode cell 410 having the second polarity (for example, a negative polarity), a small or high-capacity battery can be realized. . For example, by providing another cell or wafer having another function in the other side region from the electrode cell 410, the battery capacity can be increased or the product having such a battery can be reduced in size.

In the above battery protection circuit package of some embodiments of the present invention, compared with the case where the protection circuit device is mounted on a PCB and then the pin is adhered to the PCB, since a protection circuit device can be The pins that are mounted and connected to a battery cell can be set using only one lead frame, the manufacturing cost can be lowered and the total height can be significantly reduced. That is, since the PCB typically has a thickness of about 2 mm and the lead frame has a thickness of about 0.8 mm, the battery size can be reduced or the battery capacity can be increased by a value corresponding to the difference in thickness therebetween.

Furthermore, according to the above embodiment of the present invention, a small or high capacity battery can be realized if a battery protection circuit package is mounted using only a single side region from the electrode cells of a battery. However, the battery protection circuit package of the embodiment of the present invention is not limited to this and can be constructed to use the entire area of the upper surface of the electrode cell of the battery.

According to the technical idea of the present invention, when an electrical signal is input through a separate terminal, the substrate of the battery protection circuit package capable of forcibly blocking discharge or charging of a battery cell by turning off the FETs is not limited to only including A substrate for a lead frame. For example, a substrate for mounting a protection IC, one or more FETs, and one or more passive devices can include a PCB. A variety of other configurations are also permitted herein, and a description of other exemplary embodiments thereof is now provided.

FIG. 9 is an exploded perspective view of a battery protection circuit package 304 according to another embodiment of the present invention, and FIG. 10 is a protection IC, FETs, and a battery protection circuit package 304 according to another embodiment of the present invention. Passive An exploded perspective view of the structure of the device, and Figs. 11 and 12 are perspective views of a battery protection circuit package 304 according to another embodiment of the present invention.

Referring to FIGS. 9 through 12, a battery protection circuit package 304 of another embodiment of the present invention includes a terminal leadframe 70 and a device package 302.

The terminal lead frame 70 may include a first internal connection terminal pin 70-1 and a second internal connection terminal pin 70-6 respectively disposed at both side edges and electrically connected to the electrode end of a battery cell. An external connection end pin 70-2, 70-3, 70-4, and 70-5 are disposed between the first and second inner connecting end pins 70-1 and 70-6 and forming a plurality of external connecting ends. . The external connections may include 4 or more external connections. For example, the external connection terminals 70-2, 70-3, 70-4, and 70-5 may correspond to the external connection terminals P+, CF, CNT, and P- shown in FIG. The terminal lead frame 70 may be formed of Ni, Cu, Cu plated with Ni, or other metal. Moreover, the surface of the external connection terminal pins 70-2, 70-3, 70-4, and 70-5 of the terminal lead frame 70 facing the outside of the battery (for example, the surface shown in FIG. 8) is It can be plated completely or partially. A plating material may be at least one selected from the group consisting of gold (Au), silver (Ag), nickel (Ni), tin (Sn), and chromium (Cr).

The device package 302 includes a substrate, a battery protection circuit device mounted on the substrate, and a sealant 250 for sealing the battery protection circuit device. The battery protection circuit arrangement includes the FETs 110, the protection IC 120, and the passive devices R1, R2, R3, C1, C2, and V1. The encapsulant 250 can include, for example, an epoxy resin molding compound (EMC). The device package 302 is mounted on the terminal lead frame 70 and can be electrically Gas is connected to the terminal leadframe 70. For example, the device package 302 can be mounted on the terminal leadframe 70 using surface mount technology. One or more conductive lower exposed ends may be disposed on a lower surface of the device package 302. Still alternatively, one or more of the exposed ends 60-1 and 60-2 may be disposed on the upper surface of the device package 302. Encapsulant 250 for sealing the battery protection circuit device can expose the lower exposed ends. On the other hand, the lower exposed end provided on the lower surface of the device package 302 can be bonded and electrically connected to at least a portion of the terminal lead frame 70, thereby constituting the battery protection circuit 10 shown in FIG. At least part of it.

Referring to FIG. 10, a portion of the structure of the device package 302 is depicted. The device package 302 includes a substrate 60, and a protection IC 120, FETs 110, and passive devices R1, R2, C1, and C2 disposed on the substrate 60. Furthermore, electrical connection elements 140 for electrical interconnection from either the protection IC 120, the FETs 110, and the group of pins can be further utilized, thereby implementing the battery shown in FIG. Protection circuit 10. The detailed description of the protection IC 120 is the same as that described above with respect to FIGS. 1 and 2.

The device package 302 forms part of the battery protection circuit package 304 and thus can be understood as a sub-package. The substrate of the device package 302 for providing the protection IC 120, the FETs 110, and the passive devices R1, R2, C1, and C2 may include a lead frame, a PCB, a ceramic substrate, or a glass substrate.

In order to distinguish the terminal lead frame 70 and the substrate of the device package 302 in the battery protection circuit package 304 of another embodiment of the present invention, The terminal leadframe 70 can be referred to as a first substrate and the substrate of the device package 302 can be referred to as a second substrate.

According to the above embodiment of the present invention, a battery protection circuit package capable of ensuring the stability of a battery can be provided. However, the scope of the present invention is not limited to the above effects.

Although the present invention has been particularly shown and described with respect to the exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail are defined without departing from the scope of the appended claims. Under the spirit and scope of the present invention can be made.

10‧‧‧Battery protection circuit

100a, 100b‧‧‧ circuit part

110‧‧‧ Field Effect Crystal

120‧‧‧Protective integrated circuit

N1‧‧‧ first node

R1‧‧‧Resistors

C1‧‧‧ capacitor

S1‧‧‧ source extreme

S2‧‧‧ source extreme

FET1, FET2‧‧‧ field effect transistor

COUT‧‧‧End of the signal output

VDD‧‧‧

VSS‧‧‧ reference

C2‧‧‧ capacitor

N2‧‧‧ second node

R2‧‧‧ resistor

R3‧‧‧Resistors

B+‧‧‧First internal connection

B-‧‧‧Second internal connection

P+‧‧‧first external connection

P-‧‧‧ third external connection

CF‧‧‧Second external connection

CNT‧‧‧fourth external connection

V1‧‧‧ varistor

G1‧‧‧ gate extreme

G2‧‧‧ gate extreme

DOUT‧‧‧Delete the signal output

Claims (10)

A battery protection circuit package capable of electrically connecting to a battery cell, the package comprising: a substrate having a plurality of external connections and a plurality of internal connections; and a protective integrated chip disposed on the substrate (IC One or more field effect transistors (FETs), and one or more passive devices, wherein the protection IC includes an enabler when an electrical signal is input via one of the plurality of external connections These FETs are turned off to force a separate IC structure that blocks the discharge or charging of the battery cells. The battery protection circuit package of claim 1, wherein the FETs comprise a pair of FETs having a common drain and assembled as a first FET and a second FET, and wherein the protection IC comprises: a terminal for applying a charging and discharging voltage and detecting a battery voltage; a reference terminal for providing a reference voltage of an internal operating voltage; and a detecting terminal for detecting a charging/discharging and an overcurrent state; Turning off the discharge signal output end of the first FET in an overdischarge state; a charge completion signal output terminal for turning off the second FET in an overcharge state; and assembling the electrical signal to receive the electrical signal By turning off the FETs Forced blocking of the discharge or charging of the battery cell. The battery protection circuit package of claim 2, wherein the electrical signal comprises an electrical signal having a high level and a low level, and wherein the independent IC structure comprises a NOT gate. The battery protection circuit package of claim 1, wherein the protection IC is stacked on the FETs. A battery protection circuit package as claimed in claim 1, wherein the protection IC is not stacked on the FETs but disposed adjacent to the FETs and spaced apart therefrom. The battery protection circuit package of any one of claims 1 to 5, wherein the substrate comprises a lead frame having: an electrode end independently disposed at both side edges and electrically connectable to an electrode end of the battery cell a first internal connecting end pin and a second internal connecting end pin; an external connecting end pin disposed between the first and second internal connecting end pins; and the external connecting end pin; and Mounting the protection IC, the FETs, and mounting pins of at least a portion of the passive devices. The battery protection circuit package of claim 6, wherein at least one selected from the group consisting of the protection IC and the FETs is not inserted and fixed to the lead frame in the form of a semiconductor package; At least a portion of a surface of one of the lead frames is mounted and secured by surface bonding techniques in the form of wafer dies that are not sealed by a sealant. The battery protection circuit package of claim 6 further includes an electrical An electrical connection element interconnecting any one selected from the group consisting of the protection IC, the FETs, and the pins. A battery protection circuit package according to any one of claims 1 to 5, wherein the protection IC, the FETs, and the passive devices are embedded in a sub-package and then disposed on the substrate. A battery protection circuit package according to any one of claims 1 to 5, wherein the substrate comprises a printed circuit board (PCB).