TWI563597B - Bipolar junction transistors with reduced base-collector junction capacitance and fabrication methods thereof - Google Patents
Bipolar junction transistors with reduced base-collector junction capacitance and fabrication methods thereofInfo
- Publication number
- TWI563597B TWI563597B TW102112645A TW102112645A TWI563597B TW I563597 B TWI563597 B TW I563597B TW 102112645 A TW102112645 A TW 102112645A TW 102112645 A TW102112645 A TW 102112645A TW I563597 B TWI563597 B TW I563597B
- Authority
- TW
- Taiwan
- Prior art keywords
- fabrication methods
- reduced base
- collector
- transistors
- bipolar junction
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/01—Manufacture or treatment
- H10D10/051—Manufacture or treatment of vertical BJTs
- H10D10/054—Forming extrinsic base regions on silicon substrate after insulating device isolation in vertical BJTs having single crystalline emitter, collector or base regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D10/00—Bipolar junction transistors [BJT]
- H10D10/40—Vertical BJTs
- H10D10/441—Vertical BJTs having an emitter-base junction ending at a main surface of the body and a base-collector junction ending at a lateral surface of the body
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/133—Emitter regions of BJTs
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US13/452,335 US20130277804A1 (en) | 2012-04-20 | 2012-04-20 | Bipolar junction transistors with reduced base-collector junction capacitance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201426905A TW201426905A (zh) | 2014-07-01 |
| TWI563597B true TWI563597B (en) | 2016-12-21 |
Family
ID=49379336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW102112645A TWI563597B (en) | 2012-04-20 | 2013-04-10 | Bipolar junction transistors with reduced base-collector junction capacitance and fabrication methods thereof |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20130277804A1 (zh) |
| TW (1) | TWI563597B (zh) |
| WO (1) | WO2013158421A1 (zh) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI711117B (zh) * | 2018-06-20 | 2020-11-21 | 美商格芯(美國)集成電路科技有限公司 | 異質接面雙極性電晶體及形成異質接面雙極性電晶體之方法 |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9153569B1 (en) * | 2014-03-21 | 2015-10-06 | Texas Instruments Incorporated | Segmented NPN vertical bipolar transistor |
| US9722057B2 (en) * | 2015-06-23 | 2017-08-01 | Global Foundries Inc. | Bipolar junction transistors with a buried dielectric region in the active device region |
| KR102525873B1 (ko) * | 2015-10-16 | 2023-04-27 | 삼성전자주식회사 | 반도체 공정 시뮬레이션 장치 및 그것의 시뮬레이션 방법 |
| US9812447B2 (en) * | 2016-02-02 | 2017-11-07 | Globalfoundries Inc. | Bipolar junction transistors with extrinsic device regions free of trench isolation |
| US10367083B2 (en) * | 2016-03-25 | 2019-07-30 | Globalfoundries Inc. | Compact device structures for a bipolar junction transistor |
| US9847408B1 (en) * | 2016-06-21 | 2017-12-19 | Globalfoundries Inc. | Fabrication of integrated circuit structures for bipolor transistors |
| US9935186B1 (en) * | 2016-09-21 | 2018-04-03 | International Business Machines Corporation | Method of manufacturing SOI lateral Si-emitter SiGe base HBT |
| KR102402673B1 (ko) * | 2017-04-28 | 2022-05-26 | 삼성전자주식회사 | Beol의 공정 변이를 고려하여 집적 회로를 설계하기 위한 컴퓨터 구현 방법 및 컴퓨팅 시스템 |
| FR3078197B1 (fr) * | 2018-02-21 | 2020-03-13 | Stmicroelectronics (Crolles 2) Sas | Dispositif de transistor bipolaire et procede de fabrication correspondant |
| DE102020118776B4 (de) | 2019-10-31 | 2025-11-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Bipolartransistor (bjt) mit einem dielektrischen mehrschichtbasisfilm |
| US11183587B2 (en) * | 2019-10-31 | 2021-11-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bipolar junction transistor (BJT) comprising a multilayer base dielectric film |
| US11588043B2 (en) * | 2021-04-14 | 2023-02-21 | Globalfoundries U.S. Inc. | Bipolar transistor with elevated extrinsic base and methods to form same |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5345102A (en) * | 1992-02-28 | 1994-09-06 | Nec Corporation | Bipolar transistor having collector electrode penetrating emitter and base regions |
| US6635543B2 (en) * | 2000-10-17 | 2003-10-21 | International Business Machines Corporation | SOI hybrid structure with selective epitaxial growth of silicon |
| US20050145953A1 (en) * | 2004-01-05 | 2005-07-07 | Chartered Semiconductor Manufacturing Ltd | Heterojunction BiCMOS integrated circuits and method therefor |
| US20050151225A1 (en) * | 2004-01-09 | 2005-07-14 | International Business Machines Corporation | Bipolar transistor structure with self-aligned raised extrinsic base and methods |
| TW200539262A (en) * | 2004-03-13 | 2005-12-01 | Ibm | Methods of base formation in a BiCMOS process |
| US20070207567A1 (en) * | 2004-04-14 | 2007-09-06 | Geiss Peter J | Method of Base Formation in a Bicmos Process |
| TW200741916A (en) * | 2006-01-13 | 2007-11-01 | Ibm | Low resistance and inductance backside through vias and methods of fabricating same |
| US20090286368A1 (en) * | 2008-05-16 | 2009-11-19 | Chung Hon Lam | process for pcm integration with poly-emitter bjt as access device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH027529A (ja) * | 1988-06-27 | 1990-01-11 | Nec Corp | バイポーラトランジスタ及びその製造方法 |
| JP2003303830A (ja) * | 2002-04-12 | 2003-10-24 | Nec Electronics Corp | 半導体装置及びその製造方法 |
| US7190046B2 (en) * | 2004-03-29 | 2007-03-13 | International Business Machines Corporation | Bipolar transistor having reduced collector-base capacitance |
| US7892910B2 (en) * | 2007-02-28 | 2011-02-22 | International Business Machines Corporation | Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for BiCMOS integration |
| US8237191B2 (en) * | 2009-08-11 | 2012-08-07 | International Business Machines Corporation | Heterojunction bipolar transistors and methods of manufacture |
-
2012
- 2012-04-20 US US13/452,335 patent/US20130277804A1/en not_active Abandoned
-
2013
- 2013-04-10 WO PCT/US2013/035871 patent/WO2013158421A1/en not_active Ceased
- 2013-04-10 TW TW102112645A patent/TWI563597B/zh not_active IP Right Cessation
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5345102A (en) * | 1992-02-28 | 1994-09-06 | Nec Corporation | Bipolar transistor having collector electrode penetrating emitter and base regions |
| US6635543B2 (en) * | 2000-10-17 | 2003-10-21 | International Business Machines Corporation | SOI hybrid structure with selective epitaxial growth of silicon |
| US20050145953A1 (en) * | 2004-01-05 | 2005-07-07 | Chartered Semiconductor Manufacturing Ltd | Heterojunction BiCMOS integrated circuits and method therefor |
| US20050151225A1 (en) * | 2004-01-09 | 2005-07-14 | International Business Machines Corporation | Bipolar transistor structure with self-aligned raised extrinsic base and methods |
| TW200539262A (en) * | 2004-03-13 | 2005-12-01 | Ibm | Methods of base formation in a BiCMOS process |
| US20070207567A1 (en) * | 2004-04-14 | 2007-09-06 | Geiss Peter J | Method of Base Formation in a Bicmos Process |
| TW200741916A (en) * | 2006-01-13 | 2007-11-01 | Ibm | Low resistance and inductance backside through vias and methods of fabricating same |
| US20090286368A1 (en) * | 2008-05-16 | 2009-11-19 | Chung Hon Lam | process for pcm integration with poly-emitter bjt as access device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI711117B (zh) * | 2018-06-20 | 2020-11-21 | 美商格芯(美國)集成電路科技有限公司 | 異質接面雙極性電晶體及形成異質接面雙極性電晶體之方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2013158421A1 (en) | 2013-10-24 |
| US20130277804A1 (en) | 2013-10-24 |
| TW201426905A (zh) | 2014-07-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MM4A | Annulment or lapse of patent due to non-payment of fees |