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TWI562543B - Digital delay unit and signal delay circuit - Google Patents

Digital delay unit and signal delay circuit

Info

Publication number
TWI562543B
TWI562543B TW104104674A TW104104674A TWI562543B TW I562543 B TWI562543 B TW I562543B TW 104104674 A TW104104674 A TW 104104674A TW 104104674 A TW104104674 A TW 104104674A TW I562543 B TWI562543 B TW I562543B
Authority
TW
Taiwan
Prior art keywords
digital
signal
delay circuit
unit
delay unit
Prior art date
Application number
TW104104674A
Other languages
English (en)
Other versions
TW201630347A (zh
Inventor
Yu Hsuan Cheng
Original Assignee
Silicon Motion Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Silicon Motion Inc filed Critical Silicon Motion Inc
Priority to TW104104674A priority Critical patent/TWI562543B/zh
Priority to CN201510321530.0A priority patent/CN106209075B/zh
Priority to US15/008,919 priority patent/US9692399B2/en
Publication of TW201630347A publication Critical patent/TW201630347A/zh
Application granted granted Critical
Publication of TWI562543B publication Critical patent/TWI562543B/zh

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/14—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of delay lines
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/00019—Variable delay
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00234—Layout of the delay element using circuits having two logic levels

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)
TW104104674A 2015-02-12 2015-02-12 Digital delay unit and signal delay circuit TWI562543B (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW104104674A TWI562543B (en) 2015-02-12 2015-02-12 Digital delay unit and signal delay circuit
CN201510321530.0A CN106209075B (zh) 2015-02-12 2015-06-12 数字延迟单元与信号延迟电路
US15/008,919 US9692399B2 (en) 2015-02-12 2016-01-28 Digital delay unit and signal delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW104104674A TWI562543B (en) 2015-02-12 2015-02-12 Digital delay unit and signal delay circuit

Publications (2)

Publication Number Publication Date
TW201630347A TW201630347A (zh) 2016-08-16
TWI562543B true TWI562543B (en) 2016-12-11

Family

ID=56621500

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104104674A TWI562543B (en) 2015-02-12 2015-02-12 Digital delay unit and signal delay circuit

Country Status (3)

Country Link
US (1) US9692399B2 (zh)
CN (1) CN106209075B (zh)
TW (1) TWI562543B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107528584A (zh) * 2017-07-19 2017-12-29 成都华微电子科技有限公司 复用延迟线的高精度数字延时锁相环
CN109495105A (zh) * 2018-12-29 2019-03-19 灿芯半导体(上海)有限公司 一种基于onfi的dll单元电路
CN111884636B (zh) * 2020-06-17 2024-04-12 芯创智（北京）微电子有限公司 一种rs触发器输出延时补偿电路
CN111865271B (zh) * 2020-07-14 2023-08-18 江苏应能微电子有限公司 一种延时电路、方法、防止信号误触发电路和集成电路
CN112291120B (zh) * 2020-12-29 2021-06-15 苏州裕太微电子有限公司 一种延时线结构及其时延抖动的校正方法
CN112702044B (zh) * 2020-12-31 2021-10-12 广芯微电子（广州）股份有限公司 一种高精度数据延迟线的物理实现结构

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030052719A1 (en) * 2001-09-20 2003-03-20 Na Kwang Jin Digital delay line and delay locked loop using the digital delay line
TW546646B (en) * 2001-12-12 2003-08-11 Hynix Semiconductor Inc Register controlled DLL circuit
US7173468B2 (en) * 2004-09-27 2007-02-06 Synopsys, Inc. Multiple-input, single-exit delay line architecture
KR100855274B1 (ko) * 2007-03-30 2008-09-01 주식회사 하이닉스반도체 유닛 딜레이 셀 및 이를 포함하는 지연 고정 루프
CN1983811B (zh) * 2005-12-12 2010-05-19 三星电子株式会社 延时单元和具有其的延迟线电路
TW201103036A (en) * 2009-07-03 2011-01-16 Hynix Semiconductor Inc Delay line
TWI358902B (en) * 2007-12-31 2012-02-21 Ind Tech Res Inst Signal delay circuit
US20140077852A1 (en) * 2004-08-26 2014-03-20 Micron Technology, Inc. Delay line off-state control with power reduction

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2844655A1 (fr) * 2002-09-13 2004-03-19 St Microelectronics Sa Transformation d'un signal periodique en un signal de frequence ajustable
KR100663361B1 (ko) * 2005-05-17 2007-01-02 삼성전자주식회사 지연 회로 및 이를 구비한 반도체 장치
CN101499790B (zh) * 2008-01-28 2012-06-27 财团法人工业技术研究院 信号延迟电路
CN101562440B (zh) * 2009-05-12 2010-11-10 华为技术有限公司 延迟模块和方法、时钟检测装置及数字锁相环

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030052719A1 (en) * 2001-09-20 2003-03-20 Na Kwang Jin Digital delay line and delay locked loop using the digital delay line
TW546646B (en) * 2001-12-12 2003-08-11 Hynix Semiconductor Inc Register controlled DLL circuit
US20140077852A1 (en) * 2004-08-26 2014-03-20 Micron Technology, Inc. Delay line off-state control with power reduction
US7173468B2 (en) * 2004-09-27 2007-02-06 Synopsys, Inc. Multiple-input, single-exit delay line architecture
CN1983811B (zh) * 2005-12-12 2010-05-19 三星电子株式会社 延时单元和具有其的延迟线电路
KR100855274B1 (ko) * 2007-03-30 2008-09-01 주식회사 하이닉스반도체 유닛 딜레이 셀 및 이를 포함하는 지연 고정 루프
TWI358902B (en) * 2007-12-31 2012-02-21 Ind Tech Res Inst Signal delay circuit
TW201103036A (en) * 2009-07-03 2011-01-16 Hynix Semiconductor Inc Delay line

Also Published As

Publication number Publication date
CN106209075A (zh) 2016-12-07
CN106209075B (zh) 2019-04-12
US9692399B2 (en) 2017-06-27
US20160241224A1 (en) 2016-08-18
TW201630347A (zh) 2016-08-16

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