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TWI560545B - Dynamically updating hardware prefetch trait to exclusive or shared at program detection - Google Patents

Dynamically updating hardware prefetch trait to exclusive or shared at program detection

Info

Publication number
TWI560545B
TWI560545B TW104134317A TW104134317A TWI560545B TW I560545 B TWI560545 B TW I560545B TW 104134317 A TW104134317 A TW 104134317A TW 104134317 A TW104134317 A TW 104134317A TW I560545 B TWI560545 B TW I560545B
Authority
TW
Taiwan
Prior art keywords
trait
exclusive
shared
dynamically updating
program detection
Prior art date
Application number
TW104134317A
Other languages
English (en)
Other versions
TW201629775A (zh
Inventor
Rodney E Hooker
Albert J Loper
John Michael Greer
Original Assignee
Via Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Via Tech Inc filed Critical Via Tech Inc
Publication of TW201629775A publication Critical patent/TW201629775A/zh
Application granted granted Critical
Publication of TWI560545B publication Critical patent/TWI560545B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30047—Prefetch instructions; cache control instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815—Cache consistency protocols
    • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842—Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0629—Configuration or reconfiguration of storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0673—Single storage device
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/30105—Register structure
    • G06F9/30109—Register structure having multiple operands in a single register
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/45—Caching of specific data in cache memory
    • G06F2212/452—Instruction code
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6022—Using a prefetch buffer or dedicated prefetch cache
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6024—History based prefetching

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Human Computer Interaction (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
TW104134317A 2014-10-20 2015-10-20 Dynamically updating hardware prefetch trait to exclusive or shared at program detection TWI560545B (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201462066131P 2014-10-20 2014-10-20
US14/625,124 US10514920B2 (en) 2014-10-20 2015-02-18 Dynamically updating hardware prefetch trait to exclusive or shared at program detection
US14/624,981 US9891916B2 (en) 2014-10-20 2015-02-18 Dynamically updating hardware prefetch trait to exclusive or shared in multi-memory access agent system

Publications (2)

Publication Number Publication Date
TW201629775A TW201629775A (zh) 2016-08-16
TWI560545B true TWI560545B (en) 2016-12-01

Family

ID=55749143

Family Applications (2)

Application Number Title Priority Date Filing Date
TW104134316A TWI560547B (en) 2014-10-20 2015-10-20 Dynamically updating hardware prefetch trait to exclusive or shared in multi-memory access agent
TW104134317A TWI560545B (en) 2014-10-20 2015-10-20 Dynamically updating hardware prefetch trait to exclusive or shared at program detection

Family Applications Before (1)

Application Number Title Priority Date Filing Date
TW104134316A TWI560547B (en) 2014-10-20 2015-10-20 Dynamically updating hardware prefetch trait to exclusive or shared in multi-memory access agent

Country Status (2)

Country Link
US (2) US10514920B2 (zh)
TW (2) TWI560547B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10866896B2 (en) * 2015-09-30 2020-12-15 Arm Limited Apparatus and method for prefetching access request addresses in an adjacent region of memory
GB2547189A (en) * 2016-02-03 2017-08-16 Swarm64 As Cache and method
US10802971B2 (en) * 2016-10-13 2020-10-13 International Business Machines Corporation Cache memory transaction shielding via prefetch suppression
US10664273B2 (en) 2018-03-30 2020-05-26 Intel Corporation Delayed prefetch manager to multicast an updated cache line to processor cores requesting the updated data
US10963249B2 (en) * 2018-11-02 2021-03-30 International Business Machines Corporation Processor prefetcher mode governor for switching between prefetch modes
TWI755878B (zh) * 2020-09-30 2022-02-21 威聯通科技股份有限公司 動態改變資料預取量的方法及使用其之終端裝置
US11853569B2 (en) * 2021-01-28 2023-12-26 Nutanix, Inc. Metadata cache warmup after metadata cache loss or migration

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200413909A (en) * 2002-10-10 2004-08-01 Intel Corp An apparatus and method for facilitating memory data access with generic read/write patterns
TW200834322A (en) * 2006-12-19 2008-08-16 Ibm System and method for implementing an enhanced hover state with active prefetches
TW201101178A (en) * 2008-12-30 2011-01-01 Intel Corp Extending cache coherency protocols to support locally buffered data
US20110219208A1 (en) * 2010-01-08 2011-09-08 International Business Machines Corporation Multi-petascale highly efficient parallel supercomputer
TW201303602A (zh) * 2011-06-09 2013-01-16 Apple Inc 用於快取區塊連貫性之系統、方法及裝置
TW201342060A (zh) * 2011-12-29 2013-10-16 Intel Corp 支援不帶資料的推測式所有權之技術
TW201346757A (zh) * 2011-12-29 2013-11-16 Intel Corp 指令快取預取的管理
TW201351147A (zh) * 2009-07-10 2013-12-16 Via Tech Inc 用以快取資料的電腦程式產品

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7089371B2 (en) 2002-02-12 2006-08-08 Ip-First, Llc Microprocessor apparatus and method for prefetch, allocation, and initialization of a block of cache lines from memory
US7089368B2 (en) 2002-02-12 2006-08-08 Ip-First, Llc Microprocessor apparatus and method for exclusively prefetching a block of cache lines from memory
KR20060130120A (ko) * 2004-03-24 2006-12-18 마쯔시다덴기산교 가부시키가이샤 캐시 메모리 및 그 제어 방법
US7318125B2 (en) * 2004-05-20 2008-01-08 International Business Machines Corporation Runtime selective control of hardware prefetch mechanism
US7441087B2 (en) 2004-08-17 2008-10-21 Nvidia Corporation System, apparatus and method for issuing predictions from an inventory to access a memory
US8122195B2 (en) * 2007-12-12 2012-02-21 International Business Machines Corporation Instruction for pre-fetching data and releasing cache lines
US8566565B2 (en) 2008-07-10 2013-10-22 Via Technologies, Inc. Microprocessor with multiple operating modes dynamically configurable by a device driver based on currently running applications
GB2458005B (en) 2009-02-12 2010-01-20 Gzero Ltd Removing non-essential programs identified by a server from memory
US8762649B2 (en) 2010-03-29 2014-06-24 Via Technologies, Inc. Bounding box prefetcher
CN105183663B (zh) * 2010-03-29 2018-11-27 威盛电子股份有限公司 预取单元和数据预取方法
DE112011106013T5 (de) * 2011-12-21 2014-10-02 Intel Corp. System und Verfahren für den intelligenten Datentransfer von einem Prozessor in ein Speicheruntersystem
US9098418B2 (en) * 2012-03-20 2015-08-04 Apple Inc. Coordinated prefetching based on training in hierarchically cached processors
KR20140113103A (ko) 2013-03-15 2014-09-24 삼성전자주식회사 호스트 및 메모리 시스템을 포함하는 사용자 시스템의 동작 방법

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200413909A (en) * 2002-10-10 2004-08-01 Intel Corp An apparatus and method for facilitating memory data access with generic read/write patterns
TW200834322A (en) * 2006-12-19 2008-08-16 Ibm System and method for implementing an enhanced hover state with active prefetches
TW201101178A (en) * 2008-12-30 2011-01-01 Intel Corp Extending cache coherency protocols to support locally buffered data
TW201351147A (zh) * 2009-07-10 2013-12-16 Via Tech Inc 用以快取資料的電腦程式產品
US20110219208A1 (en) * 2010-01-08 2011-09-08 International Business Machines Corporation Multi-petascale highly efficient parallel supercomputer
TW201303602A (zh) * 2011-06-09 2013-01-16 Apple Inc 用於快取區塊連貫性之系統、方法及裝置
TW201342060A (zh) * 2011-12-29 2013-10-16 Intel Corp 支援不帶資料的推測式所有權之技術
TW201346757A (zh) * 2011-12-29 2013-11-16 Intel Corp 指令快取預取的管理

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
計算機結構：計量方法，JohnL. Hennessy, David A. Patterson作，郭景致等譯，2012年五版，ISBN 978-957-483-728-1 *

Also Published As

Publication number Publication date
TW201629775A (zh) 2016-08-16
TW201621671A (zh) 2016-06-16
US10514920B2 (en) 2019-12-24
US20160110194A1 (en) 2016-04-21
US9891916B2 (en) 2018-02-13
US20160110289A1 (en) 2016-04-21
TWI560547B (en) 2016-12-01

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