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TWI559563B - Hybrid polycrystalline germanium heterojunction back contact battery - Google Patents

Hybrid polycrystalline germanium heterojunction back contact battery Download PDF

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TWI559563B
TWI559563B TW101148468A TW101148468A TWI559563B TW I559563 B TWI559563 B TW I559563B TW 101148468 A TW101148468 A TW 101148468A TW 101148468 A TW101148468 A TW 101148468A TW I559563 B TWI559563 B TW I559563B
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layer
doped
germanium
solar cell
band gap
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TW101148468A
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TW201344931A (en
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彼得 可森斯
大衛 史密斯
林承
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太陽電子公司
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    • H10F10/00Individual photovoltaic cells, e.g. solar cells
    • H10F10/10Individual photovoltaic cells, e.g. solar cells having potential barriers
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    • H10F10/10Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/16Photovoltaic cells having only PN heterojunction potential barriers
    • H10F10/164Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells
    • H10F10/165Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells
    • H10F10/166Photovoltaic cells having only PN heterojunction potential barriers comprising heterojunctions with Group IV materials, e.g. ITO/Si or GaAs/SiGe photovoltaic cells the heterojunctions being Group IV-IV heterojunctions, e.g. Si/Ge, SiGe/Si or Si/SiC photovoltaic cells the Group IV-IV heterojunctions being heterojunctions of crystalline and amorphous materials, e.g. silicon heterojunction [SHJ] photovoltaic cells
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    • H10F71/121The active layers comprising only Group IV materials
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    • H10F77/16Material structures, e.g. crystalline structures, film structures or crystal plane orientations
    • H10F77/162Non-monocrystalline materials, e.g. semiconductor particles embedded in insulating materials
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    • H10F77/10Semiconductor bodies
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Description

混合式多晶矽異質接面背接觸電池 Hybrid polycrystalline germanium heterojunction back contact battery

本說明書所述申請標的之實施例大致上係關於太陽能電池之製造。具體而言,申請標的之實施例係關於薄矽太陽能電池及製造技術。 The embodiments of the subject matter described in this specification relate generally to the manufacture of solar cells. In particular, the embodiments of the application are directed to thin tan solar cells and manufacturing techniques.

眾所皆知的太陽能電池為將太陽輻射轉換成電能的裝置。可利用半導體製程技術將其製造於半導體晶圓上。太陽能電池包括P型與N型擴散區域。照射於太陽能電池上的太陽輻射產生遷移至擴散區域的電子與電洞,因而在擴散區域間形成壓差。在背側接觸式太陽能電池中,擴散區域與耦接至擴散區域的金屬接觸指均位於太陽能電池的背側上。接觸指使得外部電路得以耦接至太陽能電池並由太陽能電池供電。 A well-known solar cell is a device that converts solar radiation into electrical energy. It can be fabricated on semiconductor wafers using semiconductor process technology. Solar cells include P-type and N-type diffusion regions. The solar radiation that is incident on the solar cell generates electrons and holes that migrate to the diffusion region, thus creating a pressure difference between the diffusion regions. In the backside contact solar cell, the diffusion region and the metal contact fingers coupled to the diffusion region are both located on the back side of the solar cell. The contact fingers enable an external circuit to be coupled to and powered by the solar cell.

效率是太陽能電池的一個重要特性,因為其直接與太陽能電池產生電力的能力相關。因此,一般期望能有改善生產製程、降低製造成本及增加太陽能電池效率的技術。此等技術包括藉由熱製程在矽基板上形成多晶矽及異質接面層(heterojunction layers),其中本發明得以增加太陽能電池效率。此等及其他類似實施例形成本發明之背景。 Efficiency is an important feature of solar cells because it is directly related to the ability of solar cells to generate electricity. Therefore, it is generally desired to have a technology for improving the production process, reducing the manufacturing cost, and increasing the efficiency of the solar cell. Such techniques include the formation of polycrystalline germanium and heterojunction layers on a germanium substrate by a thermal process wherein the present invention increases solar cell efficiency. These and other similar embodiments form the background of the invention.

所揭示者為一種製造太陽能電池之方法。該方法包含提供矽基板,其具有薄介電層於背側上、以及經沉積矽層於薄介電層上方;於該經沉積矽層上方形成摻雜材料層;於摻雜材料層上方形成氧化物層;以交指(interdigitated)圖樣部分移除氧化物層、摻雜材料層及經沉積矽層;成長氧化物層並同時提高溫度以驅使摻雜劑由摻雜材料層進入經沉積矽層;利用來自摻雜材料層的摻雜劑對經沉積矽層進行摻雜,以形成結晶化經摻雜多晶矽層;於太陽能電池之背側上沉積寬能帶間隙經摻雜半導體及抗反射塗層;以及於太陽能電池之前側上沉積寬能帶間隙經摻雜半導體及抗反射塗層。 The disclosed method is a method of manufacturing a solar cell. The method includes providing a germanium substrate having a thin dielectric layer on the back side and a deposited germanium layer over the thin dielectric layer; forming a dopant material layer over the deposited germanium layer; forming over the dopant material layer An oxide layer; partially removing the oxide layer, the dopant material layer, and the deposited germanium layer in an interdigitated pattern; growing the oxide layer while increasing temperature to drive the dopant from the dopant material layer into the deposited germanium layer Layer; doping the deposited tantalum layer with a dopant from the doped material layer to form a crystallized doped polysilicon layer; depositing a wide band gap doped semiconductor and anti-reflection on the back side of the solar cell a coating; and depositing a broad band gap doped semiconductor and an anti-reflective coating on the front side of the solar cell.

所揭示者為另一種製造太陽能電池之方法。該方法包括提供矽基板,其具有薄介電層於背側上、以及經沉積矽層於薄介電層上方;於經沉積矽層上方形成摻雜材料層;於摻雜材料層上方形成氧化物層;以交指圖樣部分移除氧化物層、摻雜材料層及經沉積矽層;蝕刻經暴露之矽基板以形成粗化矽區域;成長氧化物層並同時提高溫度以驅使摻雜劑由摻雜材料層進入經沉積矽層;利用來自摻雜材料層的摻雜劑對經沉積矽層進行摻雜,以形成經摻雜多晶矽層;於太陽能電池之背側上覆蓋寬能帶間隙經摻雜非晶矽之第一厚層及抗反射塗層;於太陽能電池之前側上覆蓋寬能帶間隙經摻雜非晶矽之第二薄層及抗反射塗層,且其中薄層小於厚層厚度之10%至30%。 The disclosed method is another method of manufacturing a solar cell. The method includes providing a germanium substrate having a thin dielectric layer on the back side and a deposited germanium layer over the thin dielectric layer; forming a dopant material layer over the deposited germanium layer; forming an oxide over the dopant material layer a layer of the oxide layer, a layer of doped material, and a layer of deposited germanium; the exposed germanium substrate is etched to form a roughened germanium region; the oxide layer is grown while the temperature is raised to drive the dopant From the doped material layer into the deposited germanium layer; doping the deposited germanium layer with a dopant from the doped material layer to form a doped polysilicon layer; covering the wide band gap on the back side of the solar cell a first thick layer of an amorphous germanium and an anti-reflective coating; a second thin layer of the doped amorphous germanium with a wide band gap and an anti-reflective coating on the front side of the solar cell, wherein the thin layer is smaller than 10% to 30% of the thickness of the thick layer.

所揭示者為再一種製造太陽能電池之方法。該方法包括提供矽基板,其具有薄介電層於背側上,以及經摻雜矽層於薄介電層上方;於經摻雜矽層上方形成氧化物層;以交指圖樣部分移除氧化物層及經摻雜矽層;藉由於含氧環境中加熱矽基板,以在太陽能電池之背側上方成長矽氧化物層,其中經摻 雜矽層係經結晶化以形成經摻雜多晶矽層;於太陽能電池之背側上沉積寬能帶間隙經摻雜半導體;以及於太陽能電池之前側上沉積寬能帶間隙經摻雜半導體及抗反射塗層。 The disclosed method is another method of manufacturing a solar cell. The method includes providing a germanium substrate having a thin dielectric layer on the back side and a doped germanium layer over the thin dielectric layer; forming an oxide layer over the doped germanium layer; partially removing the interdigitated pattern An oxide layer and a doped germanium layer; by heating the germanium substrate in an oxygen-containing environment to grow a germanium oxide layer over the back side of the solar cell, wherein the germanium oxide layer is doped The doped layer is crystallized to form a doped polysilicon layer; a broad band gap-doped semiconductor is deposited on the back side of the solar cell; and a broad band gap is doped semiconductor on the front side of the solar cell Reflective coating.

所揭示者為再一種製造太陽能電池之方法。該方法包括提供矽基板,其具有薄介電層於背側上、以及經摻雜矽層於薄介電層上方;於經摻雜矽層上方形成氧化物層;以交指圖樣部分移除氧化物層及經摻雜矽層;蝕刻經暴露之矽基板以形成粗化矽區域;藉由於含氧環境中加熱矽基板,以在太陽能電池之背側上方成長矽氧化物層,其中經摻雜矽層係經結晶化以形成經摻雜多晶矽層;於太陽能電池之背側上沉積寬能帶間隙經摻雜非晶矽及抗反射塗層;以及於太陽能電池之前側上沉積寬能帶間隙經摻雜非晶矽及抗反射塗層。 The disclosed method is another method of manufacturing a solar cell. The method includes providing a germanium substrate having a thin dielectric layer on the back side and a doped germanium layer over the thin dielectric layer; forming an oxide layer over the doped germanium layer; partially removing the interdigitated pattern An oxide layer and a doped germanium layer; etching the exposed germanium substrate to form a roughened germanium region; by heating the germanium substrate in an oxygen-containing environment to grow a germanium oxide layer over the back side of the solar cell, wherein the germanium oxide layer is grown The hybrid layer is crystallized to form a doped polysilicon layer; a broad band gap-doped amorphous germanium and anti-reflective coating is deposited on the back side of the solar cell; and a broad band is deposited on the front side of the solar cell The gap is doped with an amorphous germanium and an anti-reflective coating.

所揭示者為一種製造太陽能電池之方法的另一實施例。該方法包括提供矽基板,其具有薄介電層於背側上、以及經摻雜矽層於薄介電層上方;於經摻雜矽層上方形成氧化物層;以交指圖樣部分移除氧化物層及經摻雜矽層;蝕刻經暴露之矽基板以形成粗化矽區域;藉由於含氧環境中加熱矽基板,以在該太陽能電池之背側上方成長矽氧化物層,其中經摻雜矽層係經結晶化以形成經摻雜多晶矽層;於太陽能電池之前側與背側上方同時沉積寬能帶間隙經摻雜非晶矽及抗反射塗層;部分移除寬能帶間隙經摻雜半導體及氧化物層,以形成一系列接觸開口;以及同時形成第一金屬柵極及第二金屬柵極,第一金屬柵極係電性耦接至經摻雜多晶矽層,第二金屬柵極係電性耦接至太陽能電池之背側上的射極區域。 The disclosed is another embodiment of a method of making a solar cell. The method includes providing a germanium substrate having a thin dielectric layer on the back side and a doped germanium layer over the thin dielectric layer; forming an oxide layer over the doped germanium layer; partially removing the interdigitated pattern An oxide layer and a doped germanium layer; etching the exposed germanium substrate to form a roughened germanium region; by heating the germanium substrate in an oxygen-containing environment to grow a germanium oxide layer over the back side of the solar cell, wherein The doped lanthanum layer is crystallized to form a doped polysilicon layer; a broad band gap is doped with an amorphous yttrium and an anti-reflective coating simultaneously on the front side and the back side of the solar cell; partially removing the wide band gap The semiconductor and oxide layers are doped to form a series of contact openings; and the first metal gate and the second metal gate are simultaneously formed, the first metal gate is electrically coupled to the doped polysilicon layer, and the second The metal gate is electrically coupled to the emitter region on the back side of the solar cell.

一種用於製造太陽能電池之改良技術係用以在矽基板之背側上提供薄介電層及經沉積矽層。可利用驅使摻雜劑進入經沉積矽層而形成經摻雜 多晶矽區域,或利用原位形成經摻雜多晶矽區域。之後可在太陽能電池之前側及背側上形成氧化物層及寬能帶間隙經摻雜半導體層。另一種作法是在氧化物及寬能帶間隙經摻雜半導體形成之前先粗化前表面及背表面。之後可形成穿過上層的接觸孔以暴露出經摻雜多晶矽區域。接著可進行金屬化製程以將接點形成至經摻雜多晶矽層上。藉由將金屬直接連接至矽基板上的射極區域亦可形成第二組接點,其中射極區域係由位於太陽能電池之背側上的經摻雜多晶矽區域間的寬能帶間隙半導體層所形成。 An improved technique for fabricating solar cells is to provide a thin dielectric layer and a deposited germanium layer on the back side of the germanium substrate. The dopant can be driven into the deposited germanium layer to form a doped The polysilicon region is formed, or the doped polysilicon region is formed in situ. An oxide layer and a wide band gap doped semiconductor layer can then be formed on the front side and the back side of the solar cell. Another approach is to roughen the front and back surfaces before the oxide and wide band gaps are formed by the doped semiconductor. A contact hole through the upper layer may then be formed to expose the doped polysilicon region. A metallization process can then be performed to form the contacts onto the doped polysilicon layer. A second set of contacts may also be formed by directly connecting the metal to the emitter region on the germanium substrate, wherein the emitter region is a wide band gap semiconductor layer between the doped polysilicon regions on the back side of the solar cell. Formed.

100‧‧‧太陽能電池 100‧‧‧ solar cells

102‧‧‧矽基板 102‧‧‧矽 substrate

104‧‧‧經沉積矽層 104‧‧‧Sedimentary layer

106‧‧‧薄介電層 106‧‧‧thin dielectric layer

108‧‧‧摻雜材料層 108‧‧‧Doped material layer

109‧‧‧摻雜劑 109‧‧‧Dopants

110‧‧‧第一氧化物層 110‧‧‧First oxide layer

112‧‧‧第二氧化物層 112‧‧‧Second oxide layer

114‧‧‧第三氧化物層 114‧‧‧ third oxide layer

124‧‧‧暴露之多晶矽區域 124‧‧‧ exposed polysilicon area

130‧‧‧第一粗化矽區域 130‧‧‧First roughening area

132‧‧‧第二粗化矽區域 132‧‧‧Second roughening area

140‧‧‧加熱 140‧‧‧heating

150‧‧‧經摻雜多晶矽層 150‧‧‧Doped polysilicon layer

160‧‧‧第一寬能帶間隙經摻雜半導體層 160‧‧‧First wide band gap doped semiconductor layer

162‧‧‧第二寬能帶間隙經摻雜半導體層 162‧‧‧Second wide band gap doped semiconductor layer

170‧‧‧抗反射塗層 170‧‧‧Anti-reflective coating

180‧‧‧接觸開口 180‧‧‧Contact opening

190‧‧‧第一金屬柵極線 190‧‧‧First metal gate line

192‧‧‧第二金屬柵極線 192‧‧‧Second metal gate line

200‧‧‧太陽能電池 200‧‧‧ solar cells

202‧‧‧矽基板 202‧‧‧矽 substrate

206‧‧‧薄介電層 206‧‧‧thin dielectric layer

209‧‧‧摻雜材料 209‧‧‧Doped materials

210‧‧‧第一氧化物層 210‧‧‧First oxide layer

212‧‧‧第二氧化物層 212‧‧‧Second oxide layer

214‧‧‧第三氧化物層 214‧‧‧ third oxide layer

220‧‧‧矽基板的暴露區域 220‧‧‧矽 exposed areas of the substrate

230‧‧‧第一粗化矽區域 230‧‧‧First roughening area

232‧‧‧第二粗化矽區域 232‧‧‧Second roughening area

240‧‧‧加熱 240‧‧‧heating

250‧‧‧經摻雜多晶矽層 250‧‧‧Doped polysilicon layer

260‧‧‧第一寬能帶間隙經摻雜半導體層 260‧‧‧The first wide band gap doped semiconductor layer

262‧‧‧第二寬能帶間隙經摻雜半導體層 262‧‧‧Second wide band gap doped semiconductor layer

270‧‧‧抗反射塗層 270‧‧‧Anti-reflective coating

290‧‧‧第一金屬柵極線 290‧‧‧First metal gate line

292‧‧‧第二金屬柵極線 292‧‧‧Second metal gate line

可同時參考詳細說明及申請專利範圍並搭配以下圖式以對本申請標的有更完整的了解,其中圖式的類似元件符號係指類似元件。 A more complete understanding of the subject matter of the present application can be made by referring to the detailed description and claims.

第1圖至第12圖為根據本發明一實施例製造之太陽能電池的剖面示意圖。 1 to 12 are schematic cross-sectional views of a solar cell fabricated in accordance with an embodiment of the present invention.

第13圖至第18圖為根據本發明另一實施例製造之太陽能電池的剖面示意圖。 13 to 18 are schematic cross-sectional views showing a solar cell manufactured according to another embodiment of the present invention.

以下詳細說明本質上僅為輔助說明,且並不欲用以限制申請標的之實施例或該等實施例的應用或用途。於本說明書中,用語「例示性(exemplary)」代表「作為一實例、範例或說明」。本說明書中任一種描述為例示性的實施態樣並不必然可解讀為相對其他實施態樣為較佳或較有利者。此外,本案並不意欲受到前述技術領域、先前技術、發明內容或以下詳細說明中所呈現之任何明示或暗示理論的限制。 The following detailed description is merely for the purpose of illustration, and is not intended to limit the embodiments of the application or the application or use of the embodiments. In the present specification, the term "exemplary" means "as an example, an example or a description." Any one of the specification described as an exemplary embodiment is not necessarily to be construed as preferred or advantageous over other embodiments. In addition, the present invention is not intended to be limited by the scope of the present invention, the prior art, the invention, or the following detailed description.

與製造方法有關的各種實施態樣如第1圖至第18圖所示。此外,各種實施態樣之某幾個不必然以所示順序進行,且其可併入具有本說明書未記載之其他功能的較完整程序、製程或製造方法中。 Various embodiments relating to the manufacturing method are shown in Figs. 1 to 18. In addition, some of the various embodiments are not necessarily in the order shown, and may be incorporated in a more complete procedure, process or method of manufacture having other functions not described herein.

第1圖至第3圖繪示用於製造太陽能電池100之一實施例,其包含矽基板102、薄介電層106及經沉積矽層104。在某些實施例中,可在形成薄介電層106之前先將矽基板102進行清潔、研磨、平面化及/或薄型化或其他處理。可利用熱製程來成長該薄介電層106及經沉積矽層104。可利用現有沉積製程在經沉積矽層104上方依序沉積摻雜材料層108及第一氧化物層110。摻雜材料層108可包括摻雜材料或摻雜劑109,但並不限於一層正型摻雜材料,例如硼、或一層負型摻雜材料,例如磷。雖然薄介電層106及經沉積矽層104如前述係分別利用熱製程進行成長或利用現有沉積製程進行沉積,然如同本說明書所述或所引用之任一種其他形成、沉積或成長製程步驟一般,各層或物質亦可利用任一種適合的製程來形成。舉例而言,在提到形成方法時,可使用化學氣相沉積(chemical vapor deposition,CVD)製程、低壓化學氣相沉積(low-pressure chemical vapor deposition,LPCVD)、大氣壓化學氣相沉積(atmospheric pressure chemical vapor deposition,APCVD)、電漿加強化學氣相沉積(plasma-enhanced chemical vapor deposition,PECVD)、熱成長、濺鍍以及任何其他理想的技術。因此,如前所述,可利用沉積技術、濺鍍或印刷製程(例如噴墨印刷或網印)將摻雜材料108形成在基板上。 FIGS. 1 through 3 illustrate an embodiment for fabricating a solar cell 100 that includes a germanium substrate 102, a thin dielectric layer 106, and a deposited germanium layer 104. In some embodiments, the germanium substrate 102 can be cleaned, ground, planarized, and/or thinned or otherwise processed prior to forming the thin dielectric layer 106. The thin dielectric layer 106 and the deposited germanium layer 104 can be grown using a thermal process. The doped material layer 108 and the first oxide layer 110 may be sequentially deposited over the deposited germanium layer 104 using an existing deposition process. The doped material layer 108 may include a dopant material or dopant 109, but is not limited to a layer of positive dopant material, such as boron, or a layer of negative dopant material, such as phosphorus. Although the thin dielectric layer 106 and the deposited germanium layer 104 are grown by a thermal process, respectively, or by an existing deposition process, as in any other forming, deposition, or growth process steps described or referenced herein. Each layer or substance may also be formed using any suitable process. For example, when referring to the formation method, a chemical vapor deposition (CVD) process, a low-pressure chemical vapor deposition (LPCVD), an atmospheric pressure chemical vapor deposition (atmospheric pressure) may be used. Chemical vapor deposition (APCVD), plasma-enhanced chemical vapor deposition (PECVD), thermal growth, sputtering, and any other desirable technique. Thus, as previously described, the doping material 108 can be formed on the substrate using deposition techniques, sputtering or printing processes such as inkjet printing or screen printing.

第4圖繪示與第1圖至第3圖相同的太陽能電池100,且其係已完成一材料移除製程以形成暴露之多晶矽區域124。材料移除製程的某些實例包括遮罩及蝕刻製程、雷射剝蝕製程及其他類似技術。可將暴露之多晶矽區域124與摻雜材料層108形成為任意理想形狀,包括交指圖樣(interdigitated pattern)。若是使用遮罩製程,則可利用網印機或噴墨印刷機以預定的交指圖樣施用遮罩墨水。因此,可使用現有化學濕式蝕刻技術來移除遮罩墨水,從而形成暴露多晶矽區 域124與摻雜材料108層的交指圖樣。在至少一實施例中,可移除部分或全部的第一氧化物層110。此可於移除經沉積矽層104及薄介電層106之區域的相同的蝕刻或剝蝕製程中完成,如第4圖及第5圖所示。 4 depicts the same solar cell 100 as in FIGS. 1 through 3, and has completed a material removal process to form exposed polysilicon regions 124. Some examples of material removal processes include masking and etching processes, laser ablation processes, and the like. The exposed polysilicon region 124 and dopant material layer 108 can be formed into any desired shape, including an interdigitated pattern. If a mask process is used, the mask ink can be applied in a predetermined interdigitated pattern using a screen printer or ink jet printer. Therefore, existing chemical wet etching techniques can be used to remove the masking ink to form an exposed polysilicon region. The intersection of the domain 124 and the layer of dopant material 108. In at least one embodiment, some or all of the first oxide layer 110 can be removed. This can be accomplished in the same etching or ablation process where the regions of the deposited germanium layer 104 and the thin dielectric layer 106 are removed, as shown in Figures 4 and 5.

請參見第5圖,太陽能電池100可經歷第二蝕刻製程以蝕刻暴露之多晶矽區域124,而在太陽能電池的背側上形成第一粗化矽區域130並在太陽能電池的前側上形成第二粗化矽區域132以促進太陽輻射之收集。粗化表面可為具有規則或不規則形狀之表面以散射入射光,進而減少由太陽能電池表面反射回去的光量。 Referring to FIG. 5, the solar cell 100 may undergo a second etching process to etch the exposed polysilicon region 124, while forming a first roughened germanium region 130 on the back side of the solar cell and a second thick on the front side of the solar cell. The pupation area 132 is used to promote the collection of solar radiation. The roughened surface can be a surface having a regular or irregular shape to scatter incident light, thereby reducing the amount of light reflected back from the surface of the solar cell.

請參見第6圖,可對太陽能電池100進行加熱140,以驅使摻雜材料109由摻雜材料層108進入經沉積矽層104。相同的加熱140也可在摻雜材料層108與第一粗化矽區域130上方形成矽氧化物或第二氧化物層112。在此製程期間,可在第二粗化矽區域132上方成長第三氧化物層114。兩個氧化物層112、114均可包括高品質氧化物。高品質氧化物為一種低界面態密度之氧化物,其通常利用熱氧化法在高於攝氏900度之溫度下成長而可提供改善的鈍化。 Referring to FIG. 6, solar cell 100 can be heated 140 to drive dopant material 109 from dopant material layer 108 into deposited germanium layer 104. The same heating 140 may also form a tantalum oxide or second oxide layer 112 over the doped material layer 108 and the first roughened germanium region 130. During this process, a third oxide layer 114 can be grown over the second roughened germanium region 132. Both oxide layers 112, 114 can comprise high quality oxides. High quality oxides are oxides of low interfacial density which are typically grown by thermal oxidation at temperatures above 900 degrees Celsius to provide improved passivation.

請參見第7圖,經沉積矽層104可因此被來自摻雜材料層108的摻雜材料109摻雜而形成經摻雜多晶矽層150。在一實施例中,可成長氧化物層並同時提高溫度以驅使摻雜劑109由摻雜材料層108進入經沉積矽層104以形成經摻雜多晶矽層,其中利用來自摻雜材料層108的摻雜劑109摻雜經沉積矽層104可形成結晶化的經摻雜多晶矽層或經摻雜多晶矽層150。在數種實施例之一者中,若使用正型摻雜材料,則經摻雜多晶矽層150可包含一層經正摻雜之多晶矽。在所示實施例中,矽基板102包含主體N型矽基板。在某些實施例中,若使用負型 摻雜材料,則經摻雜多晶矽層150包含一層經負摻雜之多晶矽。在一實施例中,矽基板102應包含主體P型矽基板。 Referring to FIG. 7, the deposited germanium layer 104 may thus be doped with dopant material 109 from the dopant material layer 108 to form a doped polysilicon layer 150. In one embodiment, the oxide layer can be grown while simultaneously increasing the temperature to drive dopants 109 from the dopant material layer 108 into the deposited germanium layer 104 to form a doped polysilicon layer, wherein the dopant layer 108 is utilized. The dopant 109 is doped to the deposited germanium layer 104 to form a crystallized doped polysilicon layer or doped polysilicon layer 150. In one of several embodiments, if a positive dopant material is used, the doped polysilicon layer 150 can comprise a layer of positively doped polysilicon. In the illustrated embodiment, the germanium substrate 102 comprises a body N-type germanium substrate. In some embodiments, if a negative type is used For the doped material, the doped polysilicon layer 150 comprises a layer of negatively doped polysilicon. In an embodiment, the germanium substrate 102 should comprise a body P-type germanium substrate.

請參見第8圖,可在太陽能電池100之背側上沉積第一寬能帶間隙經摻雜半導體層160。在一實施例中,第一寬能帶間隙經摻雜半導體層160係部分導電,且其電阻率為至少10歐姆-公分。在相同實施例中,其能帶間隙可大於1.05電子伏(eV),作為已由第一粗化矽區域130及第二氧化物層112覆蓋之太陽能電池的背側區域內之異質接面(heterojunction)。寬能帶間隙經摻雜半導體之實例包括碳化矽及氮化鋁鎵。也可以使用任何具有上述性質與特性的其他寬能帶間隙經摻雜半導體材料。第一寬能帶間隙經摻雜半導體層160可由第一厚寬能帶間隙經摻雜非晶矽層所組成。 Referring to FIG. 8, a first wide band gap doped semiconductor layer 160 may be deposited on the back side of the solar cell 100. In one embodiment, the first wide band gap is partially electrically conductive through the doped semiconductor layer 160 and has a resistivity of at least 10 ohm-cm. In the same embodiment, the band gap may be greater than 1.05 electron volts (eV) as a heterojunction in the backside region of the solar cell that has been covered by the first roughened germanium region 130 and the second oxide layer 112 ( Heterojunction). Examples of wide band gap doped semiconductors include tantalum carbide and aluminum gallium nitride. Any other wide band gap doped semiconductor material having the above properties and characteristics can also be used. The first wide band gap doped semiconductor layer 160 may be composed of a first thick wide band gap and a doped amorphous layer.

請參見第9圖,可於太陽能電池100之前側上的第二粗化矽區域132上方沉積第二寬能帶間隙經摻雜半導體層162。在一實施例中,太陽能電池100之背側與前側上的兩個寬能帶間隙經摻雜半導體層160、162均可包括寬能帶間隙經負型摻雜半導體。在另一實施例中,相較於第一厚寬能帶間隙經摻雜半導體層而言,第二寬能帶間隙經摻雜半導體層162可為相對薄。因此,在某些實施例中,第二薄寬能帶間隙經摻雜半導體層可包括第一厚寬能帶間隙經摻雜半導體層之10至30%的厚度。在又一實施例中,分別位於太陽能電池之背側與前側上的兩個寬能帶間隙經摻雜半導體層160、162可包括寬能帶間隙經負型摻雜半導體或寬能帶間隙經正型摻雜半導體。之後,可在相同製程中將抗反射塗層(anti-reflective coating,ARC)170沉積在第二寬能帶間隙經摻雜半導體層162上方。在另一實施例中,可在相同製程中將抗反射塗層170沉積在第一寬能帶間隙經摻雜半導體層160上方。在某些實施例中,抗反射塗層170可由氮化矽所組成。 Referring to FIG. 9, a second wide band gap doped semiconductor layer 162 may be deposited over the second roughened germanium region 132 on the front side of the solar cell 100. In one embodiment, the two wide band gap-doped semiconductor layers 160, 162 on the back side and the front side of the solar cell 100 may each comprise a wide band gap via a negatively doped semiconductor. In another embodiment, the second wide band gap via doped semiconductor layer 162 can be relatively thin compared to the first thick wide band gap via the doped semiconductor layer. Thus, in some embodiments, the second thin wide band gap doped semiconductor layer can comprise a thickness of 10 to 30% of the first thick wide band gap doped semiconductor layer. In yet another embodiment, the two wide band gap doped semiconductor layers 160, 162 respectively located on the back side and the front side of the solar cell may comprise a wide band gap via a negative doped semiconductor or a wide band gap Positive doped semiconductor. Thereafter, an anti-reflective coating (ARC) 170 may be deposited over the second wide band gap doped semiconductor layer 162 in the same process. In another embodiment, the anti-reflective coating 170 can be deposited over the first wide band gap over the doped semiconductor layer 160 in the same process. In some embodiments, the anti-reflective coating 170 can be comprised of tantalum nitride.

第10圖繪示太陽能電池100背側上的第一寬能帶間隙經摻雜半導體層160、摻雜材料層108及第二氧化物層112之部分移除,而形成一系列接觸開口180。在一實施例中,可利用剝蝕製程而達成該移除技術。一種此類剝蝕製程為雷射剝蝕製程。在另一實施例中,該移除技術可為任一種現有蝕刻製程,例如遮罩之噴墨印刷或網印,接著進行蝕刻製程。 FIG. 10 illustrates that the first wide band gap on the back side of the solar cell 100 is partially removed by the doped semiconductor layer 160, the doped material layer 108, and the second oxide layer 112 to form a series of contact openings 180. In an embodiment, the removal technique can be accomplished using an ablation process. One such ablation process is a laser ablation process. In another embodiment, the removal technique can be any existing etching process, such as inkjet printing or screen printing of a mask, followed by an etching process.

請參見第11圖,可在太陽能電池100之背側上形成第一金屬柵極或柵極線190。可在接觸開口180內將第一金屬柵極線190電性耦接至經摻雜多晶矽層150。在一實施例中,可將第一金屬柵極線190形成為穿過接觸開口180至第一寬能帶間隙經摻雜半導體層160、第二氧化物層112及摻雜材料層108,以連接由太陽能電池供電之外部電路的正電性端子。 Referring to FIG. 11, a first metal gate or gate line 190 can be formed on the back side of the solar cell 100. The first metal gate line 190 can be electrically coupled to the doped polysilicon layer 150 within the contact opening 180. In an embodiment, the first metal gate line 190 may be formed through the contact opening 180 to the first wide band gap-doped semiconductor layer 160, the second oxide layer 112, and the doped material layer 108 to A positive terminal that connects an external circuit powered by a solar cell.

請參見第12圖,可於太陽能電池100之背側上形成第二金屬柵極或柵極線192,第二金屬柵極線192係電性耦接至第二粗化矽區域132。在一實施例中,可將第二金屬柵極線192耦接至第一寬能帶間隙經摻雜半導體層160、第二氧化物層112及第一粗化矽區域130而作為太陽能電池背側區域內之異質接面,以連接由太陽能電池供電之外部電路的負電性端子。在某些實施例中,第11圖及第12圖中所示之金屬柵極線形成方法可由電鍍製程、網印製程、噴墨製程、鍍在由鋁金屬奈米粒子形成之金屬上或由任一種其他金屬化或金屬形成製程步驟所達成。 Referring to FIG. 12, a second metal gate or gate line 192 may be formed on the back side of the solar cell 100. The second metal gate line 192 is electrically coupled to the second roughened germanium region 132. In an embodiment, the second metal gate line 192 can be coupled to the first wide band gap doped semiconductor layer 160, the second oxide layer 112, and the first roughened germanium region 130 as a solar cell back. A heterojunction in the side region to connect the negative terminal of the external circuit powered by the solar cell. In some embodiments, the metal gate line forming method shown in FIGS. 11 and 12 may be performed by an electroplating process, a screen printing process, an inkjet process, plating on a metal formed of aluminum metal nanoparticles or by Any other metallization or metal forming process step is achieved.

第13圖至第18圖繪示製造太陽能電池200的另一實施例。除非以下另有指明,否則第13圖至第18圖中用以表示元件的元件標號與前述第1圖至第12圖中用以表示元件或技術特徵的元件標號相類似,差別處在於將標號加上100。 13 to 18 illustrate another embodiment of manufacturing the solar cell 200. Unless otherwise indicated below, the component numbers used to indicate the elements in FIGS. 13 to 18 are similar to those in the foregoing FIGS. 1 to 12 for indicating the elements or technical features, the difference being that the labels are Plus 100.

請參見第13圖至第14圖,用於製造太陽能電池200的另一實施例可包括在矽基板202上方形成第一氧化物層210、薄介電層206、經摻雜多晶矽層250。同前所述,可在形成薄介電層206之前先將矽基板202進行清潔、研磨、平面化及/或薄型化或其他處理。可利用熱製程成長第一氧化物層210、介電層206及經摻雜多晶矽層250。在一實施例中,藉由於含氧環境中加熱矽基板202,以在太陽能電池之背側上方成長矽氧化物層或氧化物層210,其中經摻雜矽層係經結晶化以形成經摻雜多晶矽層250。在另一實施例中,於介電層206上方成長經摻雜多晶矽層250之步驟包含成長經正摻雜之多晶矽,其中經正摻雜之多晶矽可由摻雜材料209所組成,例如硼摻雜劑。在另一實施例中,可使用經負摻雜之多晶矽。雖然薄介電層206及經摻雜多晶矽層250如前述係分別利用熱製程進行成長或利用現有沉積製程進行沉積,然如同本說明書所述或所引用之任一種其他形成、沉積或成長製程步驟一般,各層或物質亦可利用前述任一種適合的製程來形成。 Referring to FIGS. 13-14, another embodiment for fabricating solar cell 200 can include forming a first oxide layer 210, a thin dielectric layer 206, and a doped polysilicon layer 250 over the germanium substrate 202. As previously described, the tantalum substrate 202 can be cleaned, ground, planarized, and/or thinned or otherwise processed prior to forming the thin dielectric layer 206. The first oxide layer 210, the dielectric layer 206, and the doped polysilicon layer 250 may be grown using a thermal process. In one embodiment, by heating the germanium substrate 202 in an oxygen-containing environment, a germanium oxide layer or oxide layer 210 is grown over the back side of the solar cell, wherein the doped germanium layer is crystallized to form an admixed layer. A heteropolycrystalline layer 250. In another embodiment, the step of growing the doped polysilicon layer 250 over the dielectric layer 206 comprises growing a positively doped polysilicon, wherein the positively doped polysilicon can be composed of a dopant material 209, such as boron doping. Agent. In another embodiment, a negatively doped polysilicon can be used. Although the thin dielectric layer 206 and the doped polysilicon layer 250 are grown by a thermal process, respectively, or by an existing deposition process, as in any other formation, deposition, or growth process steps described or referenced herein. In general, the layers or materials may be formed using any of the suitable processes described above.

可部分移除第一氧化物層210、經摻雜多晶矽層250及介電層206來進一步處理太陽能電池200,藉此利用現有遮罩與蝕刻製程而以交指圖樣顯露矽基板的暴露區域220。在使用現有遮罩與蝕刻製程的情形中,可使用剝蝕製程。若是使用剝蝕製程,第一氧化物層210可部分完整保留於經摻雜多晶矽層250上方,如第14圖所示。在另一實施例中,可將網印或噴墨印刷技術搭配蝕刻製程使用。在此種實施例中,可從經摻雜多晶矽層250蝕刻去除第一氧化物層210。 The first oxide layer 210, the doped polysilicon layer 250, and the dielectric layer 206 may be partially removed to further process the solar cell 200, thereby exposing the exposed regions 220 of the germanium substrate in an interdigitated pattern using existing masking and etching processes. . In the case of using existing masking and etching processes, an ablation process can be used. If an ablation process is used, the first oxide layer 210 may remain partially intact over the doped polysilicon layer 250, as shown in FIG. In another embodiment, screen printing or ink jet printing techniques can be used in conjunction with an etching process. In such an embodiment, the first oxide layer 210 can be etched away from the doped polysilicon layer 250.

請參見第15圖,可同時蝕刻經暴露之矽基板220及太陽能電池200之前側上的暴露區域,以形成第一粗化矽區域230及第二粗化矽區域232,用以促進太陽輻射之收集。 Referring to FIG. 15, the exposed germanium substrate 220 and the exposed regions on the front side of the solar cell 200 can be simultaneously etched to form a first roughened germanium region 230 and a second roughened germanium region 232 for promoting solar radiation. collect.

請參見第16圖,可將太陽能電池200加熱240至高於攝氏900度之溫度,而在太陽能電池200之背側上形成第二氧化物層212並在前側上形成第三氧化物層214。在另一實施例中,兩個氧化物層212、214均可包括前述的高品質氧化物。 Referring to FIG. 16, the solar cell 200 can be heated 240 to a temperature higher than 900 degrees Celsius, while the second oxide layer 212 is formed on the back side of the solar cell 200 and the third oxide layer 214 is formed on the front side. In another embodiment, both oxide layers 212, 214 may comprise the aforementioned high quality oxide.

請參見第17圖,可在太陽能電池之背側及前側上同時沉積第一寬能帶間隙經摻雜半導體層260。第一寬能帶間隙經摻雜半導體層260可為部分導電,且其電阻率可大於10歐姆-公分。第一寬能帶間隙經摻雜半導體層260之能帶間隙亦可大於1.05eV。此外,第一寬能帶間隙半導體層可作為由第一粗化矽區域230及第二氧化物層212覆蓋之太陽能電池的背側區域內之異質接面。 Referring to FIG. 17, a first wide band gap doped semiconductor layer 260 may be simultaneously deposited on the back side and the front side of the solar cell. The first wide band gap may be partially conductive through the doped semiconductor layer 260 and may have a resistivity greater than 10 ohm-cm. The band gap of the first wide band gap via the doped semiconductor layer 260 may also be greater than 1.05 eV. In addition, the first wide band gap semiconductor layer can serve as a heterojunction in the back side region of the solar cell covered by the first roughened germanium region 230 and the second oxide layer 212.

第一寬能帶間隙經摻雜半導體層260可比第二寬能帶間隙經摻雜半導體層262厚10%至30%。在其他實施例中,厚度可變化為低於10%或高於30%而不脫離本說明書所述之技術。兩個寬能帶間隙經摻雜半導體層260、262皆可為經正摻雜之半導體,儘管在使用不同基板與多晶矽摻雜極性的其他實施例中,亦可使用經負摻雜之寬能帶間隙半導體層。之後可在第二寬能帶間隙經摻雜半導體層262上方沉積抗反射塗層(ARC)270。在一實施例中,抗反射塗層270可由氮化矽所組成。在某些實施例中,也可在第一寬能帶間隙經摻雜半導體層260上方沉積抗反射塗層。 The first wide band gap doped semiconductor layer 260 may be 10% to 30% thicker than the second wide band gap via the doped semiconductor layer 262. In other embodiments, the thickness can be varied to less than 10% or greater than 30% without departing from the techniques described herein. The two wide band gap doped semiconductor layers 260, 262 can be positively doped semiconductors, although in other embodiments using different substrates and polysilicon doping polarity, a negatively doped broad energy can also be used. A semiconductor layer with a gap. An anti-reflective coating (ARC) 270 can then be deposited over the doped semiconductor layer 262 over the second wide band gap. In an embodiment, the anti-reflective coating 270 can be composed of tantalum nitride. In some embodiments, an anti-reflective coating can also be deposited over the doped semiconductor layer 260 at a first wide band gap.

請參見第18圖,可在經摻雜多晶矽層250上方部分移除第一寬能帶間隙經摻雜半導體層260及第二氧化物層212,以形成一系列接觸開口,其係類似於前述第10圖至第12圖所示者並以類似技術達成。之後可在太陽能電池200之背側上形成第一金屬柵極線290,其中第一金屬柵極線290可於接觸開口內電性耦接至經摻雜多晶矽層250。可在太陽能電池200之背側上形成第二金屬柵極 線292,第二金屬柵極線292係電性耦接至第一粗化矽區域或N型射極區域230。在一實施例中,可同時形成第一及第二金屬柵極線。之後可由太陽能電池200之能量系統的其他元件來完成對第一及第二金屬柵極線290、292的額外接觸。 Referring to FIG. 18, a first wide band gap doped semiconductor layer 260 and a second oxide layer 212 may be partially removed over the doped polysilicon layer 250 to form a series of contact openings similar to the foregoing. Figures 10 through 12 are achieved with similar techniques. A first metal gate line 290 can then be formed on the back side of the solar cell 200, wherein the first metal gate line 290 can be electrically coupled to the doped polysilicon layer 250 within the contact opening. A second metal gate can be formed on the back side of the solar cell 200 The second metal gate line 292 is electrically coupled to the first roughened germanium region or the N-type emitter region 230. In an embodiment, the first and second metal gate lines can be formed simultaneously. Additional contact to the first and second metal gate lines 290, 292 can then be accomplished by other components of the energy system of the solar cell 200.

儘管已於前述實施方式中提出至少一例示性實施例,但應了解可存在大量的變化。同樣應了解的是,本說明書所述之例示性實施例或實施例並不欲用以透過任何方式限制所請求之申請標的之範圍、應用性或組態。相反地,前述實施方式將可提供本領域具有通常知識者一種簡便的指引以實施所述之一或多種實施例。應了解的是,可對元件之功能與排列進行各種變化,而不脫離申請專利範圍所界定的範圍內,且申請專利範圍包含已知的均等物及在本專利申請案提出申請時可預見的均等物。 While at least one exemplary embodiment has been presented in the foregoing embodiments, it will be appreciated that a number of variations can be present. It should be understood that the illustrative embodiments or embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed application. Rather, the foregoing embodiments are provided to provide a simple description of one or more embodiments. It will be appreciated that various changes can be made in the function and arrangement of the elements without departing from the scope of the invention, and the scope of the application includes the known equivalents and the foreseeable in the application of this patent application. Equal.

100‧‧‧太陽能電池 100‧‧‧ solar cells

102‧‧‧矽基板 102‧‧‧矽 substrate

104‧‧‧經沉澱矽層 104‧‧‧Secondary layer

106‧‧‧薄介電層 106‧‧‧thin dielectric layer

Claims (40)

一種用於製造太陽能電池之方法,該太陽能電池包含一矽基板,該矽基板具有一前側及相對該前側的一背側,該前側係設置為在正常操作期間面向太陽,且該方法包含:提供該矽基板,其具有一薄介電層於該背側上,以及一經沉積矽層於該薄介電層上方;於該經沉積矽層上方形成一摻雜材料層;於該摻雜材料層上方形成一氧化物層;以一交指圖樣部分移除該氧化物層、該摻雜材料層及該經沉積矽層;成長一氧化物層並同時提高溫度以驅使一摻雜劑由該摻雜材料層進入該經沉積矽層;利用來自該摻雜材料層的該摻雜劑對該經沉積矽層進行摻雜,以形成一結晶化經摻雜多晶矽層;於該太陽能電池之該背側上沉積一寬能帶間隙經摻雜半導體及一抗反射塗層;以及於該太陽能電池之該前側上沉積一寬能帶間隙經摻雜半導體及該抗反射塗層。 A method for fabricating a solar cell, the solar cell comprising a substrate having a front side and a back side opposite the front side, the front side being configured to face the sun during normal operation, and the method comprising: providing The germanium substrate has a thin dielectric layer on the back side, and a deposited germanium layer over the thin dielectric layer; a doped material layer is formed over the deposited germanium layer; Forming an oxide layer thereon; partially removing the oxide layer, the doping material layer and the deposited germanium layer in an interdigitated pattern; growing an oxide layer while increasing temperature to drive a dopant from the doping a layer of impurity material enters the deposited germanium layer; the deposited germanium layer is doped with the dopant from the dopant material layer to form a crystallized doped polysilicon layer; the back of the solar cell A wide band gap is doped on the side of the doped semiconductor and an anti-reflective coating; and a wide band gap doped semiconductor and the anti-reflective coating are deposited on the front side of the solar cell. 如申請專利範圍第1項所述之方法,其中提供該矽基板之步驟包含提供一具有N型主體矽之矽基板。 The method of claim 1, wherein the step of providing the germanium substrate comprises providing a germanium substrate having an N-type body. 如申請專利範圍第1項所述之方法,其中提供該矽基 板之步驟包含提供一具有P型主體矽之矽基板。 The method of claim 1, wherein the sulfhydryl group is provided The step of the board includes providing a germanium substrate having a P-type body. 如申請專利範圍第1項所述之方法,其中於該經沉積矽層上方形成該摻雜材料層之步驟包含於該經沉積矽層上方形成一正型摻雜材料層。 The method of claim 1, wherein the step of forming the doped material layer over the deposited germanium layer comprises forming a positive doped material layer over the deposited germanium layer. 如申請專利範圍第1項所述之方法,其中於該經沉積矽層上方形成該摻雜材料層之步驟包含於該經沉積矽層上方形成一負型摻雜材料層。 The method of claim 1, wherein the step of forming the doped material layer over the deposited germanium layer comprises forming a negative doped material layer over the deposited germanium layer. 如申請專利範圍第1項所述之方法,其中沉積該寬能帶間隙經摻雜半導體之步驟包含沉積一寬能帶間隙經摻雜非晶矽。 The method of claim 1, wherein the step of depositing the wide band gap through the doped semiconductor comprises depositing a broad band gap doped amorphous germanium. 如申請專利範圍第1項所述之方法,其中沉積該寬能帶間隙經摻雜半導體之步驟包含沉積能帶間隙大於1.05電子伏之一半導體。 The method of claim 1, wherein the step of depositing the broad band gap through the doped semiconductor comprises depositing a semiconductor having a band gap greater than 1.05 electron volts. 如申請專利範圍第1項所述之方法,其中以該交指圖樣部分移除該氧化物層、該摻雜材料層及該經沉積矽層之步驟包含使用一蝕刻製程以移除該氧化物層、該摻雜材料層及該經沉積矽層。 The method of claim 1, wherein the step of partially removing the oxide layer, the doped material layer, and the deposited germanium layer in the interdigitated pattern comprises using an etching process to remove the oxide a layer, the doped material layer, and the deposited tantalum layer. 如申請專利範圍第1項所述之方法,其中以該交指圖樣部分移除該氧化物層、該摻雜材料層及該經沉積矽層之步驟包含使用一剝蝕製程以移除該氧化物層、該摻雜材料層及該經沉積矽層。 The method of claim 1, wherein the step of partially removing the oxide layer, the dopant material layer and the deposited germanium layer in the interdigitated pattern comprises using an ablation process to remove the oxide a layer, the doped material layer, and the deposited tantalum layer. 如申請專利範圍第1項所述之方法,其中於該太陽能電池之該前側上沉積該抗反射塗層之步驟包含沉積 氮化矽。 The method of claim 1, wherein the step of depositing the anti-reflective coating on the front side of the solar cell comprises depositing Tantalum nitride. 如申請專利範圍第1項所述之方法,其中於該太陽能電池之該背側上沉積該寬能帶間隙經摻雜半導體之步驟包含沉積一部分導電之寬能帶間隙經摻雜半導體,其具有大於10歐姆-厘米之典型電阻率。 The method of claim 1, wherein the step of depositing the wide band gap on the back side of the solar cell by doping a semiconductor comprises depositing a portion of a conductive wide band gap doped semiconductor having Typical resistivity greater than 10 ohm-cm. 如申請專利範圍第1項所述之方法,其中於該太陽能電池之該背側與該前側上沉積該寬能帶間隙經摻雜半導體之步驟包含沉積一寬能帶間隙經負型摻雜半導體。 The method of claim 1, wherein the step of depositing the wide band gap on the back side and the front side of the solar cell by doping a semiconductor comprises depositing a wide band gap via a negative doped semiconductor . 如申請專利範圍第1項所述之方法,其中於該太陽能電池之該背側與該前側上沉積該寬能帶間隙經摻雜半導體之步驟包含沉積一寬能帶間隙經正型摻雜半導體。 The method of claim 1, wherein the step of depositing the wide band gap on the back side and the front side of the solar cell by doping a semiconductor comprises depositing a broad band gap via a positive doped semiconductor . 如申請專利範圍第1項所述之方法,其中以該交指圖樣部分移除該氧化物層、該摻雜材料層及該經沉積矽層之步驟更包括隨後蝕刻暴露之矽基板以形成一粗化矽區域。 The method of claim 1, wherein the step of partially removing the oxide layer, the doped material layer and the deposited germanium layer in the interdigitated pattern further comprises subsequently etching the exposed germanium substrate to form a The roughened area is roughened. 如申請專利範圍第1項所述之方法,其進一步包含部分移除該太陽能電池之該背側上的該寬能帶間隙經摻雜半導體、該氧化物層及該摻雜材料層,以形成一系列接觸開口。 The method of claim 1, further comprising partially removing the wide band gap-doped semiconductor, the oxide layer and the doped material layer on the back side of the solar cell to form A series of contact openings. 如申請專利範圍第15項所述之方法,其進一步包含於該太陽能電池之該背側上形成一第一金屬柵極,該第一金屬柵極係於穿過該寬能帶間隙經摻雜半導體、 該氧化物層及該摻雜材料層之該一系列接觸開口內電性耦接至該結晶化經摻雜多晶矽層。 The method of claim 15, further comprising forming a first metal gate on the back side of the solar cell, the first metal gate being doped through the wide band gap semiconductor, The oxide layer and the series of contact openings of the dopant material layer are electrically coupled to the crystallized doped polysilicon layer. 如申請專利範圍第16項所述之方法,其中於該太陽能電池之該背側上形成該第一金屬柵極之步驟包含形成一包含鋁之第一金屬柵極。 The method of claim 16, wherein the step of forming the first metal gate on the back side of the solar cell comprises forming a first metal gate comprising aluminum. 如申請專利範圍第17項所述之方法,其進一步包含於該太陽能電池之該背側上形成一第二金屬柵極,該第二金屬柵極係電性耦接至一部分該交指圖樣。 The method of claim 17, further comprising forming a second metal gate on the back side of the solar cell, the second metal gate being electrically coupled to a portion of the interdigitated pattern. 一種用於製造太陽能電池之方法,該太陽能電池包含一矽基板,該矽基板具有一前側及相對該前側的一背側,該前側係設置為在正常操作期間面向太陽,且該方法包含:提供該矽基板,其具有一薄介電層於該背側上、以及一經沉積矽層於該薄介電層上方;於該經沉積矽層上方形成一摻雜材料層;於該摻雜材料層上方形成一氧化物層;以一交指圖樣部分移除該氧化物層、該摻雜材料層及該經沉積矽層;蝕刻所暴露之矽基板以形成一粗化矽區域;成長一氧化物層並同時提高溫度以驅使摻雜劑由該摻雜材料層進入該經沉積矽層;利用來自該摻雜材料層的摻雜劑對該經沉積矽層進行摻雜,以形成一結晶化經摻雜多晶矽層; 於該太陽能電池之該背側上覆蓋一寬能帶間隙經摻雜非晶矽之一第一厚層及一抗反射塗層;以及於該太陽能電池之該前側上覆蓋一寬能帶間隙經摻雜非晶矽之一第二薄層及該抗反射塗層;其中該薄層小於該厚層厚度之30%。 A method for fabricating a solar cell, the solar cell comprising a substrate having a front side and a back side opposite the front side, the front side being configured to face the sun during normal operation, and the method comprising: providing The germanium substrate has a thin dielectric layer on the back side and a deposited germanium layer over the thin dielectric layer; a doped material layer is formed over the deposited germanium layer; Forming an oxide layer thereon; partially removing the oxide layer, the doping material layer and the deposited germanium layer in an interdigitated pattern; etching the exposed germanium substrate to form a roughened germanium region; growing an oxide And simultaneously increasing the temperature to drive the dopant from the dopant material layer into the deposited germanium layer; doping the deposited germanium layer with a dopant from the dopant material layer to form a crystallized Doped polysilicon layer; And covering the back side of the solar cell with a first thick layer of a wide band gap doped amorphous germanium and an anti-reflective coating; and covering the front side of the solar cell with a wide band gap a second thin layer of doped amorphous germanium and the anti-reflective coating; wherein the thin layer is less than 30% of the thickness of the thick layer. 如申請專利範圍第19項所述之方法,其中該薄層為該厚層厚度之10%。 The method of claim 19, wherein the thin layer is 10% of the thickness of the thick layer. 一種用於製造太陽能電池之方法,該太陽能電池包含一矽基板,該矽基板具有一前側及相對該前側的一背側,該前側係設置為在正常操作期間面向太陽,且該方法包含:提供該矽基板,其具有一薄介電層於該背側上、以及一經摻雜矽層於該薄介電層上方;於該經摻雜矽層上方形成一氧化物層;以一交指圖樣部分移除該氧化物層及該經摻雜矽層;蝕刻暴露之矽基板以形成一粗化矽區域;藉由於一含氧環境中加熱該矽基板,以在該太陽能電池之該背側上方成長一矽氧化物層,其中該經摻雜矽層係經結晶化以形成一經摻雜多晶矽層;於該太陽能電池之該前側與該背側上方同時沉積一寬能帶間隙經摻雜非晶矽及一抗反射塗層; 部分移除該抗反射塗層、該寬能帶間隙經摻雜非晶矽及該氧化物層,以形成一系列接觸開口;以及於該太陽能電池之該背側上同時形成一第一金屬柵極及一第二金屬柵極,該第一金屬柵極係電性耦接至該經摻雜多晶矽,該第二金屬柵極係電性耦接至的一部分該交指圖樣。 A method for fabricating a solar cell, the solar cell comprising a substrate having a front side and a back side opposite the front side, the front side being configured to face the sun during normal operation, and the method comprising: providing The germanium substrate has a thin dielectric layer on the back side and a doped germanium layer over the thin dielectric layer; an oxide layer is formed over the doped germanium layer; Partially removing the oxide layer and the doped germanium layer; etching the exposed germanium substrate to form a roughened germanium region; by heating the germanium substrate in an oxygen-containing environment to be above the back side of the solar cell Growing a layer of oxide, wherein the doped layer is crystallized to form a doped polysilicon layer; and a broad band gap is doped amorphous on the front side and the back side of the solar cell矽 and an anti-reflective coating; Partially removing the anti-reflective coating, the wide band gap-doped amorphous germanium and the oxide layer to form a series of contact openings; and simultaneously forming a first metal gate on the back side of the solar cell And a second metal gate electrically coupled to the doped polysilicon, the second metal gate being electrically coupled to a portion of the interdigitated pattern. 如申請專利範圍第21項所述之方法,其中該經摻雜多晶矽層包括一經負摻雜之多晶矽層。 The method of claim 21, wherein the doped polysilicon layer comprises a negatively doped polysilicon layer. 如申請專利範圍第21項所述之方法,其中該經摻雜.多晶矽層包括一經正摻雜之多晶矽層。 The method of claim 21, wherein the doped polysilicon layer comprises a positively doped polysilicon layer. 如申請專利範圍第21項所述之方法,其中於該太陽能電池之該前側與該背側上方沉積該抗反射塗層之步驟包含於該太陽能電池之該背側與該前側上沉積氮化矽。 The method of claim 21, wherein the step of depositing the anti-reflective coating on the front side and the back side of the solar cell comprises depositing tantalum nitride on the back side and the front side of the solar cell. . 一種用於製造太陽能電池之方法,該太陽能電池包含一矽基板,該矽基板具有一前側及相對該前側的一背側,該前側係設置為在正常操作期間面向太陽,且該方法包含:提供該矽基板,其具有一薄介電層於該背側上、以及一經摻雜矽層於該薄介電層上方;於該經摻雜矽層上方形成一氧化物層;以一交指圖樣部分移除該氧化物層及該經摻雜矽層;蝕刻暴露之矽基板以形成一粗化矽區域; 藉由於一含氧環境中加熱該矽基板,以在該太陽能電池之該背側上方成長一矽氧化物層,其中該經摻雜矽層係經結晶化以形成一經摻雜多晶矽層;於該太陽能電池之該背側上沉積一寬能帶間隙經摻雜非晶矽及一抗反射塗層;以及於該太陽能電池之該前側上沉積一寬能帶間隙經摻雜非晶矽及該抗反射塗層。 A method for fabricating a solar cell, the solar cell comprising a substrate having a front side and a back side opposite the front side, the front side being configured to face the sun during normal operation, and the method comprising: providing The germanium substrate has a thin dielectric layer on the back side and a doped germanium layer over the thin dielectric layer; an oxide layer is formed over the doped germanium layer; Partially removing the oxide layer and the doped germanium layer; etching the exposed germanium substrate to form a roughened germanium region; Heating the germanium substrate in an oxygen-containing environment to grow an oxide layer over the back side of the solar cell, wherein the doped germanium layer is crystallized to form a doped polysilicon layer; Depositing a broad band gap-doped amorphous germanium and an anti-reflective coating on the back side of the solar cell; and depositing a broad band gap doped amorphous germanium on the front side of the solar cell and the anti-reflection Reflective coating. 如申請專利範圍第25項所述之方法,其中該經摻雜多晶矽層包含磷。 The method of claim 25, wherein the doped polysilicon layer comprises phosphorus. 如申請專利範圍第25項所述之方法,其中該經摻雜多晶矽層包含硼。 The method of claim 25, wherein the doped polysilicon layer comprises boron. 一種用於製造太陽能電池之方法,該太陽能電池包含一矽基板,該矽基板具有一前側及相對該前側的一背側,該前側係設置為在正常操作期間面向太陽,且該方法包含:提供該矽基板,其具有一薄介電層於該背側上、以及一經摻雜矽層於該薄介電層上方;於該經摻雜矽層上方形成一氧化物層;以一交指圖樣部分移除該氧化物層及該經摻雜矽層;藉由於一含氧環境中加熱該矽基板,以在該太陽能電池之該背側上方成長一矽氧化物層,其中該經摻雜矽層係經結晶化以形成一經摻雜多晶矽層; 於該太陽能電池之該背側上沉積一寬能帶間隙經摻雜半導體;以及於該太陽能電池之該前側上沉積一寬能帶間隙經摻雜半導體及一抗反射塗層。 A method for fabricating a solar cell, the solar cell comprising a substrate having a front side and a back side opposite the front side, the front side being configured to face the sun during normal operation, and the method comprising: providing The germanium substrate has a thin dielectric layer on the back side and a doped germanium layer over the thin dielectric layer; an oxide layer is formed over the doped germanium layer; Partially removing the oxide layer and the doped germanium layer; by heating the germanium substrate in an oxygen-containing environment to grow an oxide layer over the back side of the solar cell, wherein the germanium oxide layer is doped The layer is crystallized to form a doped polysilicon layer; Depositing a broad band gap-doped semiconductor on the back side of the solar cell; and depositing a broad band gap doped semiconductor and an anti-reflective coating on the front side of the solar cell. 如申請專利範圍第28項所述之方法,其中提供該矽基板之步驟包含提供一具有N型主體矽之矽基板。 The method of claim 28, wherein the step of providing the germanium substrate comprises providing a germanium substrate having an N-type body. 如申請專利範圍第28項所述之方法,其中提供該矽基板之步驟包含提供一具有P型主體矽之矽基板。 The method of claim 28, wherein the step of providing the germanium substrate comprises providing a germanium substrate having a P-type body. 如申請專利範圍第28項所述之方法,其中以該交指圖樣部分移除該氧化物層及該經摻雜矽層而顯露該矽基板之一暴露區域的步驟包含使用一蝕刻製程以移除該氧化物層及該經摻雜矽層。 The method of claim 28, wherein the step of removing the oxide layer and the doped germanium layer by the interdigitated pattern to expose an exposed region of the germanium substrate comprises using an etching process to shift The oxide layer and the doped germanium layer are removed. 如申請專利範圍第28項所述之方法,其中以該交指圖樣部分移除該氧化物層及該經摻雜矽層而顯露該矽基板之一暴露區域的步驟包含使用一剝蝕製程以移除該氧化物層及該經摻雜矽層。 The method of claim 28, wherein the step of removing the oxide layer and the doped germanium layer by the interdigitated pattern to expose an exposed region of the germanium substrate comprises using an ablation process to remove The oxide layer and the doped germanium layer are removed. 如申請專利範圍第28項所述之方法,其中沉積該寬能帶間隙經摻雜半導體之步驟包含沉積一寬能帶間隙經摻雜非晶矽。 The method of claim 28, wherein the step of depositing the broad band gap through the doped semiconductor comprises depositing a broad band gap doped amorphous germanium. 如申請專利範圍第28項所述之方法,其中沉積該寬能帶間隙經摻雜半導體之步驟包含沉積能帶間隙大於1.05電子伏之一半導體。 The method of claim 28, wherein the step of depositing the broad band gap through the doped semiconductor comprises depositing a semiconductor having a band gap greater than 1.05 electron volts. 如申請專利範圍第28項所述之方法,其中該於該太 陽能電池之該前側上沉積該抗反射塗層之步驟包括於該太陽能電池之該前側上沉積氮化矽。 The method of claim 28, wherein the method is The step of depositing the anti-reflective coating on the front side of the solar cell includes depositing tantalum nitride on the front side of the solar cell. 如申請專利範圍第28項所述之方法,其中以該交指圖樣部分移除該氧化物層及該經摻雜矽層之步驟更包括隨後蝕刻暴露之矽基板以形成一粗化矽區域。 The method of claim 28, wherein the step of partially removing the oxide layer and the doped germanium layer in the interdigitated pattern further comprises subsequently etching the exposed germanium substrate to form a roughened germanium region. 如申請專利範圍第28項所述之方法,其進一步包含部分移除該太陽能電池之該背側上的該寬能帶間隙經摻雜半導體、該氧化物層及該經摻雜多晶矽層,以形成一系列接觸開口。 The method of claim 28, further comprising partially removing the wide bandgap-doped semiconductor, the oxide layer, and the doped polysilicon layer on the back side of the solar cell to A series of contact openings are formed. 如申請專利範圍第37項所述之方法,其進一步包含於該太陽能電池之該背側上形成一第一金屬柵極,該第一金屬柵極係於穿過該寬能帶間隙經摻雜半導體及該氧化物層之該一系列接觸開口內電性耦接至該經摻雜多晶矽層。 The method of claim 37, further comprising forming a first metal gate on the back side of the solar cell, the first metal gate being doped through the wide band gap The semiconductor and the series of contact openings of the oxide layer are electrically coupled to the doped polysilicon layer. 如申請專利範圍第38項所述之方法,其進一步包含於該太陽能電池之該背側上形成一第二金屬柵極,該第二金屬柵極係電性耦接至一部分該交指圖樣。 The method of claim 38, further comprising forming a second metal gate on the back side of the solar cell, the second metal gate being electrically coupled to a portion of the interdigitated pattern. 如申請專利範圍第39項所述之方法,其中於該太陽能電池之該背側上形成該第一金屬柵極及該第二金屬柵極之步驟包括同時形成該第一金屬柵極及該第二金屬柵極。 The method of claim 39, wherein the step of forming the first metal gate and the second metal gate on the back side of the solar cell comprises simultaneously forming the first metal gate and the first Two metal gates.
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