TWI555165B - Semiconductor package and its manufacturing method - Google Patents

Description

Semiconductor package and its manufacturing method

The present invention relates to a semiconductor package, and more particularly to a semiconductor package of a three-dimensional stacked wafer (3D IC).

With the rapid development of the electronics industry, electronic products tend to be light, thin and short in terms of type, and gradually become a high-performance, high-function, high-speed research and development direction in terms of functions. In order to meet the needs of multi-functionality, there are more and more electronic components in electronic products, and it is also necessary to meet the demand for miniaturization, and to develop a technology of three-dimensional stacked chips (3D ICs).

The 3D IC system vertically integrates a plurality of wafers into a three-dimensional space to achieve miniaturization. The difference from the general two-dimensional plane integration is that the 3D IC system utilizes the upper and lower conduction structures to greatly shorten the line length between the wafers, thereby improving the wafer performance.

Please refer to FIG. 1A, which is a schematic diagram of a conventional semiconductor package 1. As shown in FIG. 1A, the semiconductor package 1 includes a substrate 14 , an interposer 12 bonded to the substrate 14 , and a plurality of semiconductor wafers 11 bonded to the interposer 12 . A first primer 13 between the semiconductor wafer 11 and the interposer 12, and a second primer 15 formed between the interposer 12 and the substrate 14.

However, in the conventional semiconductor package 1, the material of the substrate 14 is generally a high molecular polymer, and the material of the interposer 12 is tantalum or glass, so the coefficient of thermal expansion of the substrate 14 and the interposer 12 (Coefficient of thermal Expansion, CTE) often fails to match, resulting in solder bumps 120 for the flip chip process having non-wetting, and the overall structure is prone to warpage.

US Patent No. 2010/0213600 also discloses a semiconductor package 1'. As shown in FIG. 1B, the semiconductor package 1' includes: an interposer 12' on a substrate 14', and a flip chip bond. a plurality of semiconductor wafers 11' on the interposer 12', a heat dissipation structure 10 bonded to the semiconductor wafers 11', a first primer 13 formed between the semiconductor wafer 11' and the interposer 12', And a second primer 15 formed between the interposer 12' and the substrate 14'. The substrate 14' has a supporting structure 140 for connecting the heat dissipating structure 10, and a plurality of semiconductor elements 16 are disposed on the lower side of the interposer 12', and the substrate 14' has an opening 142 for accommodating the semiconductor elements. 16.

However, in the conventional semiconductor package 1', the design of the heat dissipation structure 10 and the support structure 140 can reduce the risk of warpage of the overall structure, but the substrate 14' has an opening 142, so that the substrate 14' The stress concentrates toward the opening 142, causing the overall structure to easily break above the opening 142.

Therefore, how to overcome various problems of the prior art is an important issue.

In order to overcome the problems of the prior art, the present invention provides a semiconductor package, comprising: a substrate, an interposer disposed on the substrate, a first electronic component disposed on the interposer, coupled to the first electronic a carrier on the component, a first primer formed between the carrier and the interposer, and a second primer formed between the interposer and the substrate.

The invention provides a method for fabricating a semiconductor package, comprising: bonding a first electronic component on a carrier; and further bonding an intermediate layer having an opposite first surface and a second surface to the first surface thereof Forming a first primer between the carrier and the first surface of the interposer; forming a conductive element on the second surface of the interposer; and the interposer by the conductive element Attached to the substrate; and forming a second primer between the second surface of the interposer and the substrate to encapsulate the conductive element.

In the foregoing semiconductor package and the method of manufacturing the same, the interposer may be a perforated substrate or a glass perforated substrate, and a second electronic component may be disposed on the second surface of the interposer, such that the second primer covers the second electron element. Yet the substrate can have a thermal pad to bond the second electronic component.

In the foregoing semiconductor package and method of manufacturing the same, the first electronic component is an active component, a passive component, a memory, an integrated passive component, a radio frequency module, a microelectromechanical component or a package structure, and the second electronic component is active Component, passive component, microelectromechanical component or package structure.

In the foregoing semiconductor package and the method of manufacturing the same, the carrier may be a heat dissipation structure, so that the first electronic component can be adhered to the heat dissipation structure by a heat dissipating adhesive or a thermal interface material. Again, the carrier can have a barrier to control the extent of the first primer.

In addition, in the foregoing semiconductor package and the method of manufacturing the same, the side of the first primer may be tapered from the carrier to the first surface of the interposer.

It can be seen from the above that in the semiconductor package of the present invention and the manufacturing method thereof, the carrier is designed to overcome the non-sticking of the bump caused by the incompatibility between the substrate and the interposer (CTE). -wetting) is missing, and warpage of the overall structure can be avoided.

Furthermore, the substrate of the present invention has no opening at the second surface corresponding to the interposer as compared with the substrate opening of the prior art, so that the stress of the substrate is evenly dispersed, so that the overall structure does not break.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "upper", "lower" and "one" are used in the description for convenience of description, and are not intended to limit the scope of the invention, and the relative relationship may be changed or Adjustments, where there is no material change, are considered to be within the scope of the invention.

Please refer to FIGS. 2A to 2C for the fabrication of a semiconductor package 2 of the present invention.

As shown in FIG. 2A, a carrier 20 is provided, and the plurality of first electronic components 21 are bonded to the carrier 20 by the adhesive material 200, and the plurality of conductive components 210 are disposed on the first electronic component 21, and the conductive The component 210 can be a conductive bump such as a tin-lead bump, a lead-free bump, a conductive copper pillar, or other material having the same effect.

In this embodiment, the carrier 20 can be a heat sink, and the adhesive material 200 is a thermal adhesive or thermal interface material (TIM). The adhesive has good thermal conductivity and can be used for the first electronic The thermal energy generated by the component 21 is conducted to the carrier 20 via the thermally conductive material and then dissipated into the surrounding environment via the carrier.

Furthermore, the first electronic component 21 can be an active component, a passive component, a memory, an integrated passive device (IPD), a radio frequency (RF) module, or a microelectromechanical device. Mechanical Systems, MEMS) components or package structures.

Moreover, the carrier 20 is provided with a bank 201.

As shown in FIG. 2B, an interposer 22 having an opposite first surface 22a and a second surface 22b is provided, and the first surface 22a of the interposer 22 is bonded to the conductive element 210 of the first electronic component 21. . In another embodiment, the first electronic component 21 can also be connected to the interposer 22 through a film (not shown). The film can be an anisotropic conductive film (ACF) or a ring. An epoxy film.

Next, a first primer 23 is formed between the carrier 20 and the first surface 22a of the interposer 22 to cover the solder ball conductive elements 210, the first electronic component 21, and the side surface 21c thereof. A plurality of conductive elements 220 are formed on the second surface 22b of the interposer 22.

In this embodiment, the conductive element 220 can be a solder ball, a solder pin, or other substance having the same effect. In other embodiments, the first electronic component 21 is electrically connected to the interposer 22 via an anisotropic conductive paste (ACF), and the first primer 23 covers only a portion of the interposer 22 and the first electronic component. The side surface 21c of 21 does not cover the upper and lower surfaces of the first electronic component 21.

Furthermore, the interposer 22 is a tantalum perforated substrate or a glass perforated substrate, which is commonly known as a through silicon interposer (TSI) having a plurality of through silicon vias and a repeating wiring layer thereon. In other embodiments, the interposer 22 can also be a functional wafer, and can integrate different functional wafers in the same package.

Moreover, the bank 201 of the carrier 20 is used to control the range of the first primer 23, and the side of the first primer 23 is tapered by the carrier 20 toward the first surface 22a of the interposer 22. .

As shown in FIG. 2C, the conductive member 220 of the interposer 22 is attached to the upper surface 24a of a substrate 24. In this embodiment, the substrate 24 has a support structure 240 for attaching the interposer 22, and the substrate 24 has no opening at the second surface 22b corresponding to the interposer 22.

Next, a second primer 25 is formed between the second surface 22b of the interposer 22 and the upper surface 24a of the substrate 24 to cover the conductive elements 220.

In this embodiment, the substrate 24 is a general circuit board, and the material thereof can be ceramics, glass fiber, and the like, and therefore will not be described again. In addition, the support structure 240 can be an annular body or a plurality of columnar bodies adhered between the substrate 24 and the carrier 20, and the lower surface 24b of the substrate 24 can be implanted with a plurality of conductive elements (such as pins). ), solder balls, etc. 241 to connect an electronic device such as a circuit board (not shown).

Please refer to FIGS. 3 and 4 for a schematic view of semiconductor packages 3, 4 according to other aspects of the present invention. As shown in FIGS. 3 and 4, second electronic components 26, 27 may be disposed on the second surface 22b of the interposer 22, and the second primer 25 covers the second electronic components 26, 27.

The second electronic component 26, 27 is an active component (as shown in FIG. 3), a passive component (as shown in FIG. 4) or a package structure (as shown in FIG. 3), and a microelectromechanical component.

The interposer 22 is, for example, a transistor, a diode, a capacitor, an inductor, a resistor, a filter, a chip with a Redistribution Layer (RDL), a wafer with a specific function, such as a graphics processor (Graphics) Processing Unit (GPU), Central Processing Unit (CPU), Micro Controller Unit (MCU), and Integrated Passive Devices (IPDs).

In addition, as shown in FIG. 3, the upper surface 24a of the substrate 24 is provided with a heat dissipation pad 242 for bonding the second electronic component 26 by the adhesive material 260. The surface of the heat dissipation pad 242 may be plated with a nickel-palladium gold (Ni/Pd/Au) layer (not shown), and the adhesive material 260 is a heat-dissipating glue, a thermal interface material (TIM) or a heat-dissipating film.

In the manufacturing method of the semiconductor package 2, 3, and 4 of the present invention, the carrier 20 and the bank 201 are designed to overcome the conduction caused by the incompatibility of the thermal expansion coefficient (CTE) of the substrate 24 and the interposer 22. The element 220 is missing from non-wetting and can avoid warping of the overall structure.

Furthermore, since the substrate 24 of the present invention has no opening at the second surface 22b corresponding to the interposer 22, the stress of the substrate 24 is evenly dispersed, so that the overall structure does not break.

Moreover, the first primer 23 of the present invention is formed between the carrier 20 and the first surface 22a of the interposer 22 to cover the side surfaces 21c of the first electronic components 21, so The method of manufacturing the uncoated semiconductor wafer side surface, the fixing force of the first electronic component 21 of the present invention is increased, thereby improving the reliability of the overall structure.

The present invention provides a semiconductor package 2, 3, 4, comprising: a substrate 24, an interposer 22 disposed on the substrate 24, and a plurality of first electronic components 21 disposed on the interposer 22, coupled to a carrier 20 on the first electronic component 21, a first primer 23 formed between the carrier 20 and the interposer 22, and a second between the interposer 22 and the substrate 24. Primer 25.

The interposer 22 is a perforated substrate or a glass perforated substrate and has a first surface 22a and a second surface 22b opposite thereto, and the second surface 22b has a plurality of conductive elements 220 thereon. The interposer 22 is placed on the substrate 24, and the substrate 24 has no opening at the second surface 22b corresponding to the interposer 22.

The first electronic component 21 is bonded to the first surface 22a of the interposer 22 by flip chip bonding, and the carrier 20 is adhered by the adhesive material 200.

The carrier 20 is a heat dissipation structure and has a dam 201 to control the range of the first primer 23 .

The first primer 23 is formed between the carrier 20 and the first surface 22a of the interposer 22 to cover the first electronic component 21 and its side surface 21c.

The second primer 25 is formed between the second surface 22b of the interposer 22 and the substrate 24 to cover the conductive elements 220.

In another embodiment, the second surface 22b of the interposer 22 is provided with second electronic components 26, 27, and the second primer 25 covers the second electronic components 26, 27. The second electronic component 26, 27 is an active component, a passive component, a microelectromechanical component or a package structure, and the substrate 24 has a heat dissipation pad 242 for bonding the second electronic component 26, 27.

In summary, the semiconductor package of the present invention and the manufacturing method thereof are designed by the carrier and the bank to avoid the occurrence of warpage of the bump and the entire structure.

Furthermore, since the substrate of the present invention does not have an opening at the corresponding interposer, the stress of the substrate is evenly dispersed, so that the overall structure does not break.

Moreover, the first primer of the present invention is formed between the carrier and the interposer to cover the side surfaces of the semiconductor wafers, thereby increasing the adhesion of the semiconductor wafer, thereby improving the reliability of the overall structure.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

1,1’,2,3,4. . . Semiconductor package

10. . . Heat dissipation structure

11,11’. . . Semiconductor wafer

12,12’,22. . . Intermediary layer

120. . . Solder bump

13,23. . . First primer

14,14’, 24. . . Substrate

140,240. . . supporting structure

142. . . Opening

15,25. . . Second primer

16. . . Semiconductor component

20. . . Carrier

200,260. . . Adhesive

201. . . Barrier

twenty one. . . First electronic component

21c. . . Side surface

210,220,241. . . Conductive component

22a. . . First surface

22b. . . Second surface

24a. . . Upper surface

24b. . . lower surface

242. . . Cooling pad

26,27. . . Second electronic component

1A and 1B are schematic cross-sectional views showing a method of fabricating a conventional semiconductor package;

2A to 2C are schematic cross-sectional views showing an embodiment of a method of fabricating a semiconductor package of the present invention;

3 and 4 are cross-sectional views showing other embodiments of the semiconductor package of the present invention.

2. . . Semiconductor package

20. . . Carrier

201. . . Barrier

twenty one. . . First electronic component

21c. . . Side surface

twenty two. . . Intermediary layer

22a. . . First surface

22b. . . Second surface

220,241. . . Conductive component

twenty three. . . First primer

twenty four. . . Substrate

24a. . . Upper surface

24b. . . lower surface

240. . . supporting structure

25. . . Second primer

Claims (6)

A method of fabricating a semiconductor package, comprising: bonding a first electronic component on a carrier; and then, an interposer having an opposite first surface and a second surface, coupled to the first surface by the first surface The electronic component is disposed between the carrier and the first surface of the interposer; forming a first primer between the carrier and the first surface of the interposer to encapsulate the first An electronic component and a side surface thereof; forming a conductive component on the second surface of the interposer; attaching the interposer to the substrate by the conductive component; and forming a second primer on the second surface of the interposer The conductive member is coated with the substrate. The method of fabricating a semiconductor package according to claim 1, wherein the interposer is a tantalum perforated substrate or a glass perforated substrate. The method of fabricating a semiconductor package according to claim 1, wherein the carrier is a heat dissipation structure. The method of manufacturing a semiconductor package according to claim 1, wherein the carrier is further provided with a barrier to control the range of the first primer. The method of fabricating a semiconductor package according to claim 1, wherein the first electronic component is adhered to the carrier by a heat dissipating adhesive or a thermal interface material. The method of fabricating a semiconductor package according to claim 1, wherein the second surface of the interposer is provided with a second electronic component, and the second primer covers the second electronic component.