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TWI552339B - 半導體裝置、半導體裝置的製造方法 - Google Patents

半導體裝置、半導體裝置的製造方法 Download PDF

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TWI552339B
TWI552339B TW103137558A TW103137558A TWI552339B TW I552339 B TWI552339 B TW I552339B TW 103137558 A TW103137558 A TW 103137558A TW 103137558 A TW103137558 A TW 103137558A TW I552339 B TWI552339 B TW I552339B
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semiconductor device
semiconductor substrate
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西澤弘一郎
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三菱電機股份有限公司
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Description

半導體裝置、半導體裝置的製造方法
本發明係關於具有例如電極中使用的金屬層之半導體裝置及其半導體裝置的製造方法
專利文件1中，揭示在絕緣膜的側壁上以濕處理形成阻障層、晶種層以及配線層的技術。
[先行技術文件] [專利文件]
[專利文件1]日本專利第2006-16684號公開公報
以GaAs(砷化鎵)形成的半導體基板及以Cu(銅)、Ag(銀)或Au(金)形成的金屬層之間有時設置阻障層。阻障層，係用以防止金屬層的材料往半導體基板擴散而設置。考慮TiW(鈦鎢)、鎢(W)、鉭(Ta)、TaN(氮化鉭)、Ti(鈦)、TiN(氮化鈦)、Co(鈷)、Pd(鈀)或Ru(釕)作為阻障層的材料。這些材料中，以Pd以外的材料作為阻障層時，因為阻障層與GaAs 的反應性低，阻障層與半導體基板的密合性不足。
又，以Pd作為阻障層時，因為阻障層與GaAs的反應性高，阻障層與半導體基板容易形成合金。由於形成此合金，阻障層變得沒有阻障層功能，具有金屬層的材料往半導體基板擴散的問題。
本發明，因為係用以解決上述問題而遂至完成，以提供防止金屬層的材料往半導體基板擴散，且半導體基板與其上的層的密合性高之半導體裝置及其半導體裝置的製造方法為目的。
本案發明的半導體裝置，其特徵在於包括半導體基板，以GaAs(砷化鎵)形成；密合層，在上述半導體基板上以Pd(鈀)或包含Pd的合金形成；阻障層，在上述密合層上以Co(鈷)或包含Co的合金形成；以及金屬層，在上述阻障層上以Cu(銅)、Ag(銀)或Au(金)形成。
本案發明的半導體裝置的製造方法，其特徵在於包括密合層形成步驟，在以GaAs(砷化鎵)形成的半導體基板上，以Pd或包含Pd的合金形成密合層；阻障層形成步驟，在上述密合層上以Co(鈷)或包含Co的合金形成阻障層；以及熱處理步驟，升溫上述半導體基板、上述密合層以及上述阻障層至25℃~250℃為止，上述密合層中形成Pd-Ga-As，上述密合層與上述阻障層之間形成包含Co與Pd的合金層。
本案發明的另一半導體裝置的製造方法，其特徵在於包括密合層形成步驟，在GaAs形成的半導體基板上，以 Pd或包含Pd的合金形成密合層；阻障層形成步驟，對上述半導體基板施行無電解電鍍，在上述密合層上以Co-P(磷)或Co-W-P形成阻障層；以及金屬層形成步驟，在上述阻障層上以Cu、Ag或Au形成金屬層。
根據本發明，以GaAs形成的半導體基板與金屬層之間，由於設置以Pd或包含Pd的合金形成並連接半導體基板的密合層、以及以Co或包含Co的合金形成的阻障層，防止金屬層的材料往半導體基板擴散，並可以提高半導體基板與其上的層之間的密合性。
10‧‧‧半導體裝置
12‧‧‧半導體基板
14‧‧‧密合層
16‧‧‧阻障層
18‧‧‧金屬層
50‧‧‧半導體裝置
52‧‧‧密合層
54‧‧‧合金層
150‧‧‧半導體裝置
152‧‧‧阻障層
[第1圖]係根據第一實施例的半導體裝置的剖面圖；[第2圖]係顯示XPS深度分析的結果圖；[第3A圖]係熱處理前的樣品剖面圖；[第3B圖]係熱處理後的樣品剖面圖；[第4圖]係根據第二實施例的半導體裝置的剖面圖；[第5A圖]係熱處理前的樣品剖面圖；[第5B圖]係熱處理後的樣品剖面圖；[第6A圖]係熱處理前的樣品的XPS深度分析的結果圖；[第6B圖]係熱處理後的樣品的XPS深度分析的結果圖；[第7圖]係顯示根據第三實施例的半導體裝置的製造方法之流程圖；[第8圖]係顯示XPS解析的結果圖； [第9圖]係顯示XPS解析的結果圖；[第10圖]係顯示4個樣品(Pd-P、Ni-P、Co-P、Co-W-P)的特性表；[第11圖]係以Co-W-P無電解電鍍形成阻障層的半導體裝置的剖面圖；[第12A圖]係熱處理前的樣品剖面圖；[第12B圖]係熱處理後的樣品剖面圖；[第13A圖]係熱處理前的樣品的XPS深度分析的結果圖；以及[第13B圖]係熱處理後的樣品的XPS深度分析的結果圖。
關於根據本發明實施例的半導體裝置及半導體裝置的製造方法，參照圖面說明。相同或對應的構成要素附上相同的符號，有時會省略重複的說明。
[第一實施例]
第1圖係根據本發明第一實施例的半導體裝置10的剖面圖。半導體裝置10包括以GaAs形成的半導體基板12。半導體基板12上形成密合層14。密合層14以Pd或包含Pd的合金(之後，Pd或包含Pd的合金，稱作Pd材料)形成。所謂包含Pd的合金，例如Pd-P(Pd-P表示Pd與P的合金，之後同樣使用連字號表示合金)。
密合層14上形成阻障層16。阻障層16以Co或包含Co的合金(之後，Co或包含Co的合金，稱作Co材料)形成。密合層14與阻障層16如下形成。首先，前處理，浸泡半導體 基板12在例如5%的稀鹽酸中5分鐘。之後，以例如蒸鍍法或濺鍍法在真空環境內連續形成密合層14與阻障層16。由於連續形成密合層14與阻障層16，相較於以其他製程形成的情況，可以防止密合層14的表面氧化及污染。
阻障層16上形成金屬層18。金屬層18以Cu、Ag或Au形成。金屬層18，作用為例如半導體裝置10的電極。
第2圖係顯示關於以GaAs形成的半導體基板上蒸鍍Pd層的樣品之XPS深度分析的結果圖。XPS深度分析係對As-depo(初鍍)狀態(緊接成膜後的狀態)的樣品實施。根據第2圖，看出Pd層成為Pd-Ga-As的合金層。由於形成Pd-Ga-As，認為Pd層對半導體基板具有高密合性。
第一實施例的半導體裝置10中，半導體基板12上以Pd材料形成密合層14，密合層14中形成Pd-Ga-As。因此，半導體基板與其上的層(密合層14)之間可以得到充分的密合性。
又，因為Pd與Co係構成全率固溶體的關係，以Pd材料形成的密合層14與以Co材料形成的阻障層16之間形成Pd-Co。因此，密合層14與阻障層16的密合性良好。例如採用W、Ta、Ti或Ru作為阻障層時，因為這些都沒有與Pd構成全率固溶體的關係，密合層與阻障層不充分密合。因此，阻障層16最好以Co材料形成。
以Co材料形成的阻障層16及以GaAs形成的半導體基板12由於反應性低，不合金化。因此，可以以阻障層16防止金屬層18的材料往半導體基板12擴散。
第3A圖係在以GaAs形成的半導體基板與以Cu形成的金屬層之間設置Pd層的樣品剖面圖。第3B圖係以270℃熱處理3小時後的樣品剖面圖。根據第3B圖，Pd層與半導體基板完全反應，看出金屬層幾乎消失。即，失去Pd層對金屬層的阻障性。於是，半導體基板與金屬層之間只設置Pd時，金屬層的材料(Cu)往半導體基板擴散。為了防止以上所述，如本發明第一實施例，以Co材料形成的阻障層16是必需的。
根據本發明第一實施例的半導體裝置10可以是各種變形。例如，金屬層18可以是下層有Au，上層有Cu的2層構造。此Au可以以蒸鍍、濺鍍、或無電解置換Au電鍍形成。無電解置換Au電鍍，例如，使用包含亞硫酸Au與亞硫酸Na(鈉)的電鍍液。因為阻障層16的Co比Au的離子化傾向高，無電解Au電鍍液中，Au置換可以形成Au。
以無電解電鍍形成Au，可以成為低成本製程的構築。又，可以抑制Co材料表面的腐蝕及氧化。以無電解電鍍形成Au，對於如貫通電極構造(通孔)的凹凸形狀，可以均等形成Au。又，以濺鍍法、蒸鍍法，對於凹凸形狀無法均等形成Au。
而且，上層的Cu對下層的Au，具有高密合性。以電鍍形成Cu時，由於Au的存在電阻下降。因此，電鍍生長穩定，電鍍表面粗糙，以及可以抑制晶圓(半導體基板)面內的膜厚不均。於是，金屬層為Au與Cu的2層構造時，相較於金屬層只以Cu形成的情況，可以降低半導體基板12上的構 造(電極)全體的電阻值。
又，金屬層18，也可以用作配線而非電極。這些變形，可以應用根據以下實施例的半導體裝置與半導體裝置的製造方法。關於根據以下實施例的半導體裝置與半導體裝置的製造方法，以不同於第一實施例的點為中心說明。
[第二實施例]
係根據本發明第二實施例的半導體裝置50的剖面圖。密合層52全體以Pd-Ga-As形成。密合層52與阻障層16之間形成包含Co與Pd的合金層54。
說明關於半導體裝置50的製造方法。首先，以GaAs形成的半導體基板12上以Pd或包含Pd的合金(Pd材料)形成密合層。其次，密合層上以Co或包含Co的合金(Co材料)形成阻障層16。
其次，升溫半導體基板、密合層及阻障層至25℃~250℃為止。因此，形成密合層52(Pd-Ga-As)，而密合層52與阻障層16之間形成包含Co與Pd的合金層54。此步驟稱作熱處理步驟。熱處理步驟最好在氮氣中實施1小時左右。
說明關於熱處理步驟。因為Pd材料與半導體基板(GaAs)在20℃以上開始反應，所以以熱處理步驟促進Pd材料與半導體基板12的反應。Pd材料的厚度如果是5nm(毫微米)左右的話，熱處理的溫度即使是25℃左右密合層也全部成為Pd-Ga-As。又，因為Co與Pd有構成全率固溶體的關係，以較低的熱，在這些界面形成合金層54。
於是，設置熱處理步驟，可以形成以Pd-Ga-As 形成的密合層52，以及Co-Pd形成的合金層54。於是，可以提高層間的密合性。
第5A圖係在以GaAs形成的半導體基板上以5nm的Pd膜介於其間，緊接於形成Co-P後的樣品剖面圖。第5B圖係對此樣品在250℃下施行1小時的熱處理後的樣品剖面圖。根據第5B圖，看出熱處理前後Co-P的層厚幾乎沒變化。第6A圖係顯示關於具有GaAs/Pd/Co-P/Au的組成之As-depo狀態的樣品之XPS深度分析結果圖。斜線(/)左側的層上形成斜線(/)右側的層。於是，此樣品，在GaAs上有Pd層，在Pd層上有Co-P，以及Co-P上有Au。Pd層的層厚係數nm。第6B圖係顯示對第6A圖分析的樣品在250℃下施行1小時的熱處理後的XPS深度分析結果圖。看出熱處理後也維持GaAs/Pd/Co-P/Au的組成。於是，根據第5圖的剖面圖及第6圖的XPS深度分析結果，看出Co材料在以GaAs形成的半導體基板上難以擴散。又，根據其他的實驗，Co-P在375℃以下不與半導體基板(GaAs)反應。因此，以Co材料形成的阻障層16與GaAs反應，因為不會損傷對Cu(金屬層)的阻障性，可以防止金屬層18的材料往半導體基板12擴散。
可是，上述的熱處理步驟最好在金屬層18形成後進行。因為阻障層16的Co、與金屬層18的Cu、Ag或Au有構成全率固溶體的關係，可以以熱處理步驟在這些界面中形成合金層。為了形成上述合金層，最好在例如250℃下實施1小時的熱處理。藉由形成上述合金層，可以又提高層間的密合性而提高半導體裝置的特性，又縮小半導體裝置。
密合層52不全體以Pd-Ga-As形成，一部分以Pd-Ga-As形成也可以。
[第三實施例]
第7圖係顯示根據本發明第三實施例的半導體裝置的製造方法之流程圖。此製造方法的特徵之一係以無電解電鍍形成阻障層。首先，為了除去以GaAs形成的半導體基板的表面氧化物等，以例如如5%的稀鹽酸進行5分鐘的前處理(步驟100)。
其次，在步驟102進行處理。步驟102中，以GaAs形成的半導體基板上以Pd或包含Pd的合金形成密合層。密合層，例如，對半導體基板表面施行Pd活性化處理而形成。Pd活性化處理係例如在30℃以下的氯化鈀溶液等的包含Pd離子的液體中浸泡半導體基板3分鐘之處理。
密合層的層厚最好是1nm以上30nm以下。比此範圍厚的話，密合性不良，薄的話，在密合層上形成的Co-P等變得形成不良。根據上述的步驟，可以形成密合層(Pd層)1nm~30nm左右。
第8圖係顯示Pd活性化處理後半導體基板的XPS解析結果圖。第8圖顯示對以GaAs形成的半導體基板(GaAs基板)施行Pd活性化處理時的XPS解析結果，以及對以Si形成的半導體基板(Si基板)施行Pd活性化處理時的XPS解析結果。GaAs基板的XPS光譜中，因為出現Pd 3d軌道的峰值，看出Pd充分附著於GaAs基板。
另一方面，Si基板的XPS光譜中，因為沒出現Pd 3d軌道的峰值，看出Pd無法在Si基板上形成。第9圖係顯示對Si基板施行Pd活性化處理時的Si 2p軌道的XPS解析結果圖。因為檢測出SiO2(二氧化矽)的峰值，看出表面氧化。Si基板的表面氧化，原因被認為是是Pd活性化處理中Pd觸媒引起的氧化還原反應。由於這氧化是原因，Pd對Si基板不密合。
其次，往步驟104進行處理。步驟104中，GaAs基板上剩餘附著的Pd以純水沖洗。也可以省略步驟104。其次，往步驟106進行處理。步驟106中，對半導體基板施行無電解電鍍，密合層上以Co-P或Co-W-P形成阻障層。例如，浸泡半導體基板在無電解Co電鍍液中，形成Co-P。無電解Co電鍍液，係例如在硫酸Co與次磷酸鈉中加入錯合劑等的電鍍液。
其次，往步驟108進行處理。步驟108中，以純水沖洗半導體基板。也可以省略步驟108。其次，往步驟110進行處理。步驟110中，在阻障層上形成以Cu、Ag或Au形成的金屬層。
根據本發明第三實施例的半導體裝置的製造方法，因為以無電解電鍍形成阻障層，所以可以以批次處理形成阻障層。又，因為可以以無電解電鍍只在半導體基板上形成阻障層，相較於反應室內壁全體成膜的濺鍍法或蒸鍍法，成膜效率佳。因此，可以降低製程成本。
又，因為以無電解電鍍形成阻障層，對於如貫通電極構造(通孔)的凹凸形狀，可以均等形成阻障層。因此，可以確實防止金屬層的材料往半導體基板擴散。又，對於凹凸形 狀無法以濺鍍法或蒸鍍法均等形成阻障層。
第10圖係顯示4個樣品(Pd-P、Ni-P、Co-P、Co-W-P)的特性表。Pd-P、Ni-P、Co-P、Co-W-P，係對以Pd活性化處理形成5nm左右的Pd之GaAs基板，以無電解電鍍形成。
第10圖的最右側的欄位，顯示對各樣品以250℃施行1小時的熱處理後的膜應力。看出熱處理後的膜應力係Co-P最低。又，Co-W-P的膜應力也成為小的值。Co-P及Co-W-P的膜應力小的理由，被認為是因為Co相較於Pd或Ni與GaAs基板的反應性低。又，Pd-P，因為以20℃以上這樣的低溫與GaAs基板反應，As-depo狀態下上述反應也進行，形成高的膜應力。於是，為了降低膜應力，最好以Co材料形成阻障層。
第11圖係以Co-W-P無電解電鍍形成阻障層152的半導體裝置150的剖面圖。藉由阻障層152內加入高融點金屬W，可以確實防止金屬層18的材料(例如Cu)往半導體基板12擴散。第12A圖係在GaAs基板上由Pd層(數nm)介於其間形成Co-W-P的樣品剖面圖。第12B圖係對此樣品以250℃施行1小時的熱處理後的樣品剖面圖。熱處理前後，層厚及界面的狀況中看不到變化。第13A圖係關於具有GaAs/Pd/Co-W-P/Au組成的As-depo狀態的樣品之XPS深度分析的結果圖。斜線(/)左側的層上形成斜線(/)右側的層。第13B圖，係顯示對於第13A圖中分析的樣品以250℃施行1小時的熱處理後之XPS深度分析的結果圖。看出熱處理後也維持 GaAs/Pd/Co-W-P/Au組成。因此，根據第12圖的剖面圖及第13圖的XPS深度分析的結果，看出以Co-W-P形成的阻障層在GaAs基板上的穩定性高。因此，可以確實防止金屬層的材料往半導體基板擴散。
又，到此為止說明的各實施例的特徵，也可以適當組合使用。
10‧‧‧半導體裝置
12‧‧‧半導體基板
14‧‧‧密合層
16‧‧‧阻障層
18‧‧‧金屬層

Claims (11)

  1. 一種半導體裝置，包括：半導體基板，以GaAs形成；密合層，在上述半導體基板上以Pd或包含Pd的合金形成；阻障層，在上述密合層上以Co或包含Co的合金形成；以及金屬層，在上述阻障層上以Cu、Ag或Au形成。
  2. 如申請專利範圍第1項所述的半導體裝置，其中上述密合層的一部分以Pd-Ga-As形成。
  3. 如申請專利範圍第1項所述的半導體裝置，其中上述密合層全體以Pd-Ga-As形成。
  4. 如申請專利範圍第1至3項中任一項所述的半導體裝置，其中上述密合層與上述阻障層之間包括含有Co與Pd的合金層。
  5. 如申請專利範圍第1至3項中任一項所述的半導體裝置，其中上述密合層的層厚在1nm以上30nm以下。
  6. 如申請專利範圍第1項所述的半導體裝置，其中上述密合層以Pd-P形成。
  7. 如申請專利範圍第1至3、6項中任一項所述的半導體裝置，其中上述阻障層以Co-P或Co-W-P形成。
  8. 一種半導體裝置的製造方法，包括下列步驟：密合層形成步驟，在以GaAs形成的半導體基板上，以Pd或包含Pd的合金形成密合層；阻障層形成步驟，在上述密合層上以Co或包含Co的合金 形成阻障層；以及熱處理步驟，升溫上述半導體基板、上述密合層以及上述阻障層至25℃~250℃為止，上述密合層中形成Pd-Ga-As，上述密合層與上述阻障層之間形成包含Co與Pd的合金層。
  9. 如申請專利範圍第8項所述的半導體裝置的製造方法，其中上述熱處理步驟之前，在上述阻障層上，以Cu、Ag或Au形成金屬層。
  10. 一種半導體裝置的製造方法，包括下列步驟：密合層形成步驟，在以GaAs形成的半導體基板上，以Pd或包含Pd的合金形成密合層；阻障層形成步驟，對上述半導體基板施行無電解電鍍，在上述密合層上以Co-P或Co-W-P形成阻障層；以及金屬層形成步驟，在上述阻障層上，以Cu、Ag或Au形成金屬層。
  11. 如申請專利範圍第10項所述的半導體裝置的製造方法，其中上述金屬層係下層具有Au而上層具有Cu的2層構造。
TW103137558A 2014-03-27 2014-10-30 半導體裝置、半導體裝置的製造方法 TWI552339B (zh)

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