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TWI550818B - 靜電防護元件及其製造方法 - Google Patents

靜電防護元件及其製造方法 Download PDF

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TWI550818B
TWI550818B TW102128554A TW102128554A TWI550818B TW I550818 B TWI550818 B TW I550818B TW 102128554 A TW102128554 A TW 102128554A TW 102128554 A TW102128554 A TW 102128554A TW I550818 B TWI550818 B TW I550818B
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type well
gate
doped region
nmos
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TW201507092A (zh
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鄭志男
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天鈺科技股份有限公司
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Priority to CN201310351209.8A priority patent/CN104347623B/zh
Priority to US14/456,041 priority patent/US9748221B2/en
Publication of TW201507092A publication Critical patent/TW201507092A/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/811—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using FETs as protective elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
    • H10D30/0281—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of lateral DMOS [LDMOS] FETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
    • H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] 
    • H10D62/108—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]  having localised breakdown regions, e.g. built-in avalanching regions 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
    • H10D84/151—LDMOS having built-in components
    • H10D84/153—LDMOS having built-in components the built-in component being PN junction diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/113—Isolations within a component, i.e. internal isolations
    • H10D62/115—Dielectric isolations, e.g. air gaps
    • H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H10D62/156—Drain regions of DMOS transistors
    • H10D62/157—Impurity concentrations or distributions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
    • H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
    • H10P30/204—
    • H10P30/21—

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  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Physics & Mathematics (AREA)
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Description

靜電防護元件及其製造方法
本發明涉及一種靜電放電防護元件及靜電防護元件的製造方法。
隨著製程技術的進步，ESD之耐受力已經是積體電路可靠度的主要考量的參數之一。一般的積體電路均須特別設計ESD防護電路，用以保護積體電路中的元件免於遭受ESD損害。然而，目前的ESD防護電路一般會增加積體電路的複雜程度、佔用面積及製造成本。
有鑑於此，有必要提供一種靜電防護元件。
還有必要提供一種靜電保護元件的製造方法。
一種靜電防護元件，至少包括：設置於P型基底上的二N型金屬氧化物半導體(N-Metal Oxide Semiconductor，NMOS)；每一NMOS包括閘極、源極與汲極，其中該源極與汲極形成於該閘極的兩側；該靜電防護元件還包括注入汲極外側的高濃度摻雜，且該高濃度摻雜與該P型基底形成PN結。
一種靜電防護元件的製造方法，包括：提供一P型基底，並於該P型基底中形成N型井；於該N型井中形成P型井以定義該二NMOS的所在區域；於該N型井邊緣形成絕緣結構；利用絕緣結構為屏蔽，將N型雜質、P型雜質摻雜至該P型井以形成P+摻雜區、第一N+摻雜區及第二N+摻摻雜區；於一絕緣結構上形成閘極；及於該第一N+摻雜層外側注入高濃度N型雜質，以形成高濃度摻雜。
相較於先前技術，本發明的靜電防護元件及其製造方法將N型高濃度摻雜注入汲極的外側，以與基底形成一個具有較低崩潰電壓的PN結，進而當靜電發生時可提供一較低的觸發電壓將靜電釋放，同時將高濃度摻雜直接形成於基底上減小了積體電路面積與製程。
10‧‧‧靜電防護元件
11‧‧‧P型基底
13‧‧‧N型井
15‧‧‧閘極
111‧‧‧絕緣層
113‧‧‧高壓閘極氧化層
17‧‧‧P+摻雜區
19‧‧‧第一N+摻雜區
21‧‧‧第二N+摻雜區
23‧‧‧P型井
25‧‧‧高濃度摻雜
30‧‧‧直流轉換器
32‧‧‧高邊開關
34‧‧‧低邊開關
36‧‧‧輸出端
38‧‧‧二極體
S201~S211‧‧‧步驟
圖1是本發明的一靜電防護元件一較佳實施方式的佈局示意圖。
圖2是圖1中靜電防護元件沿II-II線的剖面示意圖。
圖3是本發明靜電防護元件製造方法流程圖。
圖4是圖1所示的靜電防護元件應用於直流轉換器時之靜電防護等效電路圖。
請一併參閱圖1與圖2，圖1是本發明的靜電防護元件10一較佳實施方式的佈局示意圖；圖2是圖1中靜電防護元件10沿II-II線的剖面示意圖。該靜電防護元件10至少包括二N型金屬氧化物半導體(N-Metal Oxide Semiconductor，NMOS)。該二NMOS係設置於P型基底11的N型井13中。該每一NMOS包括閘極15，該閘極15的一部份覆蓋於絕緣層111上，另一部份則覆蓋於高壓閘極氧化層113上，其中絕緣層111利用一般氧化層製程所製成。
每一NMOS中在閘極15一側包括一互相毗連的P+摻雜區17及第一N+摻雜區19，其中該第一N+摻雜區19為該NMOS的源極。在閘極15另一側的P型基底11中設置第二N+摻雜區21，該第二N+摻雜區21為該NMOS的汲極。該第二N+摻雜區21與閘極15之間為絕緣層111隔離。
在本實施方式中，該P+摻雜區17及第一N+摻雜區19形成於一P型井23中，其中該P型井23形成於該P型基底11的N型井13中。
進一步，該靜電防護元件10還包括一高濃度摻雜25。該高濃度摻雜25係利用一ESD植入光罩產生，並以N型雜質，如磷、砷或銻等，在使摻雜劑量大於一預定值的條件下植入N型井13中，後再經由磊晶製程以及驅入製程完成。該高濃度摻雜25環形設置於該P型井23外圍區域。
在本實施方式中，該高濃度摻雜25中N型材料的濃度高於8.5E12 atom/cm2，且採用約為150KeV左右的高能量離子佈植。
在本實施方式中，該高濃度摻雜25與該P型基底11形成之PN結可充當一二極體，且由於該高濃度摻雜25為高濃度N型半導體材料 ，故該PN結可提供較低之崩潰電壓。當靜電放電時，該PN結可將電流快速釋放，從而增強整個元件的靜電防護功能。
請一併參閱圖3，圖3是本發明靜電防護元件10的製造流程示意圖。在本實施方式中，該靜電防護元件10包括至少二NMOS。
步驟S201，提供一P型基底11，並於該P型基底11中形成N型井13。
步驟S203，於該N型井13中形成P型井23以定義該二NMOS的所在區域。
步驟S205，於該N型井13邊緣形成絕緣層111。
步驟S207，利用絕緣層111為屏蔽，將N型雜質、P型雜質摻雜至該P型井23以形成P+摻雜區17、第一N+摻雜區19及第二N+摻雜區21。其中該第一N+摻雜區19為NMOS元件的源極，該第二N+摻雜區21為NMOS元件的汲極。在本實施方式中，可利用但不限於離子植入技術，將N型雜質、P型雜質，以加速離子的形成植入該P型井中。
步驟S209，於一絕緣層111上形成閘極15。在本實施方式中，可利用但不限於薄膜沉積技術，沉積形成閘極15。
步驟S211，於該第一N+摻雜層汲極外側注入高濃度N型雜質，以形成高濃度摻雜。該高濃度摻雜為環形設置。在本實施方式中，利用但不限於離子植入技術，將高濃度N型雜質，以加速離子的形成高濃度摻雜。在本實施方式中，該高濃度摻雜25中N型材料的濃度高於8.5E12 atom/cm2，且採用約為150KeV左右的高能量離子佈植。
請參閱圖4，圖4為圖1所示的靜電防護元件10應用於直流轉換器30時的等效電路圖。該直流轉換器30包括高邊開關32、低邊開關34及輸出端36。其中該高邊開關32為NMOS FET，低邊開關34亦為NMOS FET，該高邊開關32與低邊開關34在控制信號控制下交替導通。在本實施方式中，該高邊開關32及該低邊開關34為設置於同一基底上的靜電防護元件。當發生靜電放電時，該靜電防護元件內部由高度摻雜層與基底形成之PN結等效為一接地二極體38，該二極體38因為較低之崩潰電壓而迅速導通將靜電釋放。
前述的靜電防護元件及其製造方法將N型高濃度摻雜注入汲極的外側，以與基底形成一個具有較低崩潰電壓的PN結，進而當靜電發生時可提供一較低的觸發電壓將靜電釋放，同時將高濃度摻雜直接形成於基底上減小了積體電路面積與製程。
雖然本發明以優選實施例揭示如上，然其並非用以限定本發明，任何本領域技術人員，在不脫離本發明的精神和範圍內，當可做各種的變化，這些依據本發明精神所做的變化，都應包含在本發明所要求的保護範圍之內。
10‧‧‧靜電防護元件
11‧‧‧P型基底
13‧‧‧N型井
15‧‧‧閘極
111‧‧‧絕緣層
113‧‧‧高壓閘極氧化層
17‧‧‧P+摻雜區
19‧‧‧第一N+摻雜區
21‧‧‧第二N+摻雜區
23‧‧‧P型井
25‧‧‧高濃度摻雜

Claims (9)

  1. 一種靜電防護元件，至少包括：設置於P型基底上的二N型金屬氧化物半導體(N-Metal Oxide Semiconductor，NMOS)，該P型基底中形成N型井，該N型井中形成P型井以定義該二NMOS的所在區域；每一NMOS包括閘極、源極與汲極，其中該源極與汲極形成於該閘極的兩側；該靜電防護元件還包括注入汲極外側的高濃度摻雜，且該高濃度摻雜設置於該P型井的外圍區域的該N型井中以與該P型基底形成PN結，該PN結充當一二極體。
  2. 如請求項1所述之靜電防護元件，其中，該閘極跨接於一絕緣層及一高壓閘極氧化層上。
  3. 如請求項2所述之靜電防護元件，其中，每一NMOS中在閘極一側包括一互相毗連的P+摻雜區及第一N+摻雜區，閘極另一側設置第二N+摻雜區，該第一N+摻雜區為NMOS的源極，第二N+摻雜區為NMOS的汲極。
  4. 如請求項3所述之靜電防護元件，其中，該P+摻雜區及第一N+摻雜區形成於該P型井中。
  5. 如請求項4所述之靜電防護元件，其中，該高濃度摻雜中N型材料的濃度高於8.5E12 atom/cm2，且採用約為150KeV左右的高能量離子佈植。
  6. 一種靜電防護元件的製造方法，包括：提供一P型基底，並於該P型基底中形成N型井；於該N型井中形成P型井以定義該二NMOS的所在區域；於該N型井邊緣形成絕緣結構； 利用絕緣結構為屏蔽，將N型雜質、P型雜質摻雜至該P型井以形成P+摻雜區、第一N+摻雜區及第二N+摻雜區；於一絕緣結構上形成閘極；及於該第一N+摻雜層外側注入高濃度N型雜質，以形成高濃度摻雜，該高濃度摻雜設置於該P型井的外圍區域的該N型井中以與該P型基底形成PN結，該PN結充當一二極體。
  7. 如請求項6所述之靜電防護元件的製造方法，其中，該第一N+摻雜區為NMOS的源極，該第二N+摻雜區為NMOS的汲極。
  8. 如請求項6所述之靜電防護元件的製造方法，其中，於一絕緣結構上形成閘極步驟利用薄膜沉積技術，沉積形成閘極。
  9. 如請求項7所述之靜電防護元件的製造方法，其中，將濃度高於8.5E12 atom/cm2的N型材料，採用約為150KeV左右的高能量離子佈植形成高濃度摻雜。
TW102128554A 2013-08-09 2013-08-09 靜電防護元件及其製造方法 TWI550818B (zh)

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CN201310351209.8A CN104347623B (zh) 2013-08-09 2013-08-14 静电防护元件及其制造方法
US14/456,041 US9748221B2 (en) 2013-08-09 2014-08-11 Electrostatic discharge protection device and manufacturing method thereof

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US10340266B2 (en) * 2017-10-02 2019-07-02 Globalfoundries Singapore Pte. Ltd. ESD protection circuit and method of making the same
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US20150041920A1 (en) 2015-02-12

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