TWI549416B - Power supply apparatuses for preventing latch-up of charge pump and methods thereof - Google Patents

Description

Power supply device for preventing charge pump lock and method thereof [Cross-reference to related applications]

The present application claims the priority of Korean Patent Application No. 10-2011-0014252 and No. 10-2011-0028253, which are filed on Jan. 17, 2011 and March 29, 2011, respectively, to Korea. The Intellectual Property Office, all of which is incorporated herein by reference.

The illustrative embodiments are directed to a power supply, and in particular to a power supply device including a charge pump, and to methods therefor.

Electrical or electronic devices typically use a direct current (DC) power supply that converts an alternating current (AC) power source to a direct current voltage to drive the device. A switching mode power supply (SMPS) is used as a DC power supply.

The DC power supplied by the switching power supply is applied to various parts of the electronic device. Since the switching power supply is supplied with 5V, 3.3V or 12V, the electronic device also includes a charge pump that receives the DC voltage from the switching power supply and boosts the DC voltage to various parts of the electronic device (for example) The level of the chipset and memory).

However, parts may be affected due to environmental conditions, such as design errors and ambient temperature errors (eg, when latch-up effects occur due to spike currents), resulting in uneven current distribution.

In the case of the latch-up effect, currents in excess of several hundred milliamps (mA) Flows in the circuit and interrupts or destroys the circuit. For example, a parasitic PNPN structure (also known as a thyristor structure) is in an N-type metal oxide semiconductor (NMOS) and a P-type metal oxide semiconductor (PMOS). The inter-initial is triggered, and the inrush current may flow into the thyristor structure; the N-type MOS and the P-type MOS are adjacent to each other in a complementary metal oxide semiconductor (CMOS) structure. A large amount of current may affect the device because the input/output voltage exceeds the rated voltage and the inrush current (or leakage current) flows into the internal device, or the internal device fails due to the voltage at the power supply terminal exceeding the rated voltage. To prevent this latch-up effect, an external Schottky diode is typically used, or an internal Schottky diode can be provided in the integrated circuit.

However, when an external Schottky diode is used, the manufacturing price of the module rises. Internal Schottky diodes increase wafer size.

According to some demonstrative embodiments, a power supply device is provided that includes an internal power supply, a charge pump, and an inrush current controller. The internal power supply includes a first voltage generator that generates a first voltage according to a pulse width modulation control signal; the charge pump receives the first voltage and generates a second voltage; and the inrush current The controller is connected between the charge pump and the internal power supply, and generates a pulse width modulation control signal according to the target signal and the selection reference voltage.

The inrush current controller can include a first sampling circuit, a reference voltage generator, and a first comparator. The first sampling circuit responds to the first enabling signal The first voltage is divided, and the target signal is output according to the voltage division; the reference voltage generator outputs a selection reference voltage in response to the reference voltage selection signal; and the first comparator compares the target signal with the selection reference voltage, and outputs the pulse width. Modulate the control signal.

In some exemplary embodiments, the first voltage generator generates a feedback signal, and the internal power supply includes a pulse generator that generates a pulse wave based on the feedback signal. The pulse generator may include a sawtooth pulse generator, a sawtooth pulse comparison signal generator, and a second comparator. The sawtooth pulse generator generates a sawtooth pulse wave having a slope, and the sawtooth pulse wave is a modulation signal according to a pulse width modulation and a second enable signal; the sawtooth pulse wave comparison signal generator responds to the second enable signal The target signal or the feedback signal is output as a sawtooth pulse comparison signal; and the second comparator compares the sawtooth pulse with the sawtooth pulse to generate a switching pulse.

The sawtooth pulse generator can include a second generation circuit, a first waveform generator, and a second waveform generator. The second generating circuit divides the supply voltage by a plurality of resistors, and generates a plurality of secondary reference voltages according to the divided voltage; the first waveform generator is connected to the second generating circuit and the sawtooth pulse wave output Between the terminals, the voltage is selected from the secondary reference voltage according to the second enable signal, and the ground voltage is pulled up by responding to the voltage selected from the secondary reference voltage to generate the first waveform; The second waveform generator is connected between the second generating circuit and the sawtooth pulse output end, and pulls down the voltage of the sawtooth pulse wave output to generate a second waveform by responding to the falling signal, wherein the falling signal is in the second waveform generator Generated, and according to the sampling supply voltage, the sampling supply voltage is based on the internal power supply Pulse signal.

The first waveform generator can include a bias circuit, a pull up circuit, and a memory. The bias circuit outputs one of the secondary reference voltages as a soft bias signal in response to the pulse width modulation control signal, or outputs a maximum bias signal as a sawtooth pulse basic signal in response to the second enable signal; The pull-up circuit pulls up the voltage of the sawtooth pulse wave output end in response to the sawtooth pulse wave basic signal; and the memory is connected between the sawtooth pulse wave output end and the ground end, and is used for storing the pull-up signal and generating the first waveform.

According to other exemplary embodiments, a power supply method performed by a power supply is provided, the power supply including an internal power supply and a charge pump. The power supply method comprises: generating a target signal according to a first voltage generated by the internal power supply in response to the first enable signal, generating a selection reference voltage from the supply voltage, and generating a pulse width modulation control according to the target signal and the selected reference voltage. The signal controls the pulse width of the switching pulse wave according to the pulse width modulation control signal, controls the amount of inrush current of the input charge pump according to the switching pulse wave, and uses the charge pump to generate the second voltage.

At least another exemplary embodiment discloses a power supply that includes a charge pump and an internal power supply. The charge pump receives a first voltage and generates a second voltage according to the first voltage; and the internal power supply generates a first voltage according to a pulse width of the switching pulse wave, and includes a pulse wave generator, The pulse wave generator generates a switching pulse according to the modulation control signal, and the modulation control signal is different from the second voltage, and the modulation control signal is compared according to the target signal and the selected reference voltage.

A detailed description of the illustrative embodiments is provided below with the accompanying drawings The above and other features and advantages of the exemplary embodiments will be more apparent from the description.

The illustrative embodiments will now be described more fully hereinafter with reference to the accompanying drawings. However, the illustrative embodiments may be embodied in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. Rather, these illustrative embodiments are provided so that this disclosure will be thorough and complete, and the scope of the exemplary embodiments will be fully conveyed by those skilled in the art. In the drawings, the dimensions and relative sizes of layers and regions may be exaggerated for clarity. Throughout the text, the same component symbols represent similar components.

It will be understood that when an element is "connected" or "coupled" to another element, the element can be directly connected or coupled to the other element or the intervening element can be present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, the intervening element does not. The term "and/or" used herein includes all combinations of one or more of the associated listed items and may be abbreviated as "/".

It should be understood that although the terms "first", "second", and the like may be used herein to describe various elements, these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, the first signal may be referred to as a second signal without departing from the teachings of the present disclosure. Similarly, the second signal may be referred to as a first signal.

The terminology used herein is for the purpose of describing particular embodiments, and is not intended to As used in this article, unless the context is clear The singular forms "一" and "said" are intended to include the plural. It is to be understood that the phrase "comprising" or "an", "the" Integers, steps, operations, components, components, and/or combinations thereof.

All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by the ordinary skill in the art of the exemplary embodiments, unless otherwise defined. It should be further understood that the interpretation of the meaning of the terms, such as the terms defined in the general dictionary, should be consistent with the meaning in the context of the relevant art and/or the present invention, and will not be idealized or overly formal unless explicitly defined herein. The meaning is explained.

FIG. 1 is a block diagram of a power supply 1000 in accordance with some demonstrative embodiments.

The power supply 1000 includes an internal power supply 100, a charge pump 200, an inrush current controller 300, and a timing controller 400.

The internal power supply 100 performs a switching operation in response to the clock signal SMPS_CK applied by the timing controller 400 and the pulse wave Pul1 and the pulse wave Pul2, thereby controlling the flow of the inrush current according to the width of the pulse wave Pul1 and the pulse wave Pul2. The internal power supply 100 receives the supply voltage VDD as an input and generates a first voltage. The first voltage includes a positive voltage and a negative voltage. For clarity of description, the first positive voltage is represented by VSP and the first negative voltage is represented by VSN. In some exemplary embodiments, internal power supply 100 may be a switching mode power supply (SMPS), but in other embodiments may be implemented with pulse width modulation.

The charge pump 200 alternately performs charging and discharging in response to the clock signal CP_CK applied from the timing controller 400, thereby boosting the first voltage and generating a second voltage. The second voltage includes a positive voltage and a negative voltage. For clarity of description, the second positive voltage is represented by VGH and the second negative voltage is represented by VGL. In various embodiments, the charge pump 200 can be implemented in different ways.

The inrush current controller 300 receives the first positive voltage VSP from the internal power supply 100, compares the first positive voltage VSP with the selection reference voltage VREF_SEL, and outputs the pulse width modulation control signal Pul_CON to the internal power supply 100.

The timing controller 400 applies a plurality of preset pulse waves Pul1 and pulse waves Pul2 having different widths to the internal power supply 100. The internal power supply 100 responds to the pulse width modulation control signal Pul_CON and uses the pulse Pul1 or the pulse Pul2 as the switching pulse LSW to control the amount of inrush current of the input charge pump 200.

2 is a detailed block diagram of the power supply 1000 illustrated in FIG. 1 in accordance with an exemplary embodiment.

Referring to FIG. 2, the internal power supply 100 includes a first voltage generator 150 and a pulse generator 500. The first voltage generator 150 includes a first switch 101, an inductor 102, and a load circuit 103.

The operation of the internal power supply 100 is described below. The switching pulse LSW generated by the pulse wave generator 500 is applied to the control terminal of the first switch 101. When the first switch 101 is turned on, energy from the supply voltage VDD is accumulated on the inductor 102. When the first switch 101 is turned off, the energy accumulated on the inductor 102 is released to the load circuit 103. When this operation takes The first voltage (VSP and VSN) is generated when the predetermined interval is repeated. The first voltage generator 150 divides the first voltage (VSP and VSN) and generates a feedback signal FB_VM. When the switching pulse LSW is generated, the feedback signal FB_VM is applied to the pulse generator 500 and reflected.

The inrush current controller 300 includes a first sampling block 310, a reference voltage generator 320, and a first comparator 350. When the first enable signal REF_EN is not applied to the inrush current controller 300, the pulse generator 500 applies the switching pulse LSW to the first voltage generation according to the feedback signal FB_VM received from the first voltage generator 150. 150. However, when the first enable signal REF_EN is applied to the inrush current controller 300, the inrush current controller 300 generates the pulse width modulation control signal Pul_CON. The pulse wave generator 500 selects the first pulse Pul1 or the second pulse Pul2 having different pulse widths in response to the pulse width modulation control signal Pul_CON, and performs on the selected pulse Pul1 or pulse Pul2 The pulse width is modulated to produce a switching pulse LSW. The switching pulse LSW controls the amount of inrush current supplied to the charge pump 200.

The charge pump 200 boosts the first voltage (VSP and VSN) and outputs a second voltage (VGH and VGL) that is controlled by the controlled pulse wave in the internal power supply 100. The charge pump 200 is enabled and generates a second voltage before the first voltage reaches a preset maximum output due to switching pulses. The structure and operation of the inrush current controller 300 will be described in detail below with reference to FIG.

FIG. 3 illustrates in detail the inrush current controller 300 illustrated in FIG. 2.

Referring to FIG. 3, the inrush current controller 300 includes a first sampling block. 310, a reference voltage generator 320, and a first comparator 350.

The first sampling block 310 responds to the first enable signal REF_EN, and divides the first voltage by using a plurality of resistors connected between the first voltage and the ground, and outputs a comparison target signal S_VSP. The first sampling block 310 is connected between the first voltage output terminal VSP or the output terminal VSN and the ground terminal GND. The first sampling block 310 includes a second switch 311 and a plurality of resistors. When the first enable signal REF_EN is applied to the control end of the second switch 311, the first sampling block 310 uses a resistor to divide the first voltage and outputs a comparison target signal S_VSP, the first voltage from the internal power source. The supplier 100 outputs and inputs it to the charge pump 200.

The illustrative embodiment is not limited to FIG. For example, the first voltage VSP can be its original state as a comparison target signal, or in other embodiments, can be divided according to the level of the selection reference voltage VREF_SEL.

The reference voltage generator 320 outputs the selection reference voltage VREF_SEL in response to the reference voltage selection signal SEL. The reference voltage generator 320 generates a plurality of primary reference voltages VREF_SEL_n to detect the first voltage, and the reference voltage generator 320 includes a first generation block 330 and a selection block 340.

The first generation block 330 generates a plurality of main reference voltages VREF_SEL_n by dividing the supply voltage by a plurality of resistors (ie, the resistor string Rstring), the resistor being connected between the supply voltage terminal VDD and the ground terminal GND. For example, when two target reference values are used, the first generation block 330 generates a first primary reference voltage VREF_SEL1 having a first target reference value and a second primary reference voltage VREF_SEL2 having a second target reference value. Two or more target references can be used at this time value.

The selection block 340 outputs one of the plurality of primary reference voltages VREF_SEL_n in response to the reference voltage selection signal SEL as the selection reference voltage VREF_SEL. The selection block 340 includes a plurality of switches SEL_SW1 and SEL_SW2, each of which is coupled to a reference voltage output. When the first generation block 330 generates at least two main reference voltages VREF_SEL_n, the selection block 340 selectively outputs a selection reference voltage VREF_SEL in response to the reference voltage selection signal SEL. In FIG. 3, the first main reference voltage VREF_SEL1 or the second main reference voltage VREF_SEL2 is selected in response to the reference voltage selection signal SEL and output as the selection reference voltage VREF_SEL. The switch SEL_SW1 and the switch SEL_SW2 can be implemented in different ways.

The first comparator 350 compares the comparison target signal S_VSP from the first sampling block 310 with the selection reference voltage VREF_SEL. When the comparison target signal S_VSP is lower than the selection reference voltage VREF_SEL, the first comparator 350 outputs the pulse width modulation control signal Pul_CON at the first logic level (for example, a low level). When the comparison target signal S_VSP is higher than the selection reference voltage VREF_SEL, the first comparator 350 outputs the pulse width modulation control signal Pul_CON at the second logic level (for example, a high level).

4 is a graph of voltage versus time illustrating the operation of the inrush current controller 300 illustrated in FIG. 2.

Referring to FIG. 4, when the comparison target signal S_VSP is lower than the selection reference voltage VREF_SEL, the first comparator 350 outputs the pulse width modulation control signal Pul_CON at the first logic level. When comparing the target signal S_VSP When the reference voltage VREF_SEL is selected, the first comparator 350 outputs the pulse width modulation control signal Pul_CON at the second logic level.

For example, when the first main reference voltage VREF_SEL1 is input to the first comparator 350 as the selection reference voltage VREF_SEL, the first comparator 350 outputs the first pulse width modulation control signal Pul_CON1. When the second main reference voltage VREF_SEL2 is input to the first comparator 350 as the selection reference voltage VREF_SEL, the first comparator 350 outputs the second pulse width modulation control signal Pul_CON2. The pulse width modulation control signal Pul_CON1 or the pulse width modulation control signal Pul_CON2 is applied to the pulse wave generator 500 in the internal power supply 100. The pulse width modulation control signal Pul_CON is determined by the reference voltage selection signal SEL.

When the pulse width modulation control signal Pul_CON is at a high level, the pulse generator 500 applies the first pulse Pul1 to the switch 101, and when the pulse width modulation control signal Pul_CON is at a low level, the width is first. A second pulse Pul2 different in pulse wave Pul1 is applied to the switch 101.

Therefore, in the soft pulse period of the first pulse Pul1 or the second pulse Pul2, the first voltage (VSP and VSN) of the internal power supply 100 is gradually generated and ends in the soft pulse period. Previously, the charge pump enable signal CP_Sig (also the immediate pulse signal CP_CK and the pulse width modulation control signal Pul_CON) is applied to the charge pump 200 to prevent spike current generation. When the charge pump 200 is enabled in response to the charge pump enable signal CP_Sig, the inrush current gradually flows into the charge pump 200, and since the latch-up effect is prevented, the inrush current is normally converted into a voltage to generate the first Two voltages (VGH and VGL). At this time, the soft pulse period refers to the pulse The period in which the wave width is lower than the preset maximum width. In other words, when the internal power supply 100 generates the first voltage (VSP and VSN) and the charge pump 200 generates the second voltage (VGH and VGL), the soft pulse period starts from the start of the first voltage generation until the second voltage It ends when it is stable. The control operation of the inrush current according to the pulse width modulation control will be described in detail below with reference to FIG.

FIG. 5 is a signal timing diagram illustrating operation of power supply 1000 in accordance with some demonstrative embodiments.

Referring to FIG. 5, the internal power supply 100 and the charge pump 200 receive the clock signal SMPS_CK and the clock signal CP_CK having different frequencies from the timing controller 400, respectively.

When the enable signal REF_EN is applied to the inrush current controller 300, the inrush current controller 300 divides and samples the first voltage VSP output by the internal power supply 100. The inrush current controller 300 compares the selection reference voltage VREF_SEL with the comparison target signal S_VSP. The timing controller 400 generates a first pulse Pul1 and a second pulse Pul2, each having a predetermined different pulse width. For example, the first pulse Pul1 may have a soft pulse width of PW1 and a maximum pulse width of PW_Max, and the second pulse Pul2 may have a soft pulse width of PW2 and a maximum pulse width of PW_Max.

When the timing controller 400 applies the first pulse Pul1 and the second pulse Pul2 to the internal power supply 100, the pulse generator 500 selects the first pulse Pul1 or the second pulse according to the pulse width modulation control signal Pul_CON. The wave Pul2 and the selected first pulse Pul1 or second pulse Pul2 are applied to the control terminal of the first switch 101. In the internal power supply 100 The switching operation is controlled by the pulse width modulation control signal Pul_CON such that when the internal power supply 100 generates the first voltage (VSP and VSN) during the soft pulse period, the charge pump 200 is enabled, and the charge pump 200 Operates during the charge pump operation period. In other words, before the pulse wave (ie, LSW) having the maximum pulse width PW_Max is applied to the first switch 101 in the internal power supply 100, the charge pump 200 starts the operation, and the amount of the inrush current gradually increases, thereby A large amount of current is prevented from flowing instantaneously into the charge pump 200. Therefore, the latch-up effect is prevented.

When there are two reference voltages VREF_SEL1 and VREF_SEL2, two pulse width modulation control signals Pul_CON1 and Pul_CON2 are respectively generated according to the two reference voltages VREF_SEL1 and VREF_SEL2. At this time, the two enable signals CP_Sig1 and CP_Sig2 can be used as the enable signal CP_Sig when the charge pump 200 operates. The pulse width, the number of reference voltages, and the level of the reference voltage are not limited to FIG. 5, and various changes can be made in other embodiments.

FIG. 6 is a block diagram of a power supply 1100 in accordance with other exemplary embodiments.

Referring to FIG. 6, the power supply 1100 includes an internal power supply 100, a charge pump 200, an inrush current controller 300', and a timing controller 400. The description of the power supply 1100 will focus on its differences from the power supply 1000 illustrated in Figures 2 and 3.

The inrush current controller 300' is different from the inrush current controller 300 depicted in Figure 2, and the inrush current controller 300' can use the negative voltage VSN in the first voltage as the input signal. In other words, when the enable signal REF_EN is applied When the current controller 300' is flooded, the inrush current controller 300' performs sampling using the first negative voltage VSN generated by the internal power supply 100 as an input signal to generate a comparison target signal S_VSN, and an inrush current controller. 300' and comparing the comparison target signal S_VSN with the selection reference voltage VREF_SEL, and transmitting the comparison result to the pulse wave generator 500 in the internal power supply 100, so that the amount of inrush current flowing into the charge pump 200 is controlled. At this time, the principle by which the inrush current controller 300' operates is the same as the principle of the inrush current controller 300 illustrated in FIG.

FIG. 7 is a block diagram of a power supply 1200 in accordance with other exemplary embodiments.

Referring to Figure 7, the power supply 1200 includes an internal power supply 100, a charge pump 200, an inrush current controller 300", and a timing controller 400'. The description of the power supply 1200 will focus on Figure 2 and The difference in power supply 1000 illustrated in FIG.

The inrush current controller 300" compares the comparison target signal S_VSP with the selection reference voltage VREF_SEL, and generates a pulse width modulation control signal Pul_CON. The pulse width modulation control signal Pul_CON is applied to the timing controller 400' instead of the figure 1 to 3 are applied to the pulse wave generator 500 in the exemplary embodiment, in addition, the inrush current controller 300" operates according to the principle, and the inrush current shown in FIG. The principle of the controller 300 is the same.

The timing controller 400' stores at least two related information of the preset pulse width, and applies the pulse wave Pul of the pulse width corresponding to the pulse width modulation control signal Pul_CON to the internal power supply 100.

Therefore, the pulse wave Pul is input to the pulse wave generator 500, and is output as the switching pulse wave LSW in the internal power supply 100, so that the first voltages (VSP and VSN) are gradually formed. The clock signal or charge pump enable signal CP_Sig is applied to the charge pump 200 before the end of the soft pulse period of the switching pulse LSW. Thereafter, the inrush current is gradually input to the charge pump 200, preventing the latch-up effect, causing the charge pump 200 to perform a normal boosting operation to generate the second voltage.

FIG. 8 is a flow chart of a power supply method, in accordance with some demonstrative embodiments. Referring to FIG. 8, when the supply voltage VDD is applied to the internal power generator 100 using pulse width modulation, the internal power generator 100 boosts the supply voltage VDD and generates a first voltage VSP. The first voltage VSP is boosted by the charge pump 200 and is generated as a second voltage VGH. At this time, the negative voltage GND, the negative voltage VSN, and the negative voltage VGL are incidentally generated. The internal power supply 100 using pulse width modulation can be a switched power supply (SMPS), but can be implemented in a variety of ways. The charge pump 200 can also be implemented in a variety of ways.

In operation S10, when the internal power generator 100 using the pulse width modulation generates the first voltage, and the first voltage is input to the charge pump 200, the first voltage is split. In operation S11, the first voltage is sampled in response to the first enable signal REF_EN. At this time, the first voltage may be sampled in its original state, or may be generated by the partial pressure of the response selection reference voltage VREF_SEL, but the exemplary embodiment is not limited thereto. The first voltage may be a first positive voltage VSP or a first negative voltage VSN.

In operation S12, at least one main reference voltage VREF_SEL_n Generated from the supply voltage VDD. In operation S13, one of the at least one main reference voltage VREF_SEL_n is output as the selection reference voltage VREF_SEL in response to the reference voltage selection signal SEL.

In operation S14, the comparison target signal S_VSP or the comparison target signal S_VSN obtained by the sampling is compared with the selection reference voltage VREF_SEL, and the pulse width modulation control signal Pul_CON is output. At this time, when the comparison target signal S_VSP or the comparison target signal S_VSN is lower than the selection reference voltage VREF_SEL, the pulse width modulation control signal Pul_CON is output at the low level. When the comparison target signal S_VSP or the comparison target signal S_VSN is higher than the selection reference voltage VREF_SEL, the pulse width modulation control signal Pul_CON is output at a high level.

In operation S15, the internal power supply 100 controls the pulse width in response to the pulse width modulation control signal Pul_CON. At this time, when the pulse width modulation control signal Pul_CON is at the low level, the first pulse Pul1 generated by the timing controller 400 can be selected. When the pulse width modulation control signal Pul_CON is at a high level, the second pulse Pul2 generated by the timing controller 400 can be selected.

Alternatively, when the pulse width modulation control signal Pul_CON is at the low level, the timing controller 400' may select the preset first pulse Pul1 and apply the preset first pulse Pul1 to the internal power supply 100. When the pulse width modulation control signal Pul_CON is at the high level, the timing controller 400' selects the preset second pulse Pul2 and applies the preset second pulse Pul2 to the internal power supply 100.

In operation S16, the amount of inrush current flowing into the charge pump 200 is root It is controlled according to the switching pulse wave LSW obtained by controlling the pulse width. Before the end of the soft pulse period, the charge pump enable signal CP_Sig is applied to the charge pump 200, and in operation S17, since the inrush current is gradually increased, the second voltage (VGH and VGL) is generated without occurrence of a spike. The latch-up effect caused by the current.

FIG. 9 is a block diagram of a power supply 2000 in accordance with other exemplary embodiments. Referring to FIG. 9, the power supply 2000 includes an internal power supply 100', a charge pump 200, an inrush current controller 300, and a timing controller 400. The description of the power supply 2000 will focus on its differences from the power supply 1000 illustrated in Figures 2 and 3.

The internal power supply 100' performs a switching operation in response to the clock signal SMPS_CK applied from the timing controller 400, and controls the flow of the inrush current with the pulse width. The internal power supply 100' includes a first voltage generator 150 and a pulse generator 500'.

The first voltage generator 150 receives the supply voltage VDD and generates a first voltage (VSP and VSN) and a feedback signal FB_VM. The first voltage includes a first positive voltage VSP and a first negative voltage VSN. The pulse generator 500' receives the feedback signal FB_VM and the internal power supply clock signal SMPS_CK, generates a switching pulse LSW, and applies the switching pulse LSW to the first voltage generator 150.

The first voltage (VSP) is output from the internal power supply 100' and is input to the charge pump 200. The inrush current controller 300 receives the first voltage (VSP) and the first enable signal REF_EN, compares the first voltage (VSP) with the selection reference voltage VREF_SEL, and outputs the pulse to the internal power supply 100'. The wave width modulation control signal Pul_CON and the comparison target signal S_VSP. At this time, the pulse width modulation control signal Pul_CON is used to select a soft bias signal associated with the square wave gradient and is applied to the pulse generator 500' to control the pulse width.

The charge pump 200 boosts the first voltage (VSP and VSN) and outputs a second voltage (VGH and VGL) which is controlled in accordance with the controlled pulse wave in the internal power supply 100'. At this time, since the pulse wave LSW is switched, the charge pump 200 is enabled and generates a second voltage before the first voltage reaches the preset maximum output.

FIG. 10 is a detailed block diagram of the power supply 2000 illustrated in FIG.

Referring to FIG. 10, the power supply 2000 includes an internal power supply 100', a charge pump 200, an inrush current controller 300, and a timing controller 400. The description of the power supply 2000 will focus on its differences from those depicted in FIG.

The internal power supply 100' includes a first voltage generator 150 and a pulse generator 500'. The first voltage generator 150 includes a first switch 101, an inductor 102, and a load circuit 103. In operation of the internal power supply 100', the switching pulse LSW generated by the pulse generator 500' is applied to the control terminal of the first switch 101. When the first switch 101 is turned on, energy from the supply voltage VDD is accumulated on the inductor 102. When the first switch 101 is turned off, the energy accumulated on the inductor 102 is released to the load circuit 103. When this operation is repeated at a preset interval, the first voltages (VSP and VSN) are generated. The first voltage generator 150 divides the first voltage (VSP and VSN) and generates a feedback signal FB_VM. The feedback signal FB_VM is It is applied to the pulse wave generator 500' and is reflected in the generation of the switching pulse wave LSW.

The inrush current controller 300 includes a first sampling block 310, a reference voltage generator 320, and a first comparator 350.

When the first enable signal REF_EN is not applied to the inrush current controller 300, the pulse generator 500' in the internal power supply 100' switches according to the feedback signal FB_VM received from the first voltage generator 150. The pulse wave LSW is applied to the first voltage generator 150. However, when the first enable signal REF_EN is applied to the inrush current controller 300, the inrush current controller 300 generates the pulse width modulation control signal Pul_CON. The pulse width modulation control signal Pul_CON is used to select a soft bias signal associated with the square wave slope and is applied to the pulse generator 500' to control the pulse width. The soft bias signal Sig1 is based on the second reference voltage signal VREF_1 SELECTION or VREF_2 SELECTION.

The pulse generator 500' uses pulse width modulation to generate a switching pulse LSW to control the amount of inrush current supplied to the charge pump 200. The principle of operation of the pulse wave generator 500' will be described in detail below with reference to FIG.

FIG. 11 is a block diagram of the pulse wave generator 500' illustrated in FIG.

Referring to Figure 11, the pulse generator 500' includes a sawtooth pulse generator 550, a sawtooth pulse comparison signal generator 560 (e.g., implemented in a multiplexer (MUX)), and a second comparator 502.

The sawtooth pulse generator 550 responds to the pulse width modulation control signal Pul_CON and the second enable signal MAX_PULSE_EN to generate a sawtooth pulse SAW_PULSE having an adjusted slope. At this time, the clock signal SMPS_CK in the internal power supply 100' can be used, and the internal reference can be used. The test voltage VREF_SMPS and the supply voltage VDD are used to generate the sawtooth pulse SAW_PULSE.

The sawtooth pulse comparison signal generator 560 outputs the comparison target signal S_VSP or the feedback signal FB_VM as the sawtooth pulse comparison signal COMP_REF in response to the second enable signal MAX_PULSE_EN.

The second comparator 502 receives the sawtooth pulse SAW_PULSE through the forward end (+), receives the sawtooth pulse comparison signal COMP_REF through the negative end (1), compares the sawtooth pulse SAW_PULSE with the sawtooth pulse comparison signal COMP_REF, and outputs a comparison result. COMP_OUT acts as the switching pulse LSW.

The pulse generator 500' can include an inverter 501. The inverter 501 inverts the comparison result COMP_OUT of the second comparator 502, and outputs a switching pulse LSW suitable for the switching operation of the first voltage generator 150. The structure and operation of the pulse wave generator 500' will be described in detail below with reference to Figs.

FIG. 12 is a schematic diagram showing the internal structure of the pulse wave generator 500' shown in FIG. 11 according to some exemplary embodiments. Referring to Fig. 12, the pulse generator 500' includes a sawtooth pulse generator 550, a sawtooth pulse wave comparison signal generator 560, and a second comparator 502.

The sawtooth pulse generator 550 includes a second generation block 510, a first waveform generator 520, and a second waveform generator 530.

The second generation block 510 generates a plurality of secondary reference voltages by performing voltage division with a plurality of resistors connected between the internal reference voltage VREF_SMPS and the ground GND. At this time, the secondary reference voltage may include the secondary reference voltage VREF1 of the soft bias signal Sig1 and the second The reference voltage VREF2, the maximum bias signal Sig2, and the sawtooth pulse reset reference SAW_CMP_REF are to be referenced.

The first waveform generator 520 includes a bias selection circuit 522, a pull up circuit 524, and a memory 525. The first waveform generator 520 is coupled between the second generating block 510 and the sawtooth pulse output 551. The first waveform generator 520 selects one of the soft bias signal Sig1 and the maximum bias signal Sig2 as the sawtooth pulse basic signal SAW_REF in response to the second enable signal MAX_PULSE_EN, and responds to the bias signal according to the sawtooth pulse basic signal SAW_REF. The BIAS pulls up the ground voltage to generate a first waveform.

The first circuit 521 and the bias selection circuit 522 select the soft bias signal Sig1 selected from the secondary reference voltage in response to the pulse width modulation control signal Pul_CON, or select the maximum bias voltage in response to the second enable signal MAX_PULSE_EN. The signal Sig2 is outputted and the selected signal is output as a sawtooth pulse basic signal SAW_REF.

For example, when the second enable signal MAX_PULSE_EN is at the low level (that is, when the maximum pulse width is not enabled), the soft bias signal Sig1 is output as the sawtooth pulse basic signal SAW_REF. When the second enable signal MAX_PULSE_EN is at a high level (that is, when the maximum pulse width is enabled), the maximum bias signal Sig2 is output as a sawtooth pulse basic signal SAW_REF. The soft bias signal Sig1 is one of the secondary reference voltage VREF1 and the secondary reference voltage VREF2 generated by the second generating block 510. The secondary reference voltage VREF1 and the secondary reference voltage VREF2 are the response pulse width modulation control signals. Pul_CON was chosen. Maximum bias signal The number Sig2 may be one of the preset secondary reference voltages VREF1 and VREF2 generated by the second generation block 510.

The first waveform generator 520 can also include a stabilization circuit 523 for stabilizing the output of the bias signal BIAS. The stabilization circuit 523 can be a buffer that outputs the sawtooth pulse fundamental signal SAW_REF as the bias signal BIAS, but can be implemented in other various ways.

The pull-up circuit 524 is connected between the supply voltage VDD and the sawtooth pulse output terminal X, and pulls up the voltage of the sawtooth pulse wave output terminal in response to the bias signal BIAS. Pull-up circuit 524 can be a switch implemented by a P-type MOS transistor, but can be implemented in different ways.

The memory 525 is connected between the sawtooth pulse output terminal X and the ground GND. The memory 525 stores the pull-up signal and generates a first waveform. The first waveform can be a rising waveform of the sawtooth pulse.

The second waveform generator 530 includes a second sampling block and pull-down circuit 533.

The second sampling block includes a comparator 531 and a latch circuit 532. The second sampling block is connected between the supply voltage VDD and the sawtooth pulse output terminal X to output a down signal f_SAW after resetting the latch circuit 532. The down signal f_SAW is in response to the clock signal SMPS_CK of the internal power supply 100. Obtained by sampling the supply voltage VDD. The comparator 531 compares the sawtooth pulse SAW_PULSE fed back by the sawtooth pulse output terminal X with the preset sawtooth pulse wave reset reference SAW_CMP_REF, and generates a reset signal.

The pull-down circuit 533 is connected between the sawtooth pulse output terminal X and the ground GND, and pulls down the sawtooth pulse wave output in response to the falling signal f_SAW. The voltage at terminal X. The pull-down circuit 533 can be a switch implemented by an N-type gold-oxygen half (NMOS) transistor, but can be implemented in different ways.

The sawtooth pulse comparison signal generator 560 responds to the second enable signal MAX_PULSE_EN, and outputs the comparison target signal S_VSP as a sawtooth pulse during the soft pulse period (when the second enable signal MAX_PULSE_EN is not enabled, that is, at the low level) The comparison signal COMP_REF is output and the feedback signal FB_VM is output as the sawtooth pulse comparison signal COMP_REF during the maximum pulse period (when the second enable signal MAX_PULSE_EN is enabled, that is, at the high level).

As described above, the second comparator 502 receives the sawtooth pulse SAW_PULSE through the forward end (+), and receives the sawtooth pulse comparison signal COMP_REF through the negative end (-), and compares the sawtooth pulse SAW_PULSE with the sawtooth pulse comparison signal COMP_REF. And the comparison result COMP_OUT is output as the switching pulse LSW.

Therefore, when the soft bias signal Sig1 is selected in response to the pulse width modulation control signal Pul_CON, the bias signal BIAS determining the slope of the sawtooth pulse wave is output corresponding to the soft bias signal Sig1.

For example, as the bias signal BIAS rises, the slope of the first waveform also increases. When the gradient of the first waveform is increased, the pulse width of the comparison result COMP_OUT generated by comparing the sawtooth pulse wave SAW_PULSE with the sawtooth pulse wave comparison signal COMP_REF also increases. As a result, since the comparison result COMP_OUT is reversed, the pulse width of the switching pulse LSW is reduced. Conversely, when the bias signal BIAS falls, the slope of the first waveform also decreases. Compare sawtooth pulse waves as the slope of the first waveform decreases The pulse width of the comparison result COMP_OUT generated by SAW_PULSE and the sawtooth pulse comparison signal COMP_REF is also reduced. As a result, since the comparison result COMP_OUT is reversed, the pulse width of the switching pulse wave LSW increases.

The pulse wave generator 500' generates a switching pulse wave LSW applied to the first switch 101 in the internal power supply 100' by controlling the pulse width modulation according to the above principle. The amount of inrush current flowing from the internal power supply 100' and flowing into the charge pump 200 is controlled according to the switching pulse LSW to reduce the spike current. Therefore, the latch-up effect is prevented.

FIG. 13 is a schematic diagram showing an internal structure of a pulse wave generator according to other exemplary embodiments. Referring to Figure 13, the pulse generator 500" includes a sawtooth pulse generator 550', a sawtooth pulse wave comparison signal generator 560, and a second comparator 502. The description of Fig. 13 will focus on its differences from Fig. 12. .

The first waveform generator 520' includes a bias selection circuit 522, a pull up circuit 524, and a memory 525. The first waveform generator 520' is coupled between the second generation block 510 and the sawtooth pulse output 551. The first waveform generator 520' pulls up the ground voltage and generates a first waveform in response to the secondary reference voltage. The secondary reference voltage is selected from the plurality of secondary reference voltages in response to the second enable signal MAX_PULSE_EN.

The bias selection circuit 522 outputs the soft bias signal Sig1 or the maximum bias signal Sig2 as the bias signal BIAS in response to the second enable signal MAX_PULSE_EN. The soft bias signal Sig1 is the secondary reference voltage VREF1 and the secondary reference voltage generated by the second generating block 510. One of VREF2, the secondary reference voltage VREF1 and the secondary reference voltage VREF2 are selected in response to the pulse width modulation control signal Pul_CON.

Unlike the first waveform generator 520 illustrated in FIG. 12, the first waveform generator 520' illustrated in FIG. 13 also includes a second circuit 540 that generates a maximum bias signal Sig2.

The second generating block 510 generates a secondary reference voltage in response to the level selection signal REF_SEL, and the second circuit 540 outputs a maximum bias signal Sig2 selected from the secondary reference voltage. The level selection signal REF_SEL is N bits in length, where N is a natural number of 2 or greater. The total voltage of the second generating block 510 can be divided into N voltages, and the level selection signal REF_SEL can select one of the N voltages. The second circuit 540 can include a decoder 541 and a level shifter 542, but can be implemented in different ways.

The first waveform generator 520' may also include a stabilization circuit 523 for stabilizing the output of the bias signal BIAS. The stabilization circuit 523 can include a buffer.

Therefore, the maximum bias signal Sig2 can be set in various ways according to the characteristics of the first voltage (VSP) or the power supply 2000. In other words, the second circuit 540 and the pulse wave generator 500" including the second circuit 540 can control the slope of the sawtooth pulse wave according to a physical environment such as heat and temperature that may change with operation, and reset the maximum pulse wave width PW_Max.

14A through 14C are signal timing diagrams illustrating operation of a power supply in accordance with other exemplary embodiments. For clarity of description, assume that the secondary reference voltage VREF1 is higher than the secondary reference voltage VREF2.

Figure 14A shows the operation of this signal timing diagram, which is a secondary reference The operation when the voltage VREF1 is selected as the sawtooth pulse basic signal SAW_REF in response to the pulse width modulation control signal Pul_CON.

When the second enable signal MAX_PULSE_EN is in the low level soft pulse period, when the pulse width modulation control signal Pul_CON is at the low level, the first circuit 521 selects the secondary reference voltage VREF1. The secondary reference voltage VREF1 is transmitted to the stabilization circuit 523 and outputted by the stabilization circuit 523 as a bias signal BIAS. The latch circuit 532 samples the supply voltage VDD in response to the clock signal SMPS_CK of the internal power supply 100, so that the down signal f_SAW is generated. Pull-up circuit 524 and memory 525 generate a first waveform (ie, a rising waveform) in response to bias signal BIAS. The pull-down circuit 533 generates a second waveform, that is, a falling waveform, in response to the falling signal f_SAW, so that the first sawtooth pulse SAW_PULSE@VREF1 is generated according to the secondary reference voltage VREF1. The first sawtooth pulse SAW_PULSE@VREF1 and the sawtooth pulse comparison signal COMP_REF are supplied to the forward terminal (+) and the negative terminal (-), respectively, and are compared by the second comparator 502. The second comparator 502 outputs a first comparison result COMP_OUT1. At this time, when the first sawtooth pulse wave SAW_PULSE@VREF1 is higher than the sawtooth pulse wave comparison signal COMP_REF, the first comparison result COMP_OUT1 is output at a high level, and when the first sawtooth pulse wave SAW_PULSE@VREF1 is lower than the sawtooth pulse wave comparison signal COMP_REF At the time, it is output at a low level. The first comparison result COMP_OUT1 is inverted by the inverter 501 and output as the first switching pulse LSW1.

The operation shown in the timing diagram of FIG. 14B is that the secondary reference voltage VREF2 is selected in response to the pulse width modulation control signal Pul_CON. The operation when the sawtooth pulse wave basic signal SAW_REF.

The second sawtooth pulse SAW_PULSE@VREF2 is generated according to the same principle as described above with reference to FIG. 14A. However, since the secondary reference voltage VREF2 is lower than the secondary reference voltage VREF1, the slope of the second sawtooth pulse SAW_PULSE@VREF2 is smaller than the slope of the first sawtooth pulse SAW_PULSE@VREF1. The second comparison result COMP_OUT2 and the second switching pulse wave LSW2 are generated according to the second sawtooth pulse wave SAW_PULSE@VREF2.

14C is a timing diagram of the signal, when the secondary reference voltage VREF1 is selected as the sawtooth pulse basic signal SAW_REF, and the secondary reference voltage VREF2 is selected as the sawtooth pulse basic signal SAW_REF. The difference.

Compared with when the secondary reference voltage VREF2 is selected, the sawtooth pulse basic signal SAW_REF is higher when the secondary reference voltage VREF1 is selected, so the slope of the first sawtooth pulse SAW_PULSE@VREF1 is greater than the second sawtooth pulse SAW_PULSE The slope of @VREF2. The first sawtooth pulse SAW_PULSE@VREF1 or the second sawtooth pulse SAW_PULSE@VREF2 is compared with the sawtooth pulse comparison signal COMP_REF to produce a comparison result COMP_OUT. In detail, when the first sawtooth pulse SAW_PULSE@VREF1 or the second sawtooth pulse SAW_PULSE@VREF2 is higher than the sawtooth pulse comparison signal COMP_REF, the comparison result COMP_OUT is output at a high level. When the first sawtooth pulse SAW_PULSE@VREF1 or the second sawtooth pulse SAW_PULSE@VREF2 is lower than the sawtooth pulse comparison signal COMP_REF When the comparison result COMP_OUT is output at the low level. Since the slope of the first sawtooth pulse wave SAW_PULSE@VREF1 is larger than the slope of the second sawtooth pulse wave SAW_PULSE@VREF2, when the first sawtooth pulse wave SAW_PULSE@VREF2 is used, when the first sawtooth pulse wave SAW_PULSE@VREF1 is used, The comparison result COMP_OUT has a larger pulse width. The comparison result COMP_OUT is inverted by the inverter 501 and output as the switching pulse LSW. Therefore, the pulse width of the switching pulse LSW decreases as the slope of the sawtooth pulse SAW_PULSE increases.

As described above, in the soft pulse period of the second enable signal MAX_PULSE_EN in the low level, the slope of the sawtooth pulse SAW_PULSE is controlled by the pulse width modulation control signal Pul_CON, so that the width of the switching pulse LSW is controlled.

FIG. 15 is a signal timing diagram illustrating operation of a power supply in accordance with other exemplary embodiments.

Referring to FIG. 4 and FIG. 15, the clock signal SMPS_CK generated by the timing controller 400 has different frequencies from the clock signal CP_CK, and is applied to the internal power supply 100 and the charge pump 200, respectively.

When the comparison target signal S_VSP is lower than the selection reference voltage VREF_SEL, the first comparator 350 in the inrush current controller 300 outputs the pulse width modulation control signal Pul_CON at the low level, and when the comparison target signal S_VSP is higher than the selection reference voltage When VREF_SEL, the pulse width modulation control signal Pul_CON is output at a high level.

For example, as shown in FIG. 4, when the first main reference voltage VREF_SEL1 is input as the selection reference voltage VREF_SEL to the first ratio When the comparator 350 is turned on, the first comparator 350 outputs the first pulse width modulation control signal Pul_CON1. When the second main reference voltage VREF_SEL2 is input to the first comparator 350 as the selection reference voltage VREF_SEL, the first comparator 350 outputs the second pulse width modulation control signal Pul_CON2. The first pulse width modulation control signal Pul_CON1 or the second pulse width modulation control signal Pul_CON2 is applied to the pulse wave generator 500 in the internal power supply 100.

When the second enable signal MAX_PULSE_EN at the low level is input to the second circuit 522, and the first pulse width modulation control signal Pul_CON1 is input to the first circuit 521, if the first pulse width modulation control signal Pul_CON1 is at the low level The pulse wave generator 500 selects the voltage VREF1 from the secondary reference voltage as the soft bias signal Sig1, and outputs the first switching pulse wave LSW1 having the first pulse width PW1 according to the soft bias signal Sig1. On the other hand, if the first pulse width modulation control signal Pul_CON1 is at a high level, the pulse generator 500 selects the voltage VREF2 from the secondary reference voltage as the soft bias signal Sig1, and outputs the first according to the soft bias signal Sig1. The second switching pulse wave LSW2 of the two pulse width PW2.

When the second enable signal MAX_PULSE_EN at the high level is input to the second circuit 522, the pulse generator 500 responds to the level selection signal REF_SEL and selects the maximum bias signal Sig2 from the secondary reference voltage, and according to the maximum bias signal. Sig2 outputs a switching pulse LSW1 having a maximum pulse width PW_MAX or a switching pulse LSW2.

The internal power supply 100 generates and outputs according to the switching pulse wave LSW. The first voltage (VSP and VSN) of the charge pump 200 and the inrush current. When the inrush current is gradually supplied to the charge pump 200, the charge pump 200 is enabled before the switching pulse wave LSW having the maximum pulse width PW_MAX is generated, so that a large amount of current is not instantaneously input to the charge pump 200. Therefore, the latch-up effect is prevented. In the exemplary embodiment, one of the voltages VREF1 and VREF2 is taken as the soft bias signal Sig1 according to the state of the pulse width modulation control signal Pul_CON, but the illustrative embodiment is not limited thereto. In other exemplary embodiments, the pulse width, the number of reference voltages as soft bias signals, and the level of the reference voltage can be varied.

Figure 16 is a block diagram of a power supply 2000' in accordance with other exemplary embodiments.

Referring to Fig. 16, a power supply 2000' includes an internal power supply 100', a charge pump 200, and a timing controller 400. The description of the power supply 2000' illustrated in Fig. 16 will focus on its differences from the power supply 2000 illustrated in Fig. 9.

The power supply 2000' illustrated in Fig. 16 is different from the power supply 2000 illustrated in Fig. 9, and the power supply 2000' does not include the inrush current controller 300. The internal power supply 100' includes a first voltage generator 150 and a pulse wave module 600. The pulse wave module 600 includes a pulse wave generator 500 and a control signal generator 650.

The internal power supply 100' applies a first voltage (VSP) to the pulse modulation module 600 and the charge pump 200. The control signal generator 650 of the pulse wave module 600 generates a control signal SEL_Sig to control the pulse width modulation according to the first voltage (VSP). Pulse generator 500 responds to control The signal SEL_Sig generates a soft bias signal Sig1, and generates a switching pulse LSW whose pulse width corresponds to the soft bias signal Sig1. The control signal SEL_Sig can be two bits in length, but can be implemented in a variety of other ways.

In other words, the power supply 2000' controls the amount of inrush current flowing into the charge pump 200 by controlling the pulse width modulation of the internal power supply 100 in accordance with the first voltage without using the inrush current controller 300.

FIG. 17 is a flowchart of a power supply method according to other exemplary embodiments.

Referring to FIG. 17, the power supply method is performed by a power supply (which includes an internal power supply 100' that performs a switching operation) and a charge pump 200.

In operation S100, when the first enable signal REF_EN is applied to the inrush current controller 300, the comparison target signal S_VSP is generated. In operation S110, the inrush current controller 300 generates a selection reference voltage VREF_SEL from the supply voltage VDD. In operation S120, the inrush current controller 300 compares the comparison target signal S_VSP with the selection reference voltage VREF_SEL, and generates a pulse width modulation control signal Pul_CON.

In operation S130, the pulse width modulation control signal Pul_CON is applied to the internal power supply 100, and the pulse generator 500 in the internal power supply 100 adjusts the control signal according to the second enable signal MAX_PULSE_EN and the pulse width modulation. Pul_CON, uses a pull-up operation to generate the first waveform, the rising waveform. At this time, the slope of the first waveform is changed according to the soft bias signal Sig1, and the soft bias signal Sig1 is selected according to the pulse width modulation control signal Pul_CON. In operation S140, the pulse generator 500 According to the clock signal SMPS_CK of the internal power supply 100, the second waveform, that is, the falling waveform, is generated by pulling down the first waveform, and in operation S150, the sawtooth pulse SAW_PULSE combining the first waveform and the second waveform is generated. Meanwhile, in operation S160, in order to fine-tune the control of the inrush current, the pulse generator 500 selects the comparison target signal S_VSP or the feedback signal FB_VM as the sawtooth pulse comparison signal COMP_REF in response to the second enable signal MAX_PULSE_EN. In operation S170, the pulse generator 500 compares the sawtooth pulse SAW_PULSE with the sawtooth pulse comparison signal COMP_REF and generates a switching pulse LSW. The width of the switching pulse LSW is controlled according to the slope of the sawtooth pulse SAW_PULSE.

In operation S180, the internal power supply 100 generates a first voltage (VSP and VSN) and an inrush current in response to the switching pulse LSW. In operation S190, the charge pump 200 generates a second voltage from the first voltage and the inrush current. Therefore, before the switching pulse wave LSW having the maximum pulse width PW_MAX is generated, the operation of the charge pump 200 is enabled in accordance with the amount of inrush current, so that the latch-up effect of the charge pump 200 is prevented.

18A and 18B are schematic diagrams showing waveforms in the power supply 1000, and timing diagrams of input signals in the power supply 1000, in accordance with some demonstrative embodiments. Referring to FIGS. 18A and 18B, in the soft pulse period A, in the operation in which the internal power supply 100 uses the pulse width modulation to control the amount of the inrush current input to the charge pump 200, the pulse width is according to the A voltage (VSP) level is controlled.

In detail, referring to FIG. 18A, the comparison target signal obtained by sampling the first voltage (VSP) output from the internal power supply 100 is obtained. When S_VSP is higher than the selection reference signal VREF_SEL, the charge pump 200 is enabled and generates a second voltage (VGH and VGL). At this time, the energy stored in the capacitor 102 is limited by the control pulse width modulation, thereby preventing the spike current from occurring when the power supply 1000 is powered on.

Referring to FIG. 18B, the energy from the supply voltage VDD is limitedly supplied to the capacitor 102 in the internal power supply 100 in accordance with the soft pulse width PW of the pulse wave, so that the first voltage (VSP) is in the soft pulse period A gradually increase. When the first voltage (VSP) reaches at least the preset level, the internal power supply 100 enables the charge pump 200 to be activated in the soft pulse period A due to the operation of the inrush current controller 300 or the pulse generator 500. The internal power supply 100 operates and supplies an inrush current to the charge pump 200. Only when the energy of the capacitor 102 reaches the preset maximum level, the internal power supply 100 uses the maximum pulse width PW_MAX of the pulse wave at the maximum pulse period B to increase the inrush current supplied to the charge pump 200, so that the latch is latched. The effect is prevented. At this time, in different embodiments, the pulse width PW and the pulse width PW_MAX may change the design.

19 is a diagram of an output signal of a power supply, in accordance with some demonstrative embodiments.

Referring to FIG. 19, when the first voltages (VSP and VSN) and the second voltages (VGH and VGL) are generated from the supply voltage VDD, no latch-up effect occurs.

The comparison target signal S_VSP is obtained by sampling the first voltage, and the switching pulse LSW reflects the comparison result of the selection reference voltage VREF_SEL and the comparison target signal S_VSP; in detail, when the enable signal REF_EN is applied When applied to the inrush current controller 300, the switching pulse LSW is applied to the control terminal of the first switch 101 in the internal power supply 100 such that the first voltage (VSP) is gradually formed from the soft pulse start point. When the first voltage (VSP) reaches at least the preset level, the internal power supply 100 enables the charge pump 200 at the charge pump enable point before the end of the soft pulse period, so that the inrush current gradually flows into the charge pump 200. . Therefore, in the case where the latch-up effect does not occur, the first voltage is normally boosted, and the second voltage (VGH) is generated. The negative voltage VSN and the negative voltage VGL are generated according to the same principle as described above.

FIG. 20 is a block diagram of a display system 4000 including a power supply 1000, in accordance with some demonstrative embodiments. Referring to FIG. 20, the display system 4000 includes a panel 1, a source driver 3, a gate driver 2, a controller 4, and a power supply 1000.

The panel 1 includes a plurality of data lines, a plurality of gate lines, and a plurality of pixels connected to the data lines and the gate lines.

The source driver 3 generates an analog voltage for driving the data line (or the source line) in the panel 1 in response to the control signal output from the controller 4 and the voltage output from the power supply 1000.

The gate driver 2 responds to the control signal outputted by the controller 4 and the voltage output from the power supply 1000, and sequentially drives the gate line (or scan line) in the panel 1 so that the analog voltage output from the source driver 3 is Available to pixels.

The power supply 1000 described with reference to FIGS. 1 through 17 supplies a boosted voltage (ie, a second voltage) to the source driver 3 or the gate driver 2 in response to a signal output from the controller 4. Controller 4 generates timing control signals to control The operation timing of the data line connected to the source driver 3 and the operation timing of the gate line connected to the gate driver 2.

21 is a block diagram of a display system 4000' including a power supply 1000, in accordance with other exemplary embodiments. Referring to Figure 21, display system 4000' includes panel 1 and display driver 5.

The display driver 5 includes a source driver 3', a gate driver 2', a controller 4', and a power supply 1000. The display driver 5 can be implemented as a single wafer or in a package as illustrated in FIG. 21, but the illustrative embodiments are not limited thereto.

22 is a block diagram of an electronic device including a power supply, in accordance with some demonstrative embodiments. Referring to FIG. 22, the electronic device 5000 includes a power supply 1000, a central processing unit (CPU) 5100, a memory device 5200, an input/output interface unit 5300, and a bus bar 5400.

The central processing unit 5100 can control the data exchange between the power supply 1000, the memory device 5200, and the input/output interface unit 5300 through the bus bar 5400.

The memory device 5200 can be implemented as a non-volatile memory device. Non-volatile memory devices can include a plurality of non-volatile memory cells.

Each non-volatile memory cell can be implemented as an electrically erasable EEPROM (Electrically Erasable Programmable Read-Only Memory (EEPROM), a flash memory, or a magnetic random access memory (Magnetic RAM). MRAM), spin-transfer torque magnetic random access memory (Spin-Transfer Torque MRAM, STT MRAM), conductive bridging RAM (CBRAM), ferroelectric random access memory (FRAM), phase change called Ovonic Unified Memory (OUM) Random Change RAM (PRAM), Resistive RAM (RRAM or ReRAM), Nanotube RRAM, Polymer Random Access Memory Body RAM (PoRAM), Nano Floating Gate Memory (NFGM), holographic memory, Molecular Electronics Memory, or Insulation Resistance Memory ( Insulator Resistance Change Memory).

The electronic device 5000 can be a personal computer (PC), a portable computer, a portable mobile communication device, or a consumer equipment (CE). Portable mobile communication devices include personal digital assistants (PDAs) and portable multimedia players (PMPs). The electronic device 5000 can also be an e-book, a gaming device, a game controller, a navigator, or an electronic musical instrument.

The inventive concept can be implemented as a hardware or a soft body, or a combination of a hardware and a soft body. The inventive concept can also be embodied as a computer readable code on a computer readable medium. A computer readable recording medium is any data storage device that stores data as a program that can later be read by a computer system. Examples of computer readable recording media include read only memory (ROM), random access memory (RAM), light Disc drives, tapes, flexible disks, and optical data storage devices. The computer readable recording medium can also be distributed over a network coupled computer system such that the computer readable code is stored and executed in a decentralized manner. Moreover, those skilled in the art to which the present invention pertains can readily understand functional programs, codes, and code segments that accomplish the inventive concept.

As described above, according to some exemplary embodiments, the pulse width is based on a comparison of the input signal of the charge pump with the selected reference voltage, and the amount of the inrush current input to the charge pump is controlled by the pulse width. Control, thereby preventing the latch-up effect from occurring in the power supply. Therefore, the power supply does not require an external Schottky diode, thereby reducing the manufacturing price. In addition, the internal Schottky diode can be removed from the power supply, resulting in a reduced wafer size. In addition, the peak current during charge pump operation is reduced, so that the contact pressure is reduced and the power consumption is also reduced.

While the present invention has been described and illustrated in the foregoing the embodiments of the embodiments of the invention Various changes.

1‧‧‧ panel

2, 2'‧‧ ‧ gate driver

3, 3'‧‧‧ source driver

4, 4'‧‧‧ controller

5‧‧‧ display driver

100, 100'‧‧‧ internal power supply

101‧‧‧First switcher

102‧‧‧Inductors

103‧‧‧Load circuit

150‧‧‧First voltage generator

200‧‧‧Charge pump

300, 300', 300" ‧ ‧ inrush current controller

310‧‧‧First sampling block

311‧‧‧Second switcher

320‧‧‧reference voltage generator

330‧‧‧First generation square

340‧‧‧Selection box

350‧‧‧First comparator

400‧‧‧Sequence Controller

500, 500', 500" ‧ ‧ pulse generator

501‧‧‧ reverser

502‧‧‧Second comparator

510‧‧‧second generation square

520‧‧‧First waveform generator

521‧‧‧First circuit

522‧‧‧ bias selection circuit

523‧‧‧Stable circuit

524‧‧‧ Pull-up circuit

525‧‧‧ memory

530‧‧‧Second waveform generator

531‧‧‧ Comparator

532‧‧‧Latch circuit

533‧‧‧ Pulldown circuit

540‧‧‧Second circuit

541‧‧‧Decoder

542‧‧‧ Position shifter

550‧‧‧Sawtooth pulse generator

551‧‧‧Sawtooth pulse output

560‧‧‧Sawtooth pulse wave comparison signal generator

600‧‧‧ Pulse Module

650‧‧‧Control signal generator

1000, 1100, 1200, 2000, 2000'‧‧‧ power supply

4000, 4000'‧‧‧ display system

5000‧‧‧Electronic equipment

5100‧‧‧Central Processing Unit

5200‧‧‧ memory devices

5300‧‧‧Input/Output Interface Unit

5400‧‧ ‧ busbar

A, Soft_Pulse‧‧‧ soft pulse period

B, Max_Pulse‧‧‧Maximum pulse period

BIAS‧‧‧ bias signal

COMP_REF‧‧‧Sawtooth pulse comparison signal

COMP_OUT‧‧‧ comparison results

COMP_OUT1‧‧‧ first comparison result

COMP_OUT2‧‧‧ second comparison result

CP_CK, SMPS_CK‧‧‧ clock signal

CP_Sig1, CP_Sig2‧‧‧Enable signal

FB_VM‧‧‧ feedback signal

f_SAW‧‧‧Descent signal

GND‧‧‧ ground terminal

LSW‧‧‧Switch Pulse

LSW1‧‧‧First switching pulse wave

LSW2‧‧‧Second switching pulse wave

MAX_PULSE_EN‧‧‧Second enable signal

MUX‧‧‧Multiplexer

Pul1, Pul2‧‧‧ pulse wave

Pulse width modulation control signal of Pul1_Sel‧‧‧ first logic level (low level)

Pulse width modulation control signal of Pul2_Sel‧‧‧second logic level (high level)

Pul_CON‧‧‧ pulse width modulation control signal

Pul_CON1‧‧‧First pulse width modulation control signal

Pul_CON2‧‧‧Second pulse width modulation control signal

PW1‧‧‧first pulse width

PW2‧‧‧second pulse width

PW_Max‧‧‧Maximum pulse width

REF_EN‧‧‧First enable signal

REF_SEL‧‧‧ quasi-selection signal

SEL_Sig‧‧‧Control signal

SAW_CMP_REF‧‧‧Sawtooth Pulse Reset Reference

SAW_PULSE‧‧‧Sawtooth pulse

SAW_PULSE@VREF‧‧‧Sawtooth pulse generated from reference voltage

SAW_PULSE@VREF1‧‧‧First sawtooth pulse

SAW_PULSE@VREF2‧‧‧Second sawtooth pulse

SAW_REF‧‧‧Sawtooth pulse basic signal

SAW_REF@VREF1‧‧‧Saw-tooth pulse basic signal generated according to the secondary reference voltage VREF1

SAW_REF@VREF2‧‧‧Saw-tooth pulse basic signal generated according to secondary reference voltage VREF2

SEL‧‧‧reference voltage selection signal

SEL_SW1, SEL_SW2‧‧‧ switcher

Sig1‧‧‧Soft bias signal

Sig2‧‧‧Maximum bias signal

S_VSP‧‧‧ comparison target signal

VDD‧‧‧ supply voltage

VGH‧‧‧second voltage (second positive voltage)

VGL‧‧‧second voltage (second negative voltage)

VREF1, VREF2‧‧‧ secondary reference voltage

VREF_1 SELECTION‧‧‧second reference voltage signal

VREF_2 SELECTION‧‧‧second reference voltage signal

VREF_SEL‧‧‧Select reference voltage

VREF_SEL1‧‧‧ first main reference voltage

VREF_SEL2‧‧‧Second main reference voltage

VREF_SMPS‧‧‧ internal reference voltage

Rstring‧‧‧ resistor string

VSN‧‧‧ first voltage (first negative voltage)

VSP‧‧‧ first voltage (first positive voltage)

X‧‧‧Sawtooth pulse output

FIG. 1 is a block diagram of a power supply in accordance with some demonstrative embodiments.

2 is a detailed block diagram of the power supply shown in FIG. 1 according to an exemplary embodiment.

FIG. 3 illustrates in detail the inrush current controller illustrated in FIG. 2.

4 is a graph of voltage versus time, which is depicted in FIG. The operation of the inrush current controller.

FIG. 5 is a signal timing diagram illustrating operation of a power supply in accordance with some demonstrative embodiments.

FIG. 6 is a block diagram of a power supply in accordance with other exemplary embodiments.

FIG. 7 is a block diagram of a power supply in accordance with other exemplary embodiments.

FIG. 8 is a flow chart of a power supply method, in accordance with some demonstrative embodiments.

9 is a block diagram of a power supply in accordance with other exemplary embodiments.

FIG. 10 is a detailed block diagram of the power supply shown in FIG. 9 according to an exemplary embodiment.

FIG. 11 is a block diagram of the pulse wave generator illustrated in FIG. 10, according to an exemplary embodiment.

FIG. 12 is a schematic diagram showing the internal structure of the pulse wave generator shown in FIG. 11 according to some exemplary embodiments.

FIG. 13 is a schematic diagram showing the internal structure of the pulse wave generator illustrated in FIG. 11 according to other exemplary embodiments.

14A through 14C are signal timing diagrams illustrating operation of a power supply in accordance with other exemplary embodiments.

FIG. 15 is a signal timing diagram illustrating operation of a power supply in accordance with other exemplary embodiments.

16 is a block diagram of a power supply according to other exemplary embodiments. Figure.

FIG. 17 is a flowchart of a power supply method according to other exemplary embodiments.

18A and 18B are schematic diagrams of waveforms in a power supply and timing diagrams of input signals in a power supply, according to some demonstrative embodiments.

19 is a diagram of an output signal of a power supply, in accordance with some demonstrative embodiments.

20 is a block diagram of a display system including a power supply, in accordance with some demonstrative embodiments.

21 is a block diagram of a display system including a power supply, in accordance with other exemplary embodiments.

22 is a block diagram of an electronic device including a power supply, in accordance with some demonstrative embodiments.

100‧‧‧Internal power supply

101‧‧‧First switcher

102‧‧‧Inductors

103‧‧‧Load circuit

200‧‧‧Charge pump

300‧‧‧Inrush current controller

310‧‧‧First sampling block

320‧‧‧reference voltage generator

350‧‧‧First comparator

400‧‧‧Sequence Controller

500‧‧‧ Pulse Generator

1000‧‧‧Power supply

VSN‧‧‧ first voltage (first negative voltage)

VSP‧‧‧ first voltage (first positive voltage)

VGH‧‧‧second voltage (second positive voltage)

VGL‧‧‧second voltage (second negative voltage)

VDD‧‧‧ supply voltage

LSW‧‧‧Switch Pulse

FB_VM‧‧‧ feedback signal

CP_CK, SMPS_CK‧‧‧ clock signal

Pul1, Pul2‧‧‧ pulse wave

Pulse width modulation control signal of Pul1_Sel‧‧‧ first logic level (low level)

Pulse width modulation control signal of Pul2_Sel‧‧‧second logic level (high level)

REF_EN‧‧‧First enable signal

SEL‧‧‧reference voltage selection signal

S_VSP‧‧‧ comparison target signal

VREF_SEL‧‧‧Select reference voltage

Claims (9)

A power supply device includes: an internal power supply, comprising a first voltage generator, wherein the first voltage generator is configured to generate a first voltage according to a pulse width modulation control signal; and a charge pump for receiving The first voltage generates a second voltage; and an inrush current controller is coupled to the internal power supply and configured to generate the pulse width modulation control signal according to the target signal and the selection reference voltage. The inrush current controller includes: a reference voltage generator for outputting the selection reference voltage in response to a reference voltage selection signal, the reference voltage generator comprising: a first generation circuit that uses a plurality of resistors to divide Pressing a supply voltage, and generating a plurality of primary reference voltages according to dividing the supply voltage; and selecting a circuit that outputs one of the plurality of primary reference voltages in response to the reference voltage selection signal as the selection Reference voltage. The power supply device of claim 1, wherein the inrush current controller comprises: a first sampling circuit for dividing the first voltage in response to the first enable signal, and according to the Pressing to output the target signal; and a first comparator for comparing the target signal with the selected reference voltage and outputting the pulse width modulation control signal. The power supply device of claim 1, wherein the internal power supply responds to the inrush if the timing controller applies a pulse wave having a different pulse width to the internal power supply, respectively The pulse width generated by the current controller modulates the control signal, and one of the pulse waves is selected and the first voltage is generated. The power supply device of claim 1, wherein the first voltage generator is configured to generate a feedback signal, and the internal power supply comprises a pulse wave generator, wherein the pulse wave generator is The pulse signal is generated to generate a pulse wave, and the pulse wave generator includes a sawtooth pulse wave generator for generating a sawtooth pulse wave having a slope, wherein the saw tooth pulse wave is modulated according to the pulse width modulation signal and a second enabler signal; a sawtooth pulse wave comparison signal generator that outputs the target signal or the feedback signal as a sawtooth pulse wave comparison signal in response to the second enable signal; and a second comparator The sawtooth pulse wave is compared with the sawtooth pulse wave to compare signals, and a switching pulse wave is generated. The power supply device of claim 4, wherein the sawtooth pulse generator comprises: a second generating circuit that divides an internal reference voltage by a plurality of resistors and generates the voltage according to the partial pressure a plurality of secondary reference voltages; a first waveform generator coupled between the second generating circuit and the sawtooth pulse output terminal, and selecting among the plurality of secondary reference voltages according to the second enable signal Voltage, and by responding to selected from the majority of the secondary And applying a voltage to the reference voltage to pull up a ground voltage to generate a first waveform; and a second waveform generator connected between the second generating circuit and the sawtooth pulse output end, and by falling in response And pulling down the voltage of the sawtooth pulse wave output to generate a second waveform, the descent signal is generated in the second waveform generator, and the descent signal is sampled according to sampling the supply voltage The voltage is based on the clock signal of the internal power supply. The power supply device of claim 5, wherein the first waveform generator comprises: a bias circuit that outputs the plurality of secondary reference voltages in response to the pulse width modulation control signal One of the signals is a soft bias signal, or outputs a maximum bias signal as a sawtooth pulse basic signal in response to the second enable signal; and a pull-up circuit that pulls up the basic signal in response to the sawtooth pulse The voltage of the sawtooth pulse wave output terminal; and a memory connected between the sawtooth pulse wave output end and the ground end, the memory for storing the pull-up signal and generating the first waveform. The power supply device of claim 5, wherein the first waveform generator comprises: a first circuit that selects and outputs the plurality of secondary references in response to the pulse width modulation control signal One of the voltages is a soft bias signal; the second circuit selects and outputs the plurality of signals in response to the level selection signal One of the plurality of secondary reference voltages as a maximum bias signal; the bias circuit responsive to the second enable signal to output the soft bias signal or the maximum bias signal as a sawtooth pulse a basic signal; and a pull-up circuit that pulls up the ground voltage in response to the sawtooth pulse fundamental signal to generate the first waveform. The power supply device of claim 5, wherein the second waveform generator comprises: a second sampling circuit that performs a reset operation according to the sawtooth pulse wave and the sawtooth pulse wave reset reference, and outputs The falling signal; and a pull-down circuit that pulls down the voltage of the sawtooth pulse output end in response to the pull-down signal. The power supply device of claim 4, wherein the sawtooth pulse wave comparison signal generator outputs the target signal as the saw tooth pulse in response to the second enable signal during a soft pulse period The wave compares the signal and outputs the feedback signal as the sawtooth pulse comparison signal in response to the second enable signal during the maximum pulse period.