TWI549325B - Resistive memeory device and operation method thereof - Google Patents

Description

Resistive memory element and method of operating same

The present invention relates to a semiconductor device and a method of operating the same, and more particularly to a resistive memory device and method of operation thereof.

Non-volatile memory has the advantage that the stored data will not disappear after power-off, so it is a necessary memory element for many electrical products to maintain normal operation. At present, resistive random access memory (RRAM) is a kind of non-volatile memory actively developed in the industry. It has low write operation voltage, short write erase time, long memory time, and non-destructive memory. Sexual reading, multi-state memory, simple structure and small required area have great potential for application in personal computers and electronic devices in the future.

In a resistive random access memory (RRAM), the state of the variable resistance layer is changed by applying a current pulse and a conversion voltage to set a state according to different resistance values (SET state). ) Switch between RESET state and RESET state. The values "0" and "1" are recorded in the memory according to the setting state and the reset state corresponding to the different resistance values. However, due to the higher resistance accuracy required, traditional RRAM actually It is not easy to use as a multi-level memory.

In view of the above, the present invention provides a resistive memory element and a method of operating the same, wherein each memory cell has at least three resistance states and is therefore applicable to the operation of multi-level memory.

The invention provides a resistive memory element comprising a plurality of isolation structures, a plurality of word lines, a conductive layer, a plurality of variable resistance blocks, and a plurality of bit lines. A plurality of isolation structures are disposed in the substrate and extend in the first direction, wherein the width of the active regions varies periodically in the first direction. A plurality of word lines are disposed on the substrate and extend in the second direction. The second direction is different from the first direction. At least one doped region is disposed in the substrate between adjacent two word lines. The conductive layer is disposed on the word line. The conductive layer has a plurality of conductive blocks and a plurality of wires extending in the second direction. The at least one conductive block is disposed between the adjacent two wires, and the wires and the conductive blocks are electrically connected to the doped regions. A plurality of variable resistance blocks are respectively disposed on the conductive block and electrically connected to the conductive block. A plurality of bit lines extending in the first direction are disposed on the conductive layer and electrically connected to the variable resistance block.

In an embodiment of the invention, the word line includes a plurality of first word lines and a plurality of second word lines that are alternately arranged.

The present invention further provides a method of operating a resistive memory element for operating a resistive memory element as described above, the method of operation comprising: applying 0V to a first word line, applying a first when in the first set mode AC voltage to the second character Wire, apply a second AC voltage to the bit line, apply 0V to the substrate, and apply 0V to the wire.

In an embodiment of the invention, the operating method further includes: applying a third alternating voltage to the first word line, applying 0V to the second word line, and applying the second alternating voltage to the second setting mode to The bit line, applying 0V to the substrate, applies 0V to the wire.

In an embodiment of the invention, the operating method further includes: applying a third alternating voltage to the first word line, applying the first alternating voltage to the second word line, and applying the second when in the third setting mode Apply AC voltage to the bit line, apply 0V to the substrate, and apply 0V to the wire.

In an embodiment of the invention, the operating method further includes: applying a fifth alternating voltage to the first word line, applying a sixth alternating voltage to the second word line, and applying 0V to the bit when in the reset mode. The wire, applying 0V to the substrate, applies a fourth alternating voltage to the wire.

The invention further provides a resistive memory element comprising a plurality of memory cells, and each memory cell comprises two gates, one gate node, a variable resistance block, a conductor layer and two source nodes. The two gates have different channel widths. The bungee node is located between the gates. The variable resistance block is electrically connected to the drain node. The conductor layer is electrically connected to the variable resistance block. The two source nodes are respectively located outside the gate.

Based on the above, in the resistive memory element of the present invention, each memory cell has a structure of 2T1R (two transistors and one resistor), and can be operated with multi-level memory by operating at least three resistance states. .

The above described features and advantages of the invention will be apparent from the following description.

10, 20‧‧‧Resistive memory components

100, 200‧‧‧ base

102, 102a, 102b, 202‧‧‧ isolation structure

104, 104a, 104b, 204‧‧‧ active areas

105a, 105b‧‧‧ gate insulation

106a, 106b‧‧‧ gate structure

107a, 107b, 207a, 207b‧‧‧ gate

108‧‧‧Doped area

108a‧‧‧ source area

108b‧‧‧Bungee Area

109a, 109b‧‧‧ cover layer

110, 118, 122, 124‧‧‧ insulation

111a, 111b‧‧‧ spacer

112‧‧‧ Conductive layer

113, 213‧‧‧ wires

115, 215‧‧‧ conductive blocks

117‧‧‧ bottom electrode

119‧‧‧variable resistance layer

121‧‧‧ top electrode

114, 116, 123, 127‧‧‧ conductive plugs

120, 220‧‧‧Variable resistance block

126, 226‧‧‧ bit line

A‧‧‧ memory cell

W1, W2, W3, W4‧‧‧ width

1 is a top plan view of a resistive memory device in accordance with a first embodiment of the present invention.

2A is a schematic cross-sectional view taken along line II' of FIG. 1.

2B is a schematic cross-sectional view taken along line II-II' of FIG. 1.

2C is a schematic cross-sectional view taken along line III-III' of FIG. 1.

FIG. 3 is a schematic diagram showing a current accumulation of the resistive memory element of the first embodiment.

4 is a top plan view of a resistive memory device in accordance with a second embodiment of the present invention.

Fig. 5 is a view schematically showing a current accumulation of the resistive memory element of the second embodiment.

First embodiment

1 is a top plan view of a resistive memory device in accordance with a first embodiment of the present invention. 2A is a schematic cross-sectional view taken along line II' of FIG. 1. 2B is a schematic cross-sectional view taken along line II-II' of FIG. 1. Figure 2C is along Figure 1 A schematic cross-sectional view taken on line III-III'. In FIG. 1, for the sake of clarity, components such as a substrate, a doped region, a conductive plug, an insulating layer, a bit line, and the like are not shown, but the components can be clearly seen in other cross-sections in terms of their configuration/position.

Referring to FIG. 1 and FIG. 2A to FIG. 2C simultaneously, the resistive memory device 10 of the present invention includes a plurality of isolation structures 102, a plurality of gate structures 106a and 106b, a conductive layer 112, and a plurality of variable resistance blocks 120 and more. A strip line 126 and a plurality of insulating layers 110, 118, 122 and 124.

A plurality of isolation structures 102 are disposed in the substrate 100 and extend in the first direction. In an embodiment, the first direction is, for example, the X direction. The isolation structure 102 is, for example, a shallow trench isolation (STI) structure, the material of which includes yttrium oxide. The area between the isolation structures 102 is defined as an active area (AA) 104.

It is to be noted that, in this embodiment, the isolation structure 102 includes a plurality of wavy first isolation structures 102a and a plurality of wavy second isolation structures 102b, and adjacent first isolation structures 102a. It is mirror symmetry with the waveform of the second isolation structure 102b. In an embodiment, the waveforms of the first isolation structure 102a and the second isolation structure 102b are square waves. Of course, it is common knowledge in the art that due to limitations in processes such as lithography etching, the square wave may not be an ideal square wave, but rather a waveform that is substantially similar to a square wave.

In addition, since the waveforms of the adjacent first isolation structure 102a and the second isolation structure 102b are mirror-symmetrical, the active area 104 defined between the first isolation structure 102a and the second isolation structure 102b is not elongated. But by having The block of rules changes. In an embodiment, the active region 104 includes alternating first active block 104a and second active block 104b. The first active block 104a and the second active block 104b are, for example, rectangular blocks, and the width W1 of the first active block 104a is greater than the width W2 of the second active block 104b. The widths W1, W2 of the active region 104 can be regarded as the channel width of the gates 107a, 107b.

More specifically, the active region 104 includes a continuous, alternating first active block 104a and a second active block 104b in a first direction (eg, the X direction) and has a width along a first direction (eg, an X direction) The cycle changes, for example, in the manner of W1, W2, W1, W2, .... In addition, the active region 104 includes a discontinuous, alternating first active block 104a and a second active block 104b in a second direction (such as the Y direction) different from the first direction, and the width thereof is along the second direction. (such as the Y direction) changes periodically, for example, in the manner of W1W2, W1, W2, ....

A plurality of gate structures 106a and 106b extending in the second direction are disposed on the substrate 100. In an embodiment, the second direction is, for example, the Y direction. In an embodiment, the gate structure 106a and the gate structure 106b are alternately arranged with each other. Each of the gate structures 106a includes (from bottom to top) a gate insulating layer 105a, a gate electrode 107a, and a mask layer 109a. Similarly, each gate structure 106b includes (from bottom to top) gate insulating layer 105b, gate 107b, and mask layer 109b. The material of the gate insulating layer 105a/105b includes hafnium oxide. The gates 107a/107b may be of a single layer or a multilayer structure, the material of which includes doped polysilicon, tungsten or a combination thereof. In this embodiment, the gates 107a, 107b each serve as a word line of the resistive memory element 10. The material of the mask layers 109a, 109b includes tantalum nitride. Each of the gate structures 106a, 106b may further include spacers 111a, 111b, respectively. The material of the spacers 111a, 111b includes an insulating material such as tantalum nitride.

Furthermore, at least one doped region 108 is disposed in the substrate 100 between adjacent two word lines (i.e., gates 107a, 107b). In the embodiment of FIG. 1, the four doped regions 108 are disposed in the substrate 100 between adjacent two word lines (ie, the gates 107a, 107b) as an example, but are not used. The invention is defined. In an embodiment, doped region 108 includes a plurality of source regions 108a and a drain region 108b. A section along the line I'I', as shown in Fig. 2A, it can be seen that the source region 108a and the drain region 108b are alternately arranged with each other. A section along the line II-II', as shown in Fig. 2B, only the source region 108a is seen. A section along the line III-III', as shown in Fig. 2C, only shows the drain region 108b.

The insulating layer 110 is disposed on the gate structures 106a, 106b. The material of the insulating layer 110 includes boronphosphosilicate glass (BPSG).

The conductive layer 112 is disposed on the insulating layer 110. The conductive layer 112 has a plurality of conductive blocks 115 and a plurality of wires 113 extending in the second direction. In one embodiment, the wires 113 and the conductive segments 115 are in the same plane, as shown in Figure 2A. However, the invention is not limited thereto. In another implementation, the wires 113 and the conductive segments 115 may also be located in different planes. For example, the wire 113 is in a first plane and the conductive block 115 is in a second plane that is different from the first plane. The material of the conductive layer 112 includes a metal such as aluminum, copper or an alloy thereof.

In addition, at least one conductive block 115 is disposed between two adjacent wires 113. In this embodiment, the four conductive blocks 115 are disposed between the adjacent two wires 113 as an example, but are not intended to limit the present invention. Along the I-I' line The cross section, as shown in FIG. 2A, can be seen that the wires 113 and the conductive blocks 115 are arranged in an alternate configuration.

In addition, the wire 113 and the conductive block 115 are electrically connected to the doping region 108. Specifically, the wire 113 is electrically connected to the source region 108a through the conductive plug 114, and the conductive block 115 is electrically connected to the drain region 108b through the conductive plug 116. The material of the conductive plugs 114, 116 includes copper or tungsten.

The insulating layer 118 is disposed on the conductive layer 112. The material of the insulating layer 118 includes ruthenium oxide.

A plurality of variable resistance blocks 120 are disposed on the insulating layer 118 and respectively correspond to the conductive blocks 115. In an embodiment, the variable resistance block 120 is disposed in the insulating layer 122. The material of the insulating layer 122 includes ruthenium oxide. Each variable resistance block 120 includes a bottom electrode 117, a top electrode 121, and a variable resistance layer 119 between the bottom electrode 117 and the top electrode 121. The material of the bottom electrode 117 includes titanium nitride (e.g., TiN). The material of the variable resistance layer 119 includes a transition metal oxide such as HfO ₂ or ZrO ₂ . The material of the top electrode material layer 121 includes titanium nitride (for example, Ti/TiN).

In addition, the variable resistance block 120 is electrically connected to the conductive block 115. Specifically, the variable resistance block 120 is electrically connected to the conductive block 115 through the conductive plug 123. The material of the conductive plug 123 includes copper or tungsten.

The insulating layer 124 is disposed on the variable resistance block 120. The material of the insulating layer 124 includes yttrium oxide.

A plurality of bit lines 126 are disposed on the insulating layer 124 and extend in the first direction. The material of the bit line 126 includes a metal such as copper, aluminum or an alloy thereof. Bit line 126 is electrically connected to the variable resistance block 120. Specifically, the bit line 126 is electrically connected to the variable resistance block 120 through the conductive plug 127. The material of the conductive plug 127 includes copper or tungsten.

In this embodiment, the insulating layers 110, 118, 122, and 124 together with the insulating spacers 111a, 111b can connect the word lines (ie, the gates 107a, 107b) to the conductive layer 112, the variable resistance block 120, and the bit lines. 126 are electrically isolated from each other.

As shown in FIG. 1 and FIG. 2A, the memory cell A of the present invention is a 2T1R (two transistors and one resistor) structure including two gates 107a, 107b and a variable resistance block 120. More specifically, the memory cell A of the present invention includes a gate 107a and a gate 107b (both as word lines), two wires 113 (both as source lines), a conductive block 115, and a variable resistor. Block 120 and a bit line 126. Further, adjacent memory cells A share a isolation structure 102a or 102b in the second direction (e.g., the Y direction). In addition, since the adjacent memory cells A share a wire 113 in the first direction (e.g., the X direction), they constitute a back-to-back structure.

FIG. 3 is a schematic diagram showing a current accumulation of the resistive memory element of the first embodiment. In the resistive memory device of the first embodiment, each of the memory cells A has a 2T1R structure, and the channel widths of the two transistors are different, so that the modes of the transistors can be turned on or turned on together with the bits. The voltage setting of the line, the wire and the substrate is such that each memory cell A is operated to have four resistance states (as shown by HRS, LRS1, LRS2, and LRS3 in FIG. 3), so that 2 bits (2 bits) of data can be stored. As an application of multi-level memory.

More specifically, in this embodiment, the channel width W1 of the gate 107a of each memory cell A is greater than the channel width W2 of the gate electrode 107b, so a set voltage is applied to the bit line 126 and the wire 113 and the substrate 100 are applied. In the case of grounding, the gate 107a is turned off and the gate 107b is turned on to have a first low resistance state (labeled as LRS1 of FIG. 3); the gate 107b is turned off and the gate 107a is turned on to have a second low resistance state (marked as shown in FIG. LRS2) of 3; simultaneously opening gate 107a and gate 107b to have a third low resistance state (labeled as LRS3 of FIG. 3). In the case where the bit line 126 and the substrate 100 are grounded, the gate 107a and the gate 107b are simultaneously turned on, and a reset voltage is applied to the wire 113 to have a high resistance state (labeled as HRS of FIG. 3). In other words, the resistance state is: HRS>LRS1>LRS2>LRS3.

Hereinafter, a method of operating the resistive memory element of the first embodiment will be explained. The resistive memory element of FIGS. 1 to 2C described above and the cumulative diagram of FIG. 3 will be specifically described.

When in the first setting (SET) mode (such as LRS1 of FIG. 3), applying 0V to the first word line (eg, gate 107a), applying a first alternating voltage (eg, about 1~3V) to the second character A line (e.g., gate 107b) is applied with a second alternating voltage (e.g., about 1 to 3V) to bit line 126, 0V is applied to substrate 100, and 0V is applied to conductor 113.

When in the second setting mode (such as LRS2 of FIG. 3), a third alternating voltage (eg, about 1~3V) is applied to the first word line (eg, gate 107a), and 0V is applied to the second word line (eg, The gate 107b) applies the second alternating voltage (eg, about 1 to 3V) to the bit line 126, applies 0V to the substrate 100, and applies 0V to the wire 113.

When in the third setting mode (such as LRS3 of FIG. 3), applying the third alternating voltage (eg, about 1~3V) to the first word line (eg, gate 107a), applying Applying a first alternating voltage (eg, about 1~3V) to a second word line (eg, gate 107b), applying the second alternating voltage (eg, about 1~3V) to bit line 126, applying 0V to substrate 100 Apply 0V to the wire 113.

When in the reset mode (such as HRS of FIG. 3), a fifth alternating voltage (eg, about 1~3V) is applied to the first word line (eg, gate 107a), and a sixth alternating voltage is applied (eg, about 1~3V). To the second word line (eg, gate 107b), applying 0V to bit line 126, applying 0V to substrate 100, applying a fourth alternating voltage (eg, about 1 to 3V) to conductor 113.

In the above embodiment, as shown in FIG. 2A, the wire 113, the conductive plug 114 and the source region 108a constitute a source node, and the conductive block 115, the conductive plug 116 and the source region 108b constitute a source node. A drain node. Therefore, in the resistive memory element 10 of the present invention comprising a plurality of memory cells A, each of the memory cells A includes two gates 107a and 107b, a drain node, a variable resistance block 120, and a conductor layer (for example Bit line 126) and two source nodes. The gates 107a and 107b have different channel widths. In an embodiment, the channel width W1 of the gate 107a is greater than the channel width W2 of the gate 107b. The drain node is located between the gates 107a and 107b. The variable resistance block 120 is electrically connected to the drain node. A conductor layer (eg, bit line 126) is electrically coupled to variable resistance block 120. The two source nodes are located outside the gates 107a and 107b, respectively.

Second embodiment

4 is a top plan view of a resistive memory device in accordance with a second embodiment of the present invention. The second embodiment is similar to the first embodiment except that the first The two gates of each of the memory cells of the second embodiment have the same channel width. Specifically, in FIG. 4, the width of the isolation structure 202 is the same, and the width of the active region 204 is the same, so the channel width W3 of the gate 207a is equal to the channel width W4 of the gate 207b. In FIG. 4, components such as a substrate, a doped region, a conductive plug, an insulating layer, and the like are not shown for clarity of explanation. In addition, the cross-sections shown in the lines I-I', II-II', and III-III' of FIG. 4 are similar to those of FIGS. 2A, 2B, and 2C, and will not be described again.

As shown in FIG. 4, the memory cell A of the second embodiment is also a 2T1R structure including two gates 207a, 207b and a variable resistance block 220. More specifically, the memory cell A of the second embodiment includes a gate 207a and a gate 207b (both as word lines), two wires 213 (both as source lines), a conductive block 215, and a Variable resistance block 220 and one bit line 226. In addition, adjacent memory cells A share an isolation structure 202. In addition, since the adjacent memory cells A share a single wire 213, they constitute a back-to-back structure.

Fig. 5 is a view schematically showing a current accumulation of the resistive memory element of the second embodiment. In the resistive memory device of the present invention, each of the memory cells A has a 2T1R structure, and the channel widths of the two transistors are the same, so that the mode can be turned on or jointly turned on by any of the transistors and matched with the bit lines, The voltage setting of the wire and the substrate is such that each memory cell A is operated to have three resistance states (as shown by HRS, LRS1, and LRS2 in FIG. 5), so that 11⁄2 bits (11⁄2 bits) of data can be stored as multi-order. The application of memory.

More specifically, in this embodiment, the channel width W3 of the gate 207a of each memory cell A is equal to the channel width W4 of the gate 207b, so a set voltage is applied to the bit line. 226 and in the case where the wire 213 is grounded to the substrate 200, one of the open gate 207b and the gate 207a is made to have a first low resistance state (labeled as LRS1 of FIG. 5); at the same time, the gate 207a and the gate 207b are turned on. Has a second low resistance state (labeled LRS2 as in Figure 5). When the bit line 226 and the substrate 200 are grounded, the gate 207a and the gate 207b are simultaneously turned on, and a reset voltage is applied under the wire 213 to have a high resistance state (labeled as HRS of FIG. 5). In other words, the resistance state is: HRS>LRS1>LRS2.

Hereinafter, a method of operating the resistive memory element of the second embodiment will be explained. This will be specifically described using the resistive memory element of Fig. 4 described above and the current accumulation diagram of Fig. 5.

When in the first setting (SET) mode (such as LRS1 of FIG. 5), applying 0V to one of the first word line (eg, gate 207a) and the second word line (eg, gate 207b), applying the first Seven alternating voltages (eg, about 1~3V) to the first word line (eg, gate 207a) or the second word line (eg, gate 207b), applying an eighth alternating voltage (eg, about 1~3V) To the bit line 226, 0 V is applied to the substrate 200, and 0 V is applied to the wire 213.

When in the second setting mode (such as LRS2 of FIG. 5), the seventh alternating voltage (eg, about 1~3V) is applied to the first word line (eg, gate 207a) and the second word line (eg, gate) The pole 207b) applies an eighth alternating voltage (e.g., about 1 to 3 V) to the bit line 226, applies 0 V to the substrate 200, and applies 0 V to the wire 213.

When in the reset mode (such as HRS of FIG. 5), a ninth alternating voltage (eg, about 1~3V) is applied to the first word line (eg, gate 207a) and the second word line (eg, gate 207b). Apply 0V to the bit line 226, apply 0V to the substrate 200, apply the first Ten alternating voltages (eg, about 1 to 3V) to the conductor 213.

In summary, in the resistive memory element of the present invention, each memory cell has a 2T1R structure and can be operated with at least three resistance states, so it can be applied to the operation of multi-level memory.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

10‧‧‧Resistive memory components

102, 102a, 102b‧‧‧ isolation structure

104, 104a, 104b‧‧‧ active area

107a, 107b‧‧‧ gate

113‧‧‧Wire

115‧‧‧ conductive block

120‧‧‧Variable resistance block

A‧‧‧ memory cell

W1, W2‧‧‧ width

Claims (19)

A resistive memory element comprising: a plurality of isolation structures disposed in a substrate and extending in a first direction, wherein an area between the isolation structures is defined as an active area, the active area comprising a continuous, alternating change a first active block and a plurality of second active blocks, wherein the width of the active area changes periodically along the first direction; a plurality of word lines are disposed on the substrate and extend in the second direction At least one doped region is disposed in the substrate between adjacent two word lines, and the second direction is different from the first direction; a conductive layer is disposed on the word line The conductive layer has a plurality of conductive blocks and a plurality of wires extending along the second direction, at least one conductive block is disposed between the adjacent two wires, and the wires and the conductive blocks Electrically connecting with the doped region; a plurality of variable resistance blocks respectively disposed on the conductive block and electrically connected to the conductive block; and a plurality of bit lines disposed on the conductive On the layer, extending along the first direction The variable resistor electrically connected to the block. The resistive memory element of claim 1, wherein the width of the active region varies periodically along the second direction. The resistive memory element of claim 1, wherein the isolation structure comprises a plurality of wavy first isolation structures and a plurality of wavy second isolation structures arranged alternately, and adjacent to the a first isolation structure and the second isolation junction The waveform of the structure is mirror symmetrical. The resistive memory device of claim 3, wherein the waveforms of the first isolation structure and the second isolation structure are square waves. The resistive memory element of claim 1, wherein the second direction is perpendicular to the first direction. The resistive memory device of claim 1, wherein the conductive line of the conductive layer and the conductive block are in the same plane. The resistive memory device of claim 1, wherein the doped region comprises a plurality of source regions and a plurality of drain regions, the wires are electrically connected to the source regions, and The conductive block is electrically connected to the drain region. The resistive memory device of claim 1, wherein the conductive wire and the conductive block are electrically connected to the doped region through a plurality of first conductive plugs. The resistive memory device of claim 1, wherein the variable resistance block is electrically connected to the conductive block through a plurality of second conductive plugs. The resistive memory device of claim 1, wherein the bit line is electrically connected to the variable resistance block through a plurality of third conductive plugs. The resistive memory device of claim 1, wherein each of the variable resistance blocks includes a bottom electrode, a top electrode, and a variable resistance layer between the bottom electrode and the top electrode. The resistive memory device of claim 1, further comprising at least one insulating layer to isolate the word line from the conductive layer, the variable resistance block, and the bit line . The resistive memory element of claim 1, further comprising a plurality of gate channels, the gate channels having at least two widths. The resistive memory element of claim 1, wherein the word line comprises a plurality of first word lines and a plurality of second word lines arranged alternately. A method of operating a resistive memory device for operating a resistive memory device according to claim 14, wherein the operating method comprises: applying 0V to the first character when in the first setting mode A line, applying a first alternating voltage to the second word line, applying a second alternating voltage to the bit line, applying 0V to the substrate, applying 0V to the wire. The method of operating the resistive memory device of claim 15, further comprising: applying a third alternating voltage to the first word line and applying 0V to the second when in the second setting mode A word line, applying the second alternating voltage to the bit line, applying 0V to the substrate, applying 0V to the wire. The method of operating the resistive memory device of claim 16, further comprising: applying the third alternating voltage to the first word line when the third set mode is applied, applying the first AC voltage to the second word line, applying the second alternating voltage to the bit line, applying 0V to the substrate, applying 0V to the lead line. The method of operating the resistive memory device of claim 17, further comprising: applying a fifth alternating voltage to the first word line when the reset mode is applied, applying a sixth alternating voltage to the A second word line, applying 0V to the bit line, applying 0V to the substrate, applying a fourth alternating voltage to the wire. A resistive memory element comprising a plurality of memory cells, each memory cell comprising: two gates having different channel widths; a drain node located between the gates; a variable resistance block, electrical Connected to the drain node; a conductor layer electrically connected to the variable resistance block; and two source nodes respectively located outside the gate.