TWI549129B - 3d nand memory with decoder and local word line drivers - Google Patents

Description

Three-dimensional anti-gate memory with decoder and local word line driver

The present invention relates to a high-density memory device which is proposed to delete a portion of content, and more particularly to a memory device in which a plurality of memory cells are arranged in a three-dimensional array.

Three-dimensional memory devices have evolved into a variety of configurations including vertical channel structures. In the vertical channel structure, a memory cell including a charge storage structure is disposed in a horizontal plane of the conductive string and an adjacent region of a vertical active strip. The conductive string is used as a word line. The vertical active serial includes several channels used by the memory cell.

The memory can include a plurality of planes of memory cells including a plurality of horizontal conductive strips or a plurality of stacked arrays of word lines. The trend to increase memory capacity has led to an increase in the number of horizontal conductive series stacks plus. The horizontal serial selection line is selected by the string select line. Unfortunately, the increase in the number of stacks causes problems with capacitance, noise, and power consumption.

One way to increase the memory capacity without increasing the number of stacks of horizontal conductive strings is to increase the number of planes and the number of staircase contacts. Stair contact access increases the number of planes. However, this method is related to the density of the wires electrically coupled to the step contacts and the decoder. These increased densities lead to challenges in other processes.

At present, it is highly desirable to develop a three-dimensional integrated circuit memory using a vertical channel structure to reduce the disadvantages caused by an increase in memory capacity.

According to various aspects of the technology, a plurality of conductive lines are, for example, a block select line, and a control switch is, for example, a transistor. Other wires (eg, layer select lines) carry a layer select signal to alternately select a particular layer of word lines. Whether the transistor control layer selection line is electrically coupled to different layers of the word line. When the layer select line is alone, all the word lines of the selected layer will be turned on. The combination of the layer selection line and the block selection line can only open the word line of the selected layer. The remaining wires (e.g., string select lines) select a particular stack of conductive strips, such as by activating an access transistor located at the end of the NAND string. (access transistor). Tandem selection line The block selection signals carried by the serial selection signal and the block selection line are selected to select a specific stack of the conductive series. The arrangement of such wires can increase the memory capacity without the above problems. The various aspects of the technology will be described later.

According to an aspect of the present technique, a memory device is provided. The memory device includes a stack composed of a plurality of conductive lines, a plurality of semiconductive vertical structures, a plurality of memory elements, a plurality of wires, and a control circuit. The semiconductor vertical structures are orthogonal to these stacks. The memory element is located adjacent to the intersection of the stack and the side surface of the semiconductor vertical structure.

The stack of conductive strings is staggered across the insulated series. The stack includes a bottom layer of a conductive string, a plurality of intermediate layers of the conductive string, and a top layer of the conductive string.

The plurality of first wires are electrically coupled to the top layer of the conductive series. The plurality of second wires and the plurality of third wires are electrically coupled to the intermediate layer.

The control circuit is configured to cause the first wire to select one of the first particular stacks, the second wire to select the first specific stack of the stacks, and the third wire to select one of the intermediate layers A particular layer.

According to another aspect of the present technology, one of the decoders used by the wires is further included.

According to another aspect of the present technology, a method is provided. This method includes the following steps: The plurality of first wires are selected to select at least one first particular stack of the plurality of stacks. These stacks consist of several conductive strips. The conductive strings are staggered across a plurality of insulating strips. The stack includes one of the conductive traces, a plurality of intermediate layers of the conductive traces, and a top layer of the conductive traces. The first wire is electrically coupled to the top layer of the series.

A plurality of second wires are selected to select the first particular stack of the stacks. The second wire is electrically coupled to the intermediate layer.

The third wire is selected to select a particular layer of one of the intermediate layers. The second wire is electrically coupled to the intermediate layer.

The first wires, the second wires, and the third wires assist in the selection of at least one of the plurality of memory elements. The memory elements are located in a plurality of contiguous regions of the plurality of intersections stacked on the side surfaces of the plurality of semiconductive vertical structures. Such semiconductor vertical structures are orthogonal to these stacks.

In an embodiment, the first wires are string select lines. The second wires are electrically coupled to a plurality of switches. The switches are electrically coupled to the third wires and the conductive strings. These third wires are layer select lines. In an embodiment, the open relationships are transistors. Such transistors have a plurality of lateral gates. The side gates are located above a plurality of lateral conductive channels. The side conductive channels are electrically coupled to the conductive series and the Some third wires. In an embodiment, the open relationships are transistors. Such transistors have a number of gates surrounding a vertical conductive channel. The vertical conductive channels are electrically coupled to the conductive strings and the third wires.

In an embodiment, the third wires are electrically coupled to the intermediate layers by the second wires.

In an embodiment, the different intermediate layers are electrically coupled to different staircase contacts, and the different third wires are electrically coupled to different step contacts.

In an embodiment, the second wires comprise a particular decoding line. A particular decoder line selects multiple of these stacks. The selected stack is electrically coupled to a first set of the plurality of first conductors. The different first conductors of the first set select different stacks.

In an embodiment, one of the second conductive lines of the second conductive line selects only one of the stacks.

In an embodiment, the control loop is configured to select the first wires to select at least one first specific stack of the stacks, and the second wires select at least one first specific stack of the stacks and do not select such The other portions of the stack are arranged such that at least one particular layer of the intermediate layers are selected and the other portions of the intermediate layers are not selected.

In an embodiment, a plurality of fourth wires are further included. The fourth wires are electrically coupled to the semiconductor vertical structures. The control loop makes these fourth wires selected A subset of such semiconductor vertical structures is selected. This subset is arranged in a column that is orthogonal to these stacks.

In an embodiment, the third wires are parallel to the fourth wires.

In an embodiment, a first decoder, a second decoder, and a third decoder are further included. The first decoder is electrically coupled to the first wires. The second decoder is electrically coupled to the second wires. The first decoder and the second decoder are located on one of the first side and the second side of the stack, and the first wires are parallel to the second wires. The third decoder is electrically coupled to the third wires. The third decoder is located on one of the third sides of the stack. The third side is different from the first side and the second side.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

1, 2, 3‧‧‧Connector ladder

10, 11‧‧‧ page buffer

20, 21‧‧‧ character line decoder

101‧‧‧Integrated circuit board

120‧‧‧Vertical channel structure between stacks

130, 141, 142, 143‧‧‧ connecting elements

151, 152, 153, 161, 162, 163, 164, 165, 166, 171, 172, 173, 174, 175, 176, 181, 182, 183, 184, 185, 186 ‧ ‧ inter-layer connectors

160‧‧‧ reference conductor

167, 177, 187‧‧‧ conductive decoding lines

170, 190‧‧‧ access to the crystal

180‧‧‧交点点

201‧‧‧Sequence Select Line Decoder

203‧‧‧3D anti-gate memory array

204‧‧‧X decoder

205‧‧‧step connector

206‧‧‧Global word line

207‧‧‧Word line voltage generator

208‧‧‧block decoder

209‧‧‧Local word line driver

231, 232, 233, 234, 235, 236 ‧ ‧

251‧‧‧Vertical channel structure

252‧‧‧ memory components

261‧‧‧Vertical channel structure

262‧‧‧ dielectric

263, 264, 301, 302‧‧‧ conductive plugs

310‧‧‧Horizontal channel structure

312, 313‧‧‧ section line

1800‧‧‧ integrated circuit

1802‧‧‧Sensor amplifier and data input structure

1805‧‧‧ data input line

1810‧‧‧ Controller

1820‧‧‧ biasing device

1830‧‧ ‧ busbar

1840‧‧‧Serial decoder

1845‧‧‧Serial selection and grounding selection layer

1850‧‧‧layer decoder/block decoder/local word line driver

1860‧‧‧Three-dimensional memory array

1865‧‧‧ bit line

1870‧‧‧ bit line decoder

1875‧‧‧ data bus

1885‧‧‧ data output line

1890‧‧‧Output circuit

B1, B2, B3‧‧‧ block selection line

BL1, BL1 12, BL1 13, BL2, BL2 14, BL2 15, BL3, BL3 16, BL3 17, BL4, BL4 18, BL4 19‧‧‧ bit line

B#‧‧‧ Conductive decoding line

L1, L2, L3, L4‧‧‧ global character lines

GND 34‧‧‧ Grounding point

GSL, GSL 32; GSL 210‧‧‧ Grounding selection line

SSL, SSL1, SSL2, SSL3, SSL 30, SSL1 42, SSL2 44, SSL3 46, SSL1 42, SSL2 44, SSL3 46, SSL4 48, SSL5 50, SSL6 52, SSL# 240‧‧‧ Serial selection line

WL1 22, WL1 23, WL2 24, WL2 25, WL3 26, WL3 27, WL4 28, WL4 29, WL ₀ ~ WL _N-1 ‧‧‧ character line

FIG. 1 is a simplified circuit diagram of a two-dimensional memory array of an embodiment.

Figure 2 is a simplified circuit diagram of a three-dimensional memory array employing a vertical channel structure.

FIG. 3 is a schematic diagram showing a three-dimensional memory array using a vertical channel structure.

Figure 4 is a top view of a three-dimensional memory array using a vertical channel structure.

Figure 5 is a top view of a large-capacity three-dimensional memory array using a vertical channel structure.

Figure 6 is a top view of another large-capacity three-dimensional memory array using a vertical channel structure.

Figure 7 is a top view of another large-capacity three-dimensional memory array using a vertical channel structure.

Figure 8 is a block diagram showing a three-dimensional memory array using a vertical channel structure.

Figure 9 is a simplified circuit diagram of a via transistor similar to the three-dimensional memory device of Figure 8.

Figure 10 is a top view of a three-dimensional memory device employing a vertical channel structure and having a via transistor.

Figure 11 is a top plan view showing another three-dimensional memory device having a vertical channel structure and having a via transistor.

12 to 13 are a top view and a cross-sectional view showing another three-dimensional memory device having a vertical channel structure and having a via transistor.

14 to 15 are a top view and a cross-sectional view showing another three-dimensional memory device having a vertical channel structure and having a via transistor.

16 to 17 are a top view and a cross-sectional view showing another three-dimensional memory device having a vertical channel structure and having a via transistor.

Figure 18 is a simplified block diagram of the integrated circuit memory of one embodiment of the present invention.

The embodiments of the present invention are described in detail below with reference to the drawings. The present invention is not limited to the specific structures and methods disclosed in the embodiments. The invention can pass other Features, component methods, or other implementations are implemented. The preferred embodiments are merely illustrative of the invention and are not intended to limit the scope of the invention. The scope of protection of the present invention is still subject to the scope of the patent application. Those of ordinary skill in the art to which the present invention pertains will appreciate that the recited content includes equivalent variations thereof. Also, in the different embodiments, like elements are recited in the like.

Figure 1 shows a simplified circuit diagram of a two-dimensional memory array.

A plurality of NAND strings connected to the memory cells are accessed by bit lines BL1 12, BL2 14, BL3 16, and BL4 18. The reverse gate train has a first end. The first end is connected to the page buffer 10 via a bit line. The reverse gate train has a second end. The second end is located at the ground point GND 34. The first end of the page buffer 10 opposite the gate string has a plurality of access transistors controlled by a string select line SSL 30. The second end connected to the ground point GND 34 opposite the gate string has a plurality of access transistors controlled by a ground select line GSL 32. The different memory cells along the reverse gate train are accessed by word lines WL1 22, WL2 24, WL3 26, and WL4 28. The word lines WL1 22, WL2 24, WL3 26, and WL4 28 are controlled by a word line decoder 20.

Figure 2 shows a simplified circuit diagram of a three-dimensional memory array using a vertical channel structure.

A three-dimensional array is composed of several adjacent two-dimensional arrays. For ease of explanation, the simplified circuit diagram juxtaposes multiple two-dimensional arrays together.

The AND gate sequence is accessed by bit lines BL1 13, BL2 15, BL3 17, and BL4 19, respectively. The same bit line is shared by several two-dimensional arrays. The first end of the gate sequence is connected to the page buffer 11 through a bit line. The reverse gate sequence is listed at ground point GND 34 and has a second end. The first end of the page buffer 11 connected to the gate string has an access transistor controlled by the string select lines SSL1 42 , SSL 2 44 , and SSL 3 46 . The access transistors of a particular two-dimensional array are selected and controlled by corresponding serial select lines SSL1 42, SSL2 44, and SSL3 46. The second end connected to the ground point GND 34 opposite the gate string has a plurality of access transistors controlled by the ground select line GSL 32. The different memory cells along the reverse gate train are accessed by word lines WL1 23, WL2 25, WL3 27, WL4 29. The word lines WL1 23, WL2 25, WL3 27, WL4 29 are controlled by the word line decoder 21.

Figure 3 is a schematic diagram showing a three-dimensional memory array using a vertical channel structure.

The memory device includes an array of memory cells that are opposite to the gate train. The memory device can be a double-gate vertical channel memory array (DGVC). In FIG. 3, the three-dimensional memory array includes an integrated circuit substrate 101 and a plurality of stacks composed of a plurality of conductive strings. Each of the conductive series is separated by an insulating material, and includes one bottom surface of the conductive series (ground selection line GSL), a plurality of intermediate layers of the conductive series (word lines WL ₀ ~ WL _N-1 ), and conductive strings The top of the column (serial selection line SSL).

A plurality of vertical channel structures are orthogonal to the stack and include a stack An inter-stack vertical channel structure 120 and a linking element 130. The vertical channel structure 120 between the stacks is located between the stacks. The connecting element 130 is over the stack and connects the vertical channel structure 120 between the stacks. The material of the connecting element 130 of this example includes a semiconductor, such as a polysilicon, having a relatively high doping concentration such that the connecting element 130 has a higher electrical conductivity than the vertical channel structure 120 between the stacks. The vertical channel structure 120 between the stacks is used to provide a channel area for the memory cells within the stack. In FIG. 3, the material of the connecting member 130 may include an N+ doped semiconductor material. The material of the vertical channel structure 120 between the stacks may include a lightly doped semiconductive material. The memory element includes a patterned conductive layer (not shown) coupled to the vertical channel structure, for example, including a plurality of global bit lines connected to a sensing circuit.

The memory device includes a charge storage structure. The charge storage structure is located at a cross-point 180 of the conductive series of the intermediate layers of the stack (word lines WL ₀ ~ WL _N-1 ) and the vertical channel structure 120 between the stacks. In the illustrated example, the memory cell at intersection 150 is a vertical pattern. The conductive strings on either side of a stack of vertical channel structures 120 act as dual-gates and can be read, erased or programmed. In other embodiments, a surrounding gate can also be employed. The vertical channel structure traverses the horizontal string. A frustum that is horizontally listed in a vertical channel structure surrounds the memory layer. The reference conductor 160 is disposed between the bottom layer of the series (the ground selection line GSL) and the integrated circuit substrate 101.

The memory device includes a string select switch And reference select switch (reference select switch). The serial select switch is, for example, an access transistor 190 located at the top of the string. The reference select switch is, for example, an access transistor 170 located at the bottom of the series (ground select line GSL). In some examples, the dielectric layer of the charge storage structure acts as a gate dielectric layer for accessing the transistors 170, 190.

In an embodiment, to reduce the resistance of the reference conductor 160, the memory device can include a bottom gate adjacent to the reference conductor 160. The bottom gate can be activated to increase the reference during the reading process by applying a suitable pass voltage to the doped well or well in the substrate, or other patterned conductive structure. Conductivity of the conductor 160.

The memory device includes a connecting element. The connecting element includes a horizontal word line and a landing rea of the ground selection line GSL line structure to form a staircase contact of the decoding circuit. The series select lines of the top layer of the conductive series are independently coupled and controlled by string selection line decoding circuits.

The conductive series of the intermediate layer (word line WL ₀ ~ WL _N-1 ) and the conductive series of the bottom layer (ground selection line GSL) are connected together to reduce the area of the decoder and reduce the overall size of the memory device. The conductive strings of the top layer (serial select line SSL) are independently decoded to allow the bit lines to be decoded.

The memory unit may include a linking element (e.g., connecting elements 141 and 142) and an interlayer connector (e.g., interlayer connectors 151 and 152). In the intermediate layer (word lines WL ₀ ~ WL _N-1 ), the connection elements 141, 142 provide the landing area of the word line. The interlayer connectors 151, 152 are coupled to the landing regions of the connecting members 141, 142. The connecting element includes an opening such that the interlayer connector passes through the opening to couple to a landing zone at which the lower intermediate layer extends. The landing zone is located adjacent the bottom surface of the interlayer connector and the top surface of the connecting element.

As shown in Fig. 3, the connecting member 141 provides a landing area connected to the word line WL _N-1 . Connection element 142 provides a landing area that is coupled to word line WL ₀ .

As shown in Fig. 3, the interlayer connectors connecting the word lines in the intermediate layer are arranged in a stepped structure. For example, the interlayer connector 151 is connected to a landing area to connect the intermediate layer to the word line WL _N-1 . The interlayer connector 152 is connected to another landing area to connect the intermediate layer to the word line WL ₀ . The ladder structure can be formed in a word line decoder disposed at the edge of the memory cell and the array of the gate string and the edge of the peripheral line.

In the example of Fig. 3, the memory device includes a connecting member and an interlayer connector. The connecting element is, for example, a connecting element 143 that is connected to a ground selection line GSL in the bottom layer of the conductive string. The inter-layer connection is, for example, an interlayer connection 153 coupled to the landing area of the bottom layer. The interlayer connectors extend through the openings in the connecting elements of the intermediate layers (word lines WL ₀ ~ WL _N-1 ). The landing zone is located at the abutment of the bottom surface of the interlayer connector (e.g., interlayer connector 153) and the top surface of the connecting member (e.g., connecting member 143).

Several examples of three-dimensional inverse gate memory structures using vertical channels The "3D Independent Double Gate Flash Memory" of the co-pending U.S. Patent Application Serial No. 14/284,306, filed on May 21, 2014. US patent application. This case is incorporated by reference to this patent application. And U.S. Patent No. 8,013,383, "Nonvolatile Semiconductor Storage Device Including a Plurality of Memory Strings", published on September 6, 2011, in U.S. Patent No. 2012 US Patent Publication No. 2102/0299086, "Semiconductor Memory Devices", and U.S. Patent No. 8,363,476, issued Jan. 20, 2013, to U.S. Patent No. 8,363,476, "memory devices, methods of manufacture, and methods of operation thereof" Memory Device, Manufacturing Method and Operating Method of the Same) "US Patent Cases are both incorporated in this case. As described in these cited documents, the design of various word lines of vertical channel memory structures has been developed and these can be employed in embodiments of the present technology.

Figure 4 is a top view of a three-dimensional memory device employing a vertical channel structure.

A plurality of reverse gate series connected to the memory cell are accessed by bit lines BL1 13, BL2 15, BL3 17, and BL4 19. The anti-gate train has a first end and a second end. The first end is connected to a page buffer by a bit line. The second end is connected to a grounding point (not shown). The first end of the reverse gate series begins with an access transistor controlled by serial select lines SSL1 42, SSL2 44, and SSL3 46. Bit The stacking of a particular vertical plane is selected by the corresponding tandem select lines SSL1 42, SSL2 44, and SSL3 46. The serial select lines SSL1 42, SSL2 44, and SSL3 46 control the access transistors located in a particular vertical plane. The second end of the reverse gate train is connected to the ground point GND 34 and has an access transistor controlled by the ground select line GSL32. The different memory cells along the reverse gate train are accessed by word lines WL1 23, WL2 25, WL3 27, WL4 29. The word lines WL1 23, WL2 25, WL3 27, WL4 29 are controlled by the word line decoder 21.

The different intermediate layers of the word lines are selected by the interlayer connectors 161, 162, and 163. The interlayer connectors 161, 162, and 163 are electrically connected to landing areas of different intermediate layers. The memory cells in the array include a vertical channel structure 251 and a memory element 252.

Figure 5 is a schematic diagram showing a large-capacity three-dimensional memory device using a vertical channel structure.

The capacity of the three-dimensional memory device of FIG. 5 is greater than the capacity of the three-dimensional memory device of FIG. 4 by increasing the number of serial selection lines and by increasing the number of word line stacks. These word lines are placed on an increased number of vertical planes. The increased number of serial selection lines includes serial selection lines SSL1 42, SSL2 44, SSL3 46, SSL4 48, SSL5 50, and SSL6 52. The increased number of interlayer connections includes interlayer connectors 161, 162, 163, 164, 165, and 166. The number of intermediate layers of the word lines also corresponds to an increase in the number of interlayer connectors. The interlayer connection members 161, 162, 163, 164, 165, and 166 are electrically connected to the word line decoder 21 and different intermediate portions by wires (for example, a conductive decoding line 167). Between the landing areas of the layers. These increased number of stacks increase capacity, noise, and power consumption relative to a smaller number of stacked three-dimensional memory devices in FIG.

FIG. 6 is a schematic diagram showing another large-capacity three-dimensional memory device using a vertical channel structure.

The capacity of the three-dimensional memory device of Fig. 6 is increased relative to Fig. 4 by increasing the number of intermediate layers of the word line. The increased interlayer connectors include interlayer connectors 171, 172, 173, 174, 175, and 176 corresponding to the number of interlayer connectors.

The number of interlayer connectors and the number of intermediate layers of the word lines are equal in Figures 5 and 6. However, the number of tandem selection lines (the vertical faces of the stack of word lines) is reduced. Another case is that the arrangement of the landing areas changes from depth 1 and width N to depth N and width 1. In this context, depth refers to the direction of the length of the word line, and width refers to the direction of the bit line. The inter-connector 161, 162, 163, 164, 165, and 166 are electrically coupled to the word line decoder 21 by the conductive decoding line 177. Because the wires are crowded in a small space, the process complexity is much higher than that in Figure 5.

Fig. 7 is a schematic view showing another large-capacity=dimensional memory device using a vertical channel structure.

With respect to Fig. 4, the capacity of the three-dimensional memory device of Fig. 7 is increased by increasing the number of intermediate layers of the word line. The interlayer connectors are added as interlayer connectors 181, 182, 183, 184, 185, and 186. The number of intermediate layers of the word lines also increases corresponding to the number of interlayer connectors.

The number of interlayer connectors and the number of intermediate layers of the word line are in Figures 5, 6, and 7 are the same. However, the number of tandem selection lines (the number of stacks of word lines stacked in a vertical plane) is between Fig. 5 and Fig. 6. The arrangement of the landing areas is not depth 1 and width N, nor depth N and width 1. Instead, the arrangement of the landing areas is depth 2 and width N/2. In this context, depth refers to the direction of the length of the word line, and width refers to the direction of the bit line. The interlayer connectors 181, 182, 183, 184, 185, and 186 are electrically coupled between the word line decoder 21 and the landing regions of the different intermediate layers by wires (e.g., conductive decode lines 187). The wire is placed in a larger space than in Figure 6. This space is still smaller than Figure 5, and the process is more complicated.

Figure 8 is a block diagram showing a three-dimensional memory device employing a vertical channel structure.

The 3D NAND memory array 203 includes a plurality of inverted gate trains. The gate sequence is connected to the memory cell, and the memory cell is accessed by the bit line. The gate sequence has a first end and a second end. The first end is connected to the page buffer 11 through the bit line, and the second end is located at the ground point. The first end connected to the page buffer 11 opposite the gate string has a plurality of access transistors that are controlled by the series select lines. The serial selection line is controlled by the serial selection line decoder 201. The three-dimensional inverse gate array is a similar arrangement of multiple two-dimensional arrays. A particular two-dimensional array is selected by a corresponding string select line that controls the access transistor of the two-dimensional array. The different memory cells of the gate sequence are accessed by word lines, which are initiated by a word line voltage generator 207. Layer decoder and state machine circuitry (not shown) is located in word line voltage generator 207 to control the voltage of different global word lines 206. For example, the erase, stylize, and read programs can control the different global word lines 206 to have different voltages through the word line voltage generator 207 for erasing, programming, and reading. The word line voltage generator 207 is electrically coupled to the local word line of the three-dimensional anti-gate memory array 203 via a staircase contact 205 and a local word line driver 209. The local word line driver can act as a switch for the transistor to electrically connect or disconnect the global word line 206 to the local word line of the three-dimensional inverse gate memory array 203. The signal of the page buffer 11 to the bit line, the signal of the serial selection line decoder 201 to the serial selection line, and the combination of the signal of the word line line generator 207 via the local word line driver 209 to the local word line may be Fill in a memory cell in a three-dimensional array.

The local word line driver 209 controls a plurality of switches that are electrically coupled to the local word line 206 to the local word line of the three-dimensional inverse gate memory array 203 through the step connection 205. A block decoder 208 performs block decoding to turn a group switch of the local word line driver 209 on or off. The global word line driver 207 can provide a voltage to a plurality of word lines of an intermediate layer, and the local word line driver 209 turns off a portion of the word lines of the intermediate layer activated by the global word line 206.

The conductive global word line 206 from the word line voltage generator 207 is parallel to the conductive bit lines from the page buffer 11. In this embodiment, the SSL decoder 201 and the X decoder (X-decoder) 204 are located in the three-dimensional anti-gate Both sides of the body array 203 are recalled. The X decoder 204 can include a local word line driver 209 and a block decoder 208.

In the three-dimensional inverse gate memory array and the step connector 205, the broken lines indicate blocks that are electrically insulated from each other. Such electrical insulation allows partial local word lines to be initiated with different block select lines in a particular intermediate layer.

A block can be the smallest erase unit in the NAND flash. In the case of a two-dimensional inverse gate, each block has a serial select line SSL/ground select line GSL. In the three-dimensional inverse gate, the plurality of serial selection lines SSL and one of the ground selection lines GSL may be located in a single block. Flash memory has a limited life cycle; for example, a flash memory cell will collapse after 1000 stylization/erasing cycles. In order to increase the life cycle of the memory chip, the data read/write of each block must be balanced. In the damaged area, good blocks can still be used. The smallest unit of these techniques is a block. In the two-dimensional inverse gate, the block size is N _BL *N _WL . In the three-dimensional inverse gate, the block size is N _BL *N _WL *N _SSL . N _BL is the number of bit lines in a block. N _WL is the number of word lines in a block. N _SSL is the number of serial selection lines SSL of a block.

Figure 9 is a simplified circuit diagram of a pass transistor similar to the step connector of the three-dimensional memory device of Figure 8.

The word line voltage generator 207 controls different global word lines (eg, global word lines L1, L2, L3, and L4) having different voltages to implement the wipe. Programs such as division, stylization, and reading.

Different global character lines L1, L2, L3, and L4 turn on/off different layers of the word line, respectively. The global word line L1 is electrically coupled to the first step (staircase step 1). The global word line L2 is electrically coupled to the second step (staircase step 2). The global word line L3 is electrically coupled to the third step (staircase step 3). The global word line L4 is electrically coupled to the fourth step (staircase step 4). Different levels are electrically coupled to different intermediate layers of the word line. As mentioned above, each level can be any collection of staircase contacts controlled by a block select signal.

The block decoder 208 controls the transistor as a word line driver to switch whether the signal of the global word line reaches the corresponding step connector and the corresponding word line intermediate layer. The signals generated by block decoder 208 are carried by conductive block select lines B1, B2, and B3. The block select lines B1, B2, and B3 respectively activate and deactivate specific blocks of the word line driver to enable and disable local word lines of a particular intermediate layer. Each of the conductive block select lines B1, B2, and B3 controls a column of word line driver transistors that drive the gas crystals to connect to different stack of contacts. The different connector steps are electrically insulated from each other. The block select line B1 controls a column word line driver transistor connected to a contact staircase 1 . The block select line B2 controls a column word line driver transistor connected to a contact staircase 2. The block select line B3 controls a column word line driver transistor connected to a contact staircase 3. Connector steps 1, 2, and 3 are electrically connected to each other edge.

Figure 10 is a top view of a three-dimensional memory device having a pass transistor and a vertical channel structure. The via transistor initiates a particular word line associated with a string select line of one of the three dimensional memory devices.

The signal generated by word line voltage generator 207 is carried by conductive global word lines L1, L2, L3, L4, L5, and L6. The global word lines L1, L2, L3, L4, L5, and L6 enable and disable different layers of the word line. The global word line L1 is electrically coupled to the level 231. The global word line L2 is electrically coupled to the level 232. The global word line L3 is electrically coupled to the level 233. The global word line L4 is electrically coupled to the level 234. The global word line L5 is electrically coupled to the level 235. The global word line L6 is electrically coupled to the level 236.

Block decoder 208 controls the word line driver transistors. The word line driver transistor switches whether the signal of the global word line reaches the corresponding interlayer connector and the corresponding intermediate layer of the local word line. For example, the word line driver transistor at the intersection of the block select line B1 and the global word line L1 has a gate all around structure with a vertical channel that traverses the dielectric 262. Structure 261. The signal generated by block decoder 209 is carried by block select lines B1, B2, and B3. The block select lines B1, B2, and B3 turn on and off a particular word line driver transistor, respectively, and activate and deactivate local word lines for a particular block of each intermediate layer.

The memory cells within the array include a vertical channel structure 251 and a memory element 252. The vertical channel structure can include a semiconductor that can serve as a channel for the memory element Materials such as germanium (Si), germanium (Ge), germanium telluride (SiGe), gallium arsenide (GaAs), germanium carbide (SiC), and Graphene. The memory element of the memory device can include a charge storage structure, such as a multilayer dielectric charge trapping structure well known in flash memory technology. The multilayer dielectric charge trapping structure is, for example, ONO (oxide-nitride-oxide), ONONO (oxide-nitride-oxide-nitride-oxide), SONOS (silicon-oxide-nitride-oxide-silicon), BE-SONOS (bandgap engineered) Silicon-oxide-nitride-oxide-silicon, TANAS (tantalum nitride, aluminum oxide, silicon nitride, silicon oxide, silicon), and MA BE-SONOS (metal-high-k bandgap-engineered silicon-oxide-nitride-oxide- Silicon).

The reverse gate sequence connected to the memory cell is accessed by bit lines BL1, BL2, BL3, and BL4. The bit line selects memory cells at different locations along the local word line. The same line is located along the local word lines of the different intermediate layers to select the memory cells. The reverse gate train has a first end. The first end is connected to the page buffer 11 through a bit line. The reverse gate train has a second end. The second end is at the grounding point. The first end of the page buffer 11 connected to the gate string has a plurality of access transistors controlled by the string selection lines SSL1, SSL2, and SSL3. The second end connected to the ground point opposite the gate train has a plurality of access transistors controlled by the ground select line GSL.

The first series of reverse gate series is turned on and off by the ground point SSL1. The transistor located in the first string of the reverse word line of the gate string is grounded by the ground point B1 control. The second series of reverse gate series is turned on and off by the serial selection line SSL2. The transistors located in the first series of inverted word lines of the gate string are controlled by the block select line B2. The third series of reverse gate series is turned on and off by the serial selection line SSL3. The transistors located in the local string of the third string of inverted gate trains are controlled by block select line B3.

In this way, even if the global word line voltage generated by the word line voltage generator 207 is coupled to a plurality of local word lines located in the same intermediate layer, the block decoder 208 can only activate the local character of the selected part. Line driver transistor. Thereby, only the local word line of the selected one of the selected portions can be activated in the same intermediate layer. For example, word line voltage generator 207 can use conductive global word line L1 to select a plurality of local word lines of the top intermediate layer through level 231. From these local word lines, the block select line B1 only activates the transistor associated with the tandem select line SSL1, the block select line B2 only activates the transistor associated with the tandem select line SSL2, and the block select line B3 only A transistor associated with the serial select line SSL3 is activated.

The layer select line is parallel to the word line. The serial selection line SSL determines the vertical pitch. The word line and layer selection line determine the horizontal pitch. The number of block select lines may be equal to or less than the number of string select lines SSL.

Figure 11 is a top view of a three-dimensional memory structure having a vertical channel structure and having a via transistor. The via transistor initiates a particular word line associated with a plurality of serial select lines.

The arrangement of the three-dimensional memory device of Fig. 10 and Fig. 11 is similar. Of course However, in Fig. 11, the signal generated by the block decoder 208 is carried by the conductive decoding line B#. The conductive decode line B# turns on and off a particular word line transistor corresponding to the plurality of string select lines. In Fig. 11, all of the transistors of the reverse gate train are turned on and off by the word line driver transistor controlled by the conductive decode line B#. The reverse gate sequence is turned on and off by the serial selection lines SSL1, SSL2, and SSL3. In contrast, in FIG. 10, the signal generated by the block decoder 208 is carried by the block selection lines B1, B2, and B3, and the characters corresponding to a specific block of a serial selection line are respectively turned on and off. Line driver transistor. In other embodiments, the block select line can initiate and turn off a particular region fast word line driver transistor corresponding to other numbers of serial select lines.

12 and 13 are a top view and a side view of a three-dimensional memory device having a vertical channel structure and having a via transistor. The via transistor initiates a word line for a particular portion of a serial select line.

Some of the elements of the different three-dimensional memory devices of Figures 10 and 11 are described in more detail in Figures 12 and 13. 12 and 13 are detailed diagrams showing the serial selection line and the block selection line of the three-dimensional memory device of FIG. 10, for example, the serial selection line SSL1 and the block selection line B1, or the serial selection line SSL2 and the area. The block selection line B2, or the tandem selection line SSL3 and the block selection line B3. 12 and 13 also illustrate in detail the serial selection line and the block selection line of the three-dimensional memory device of FIG. 11, for example, the serial selection line SSL2 and the conductive decoding line B#.

The conductive global word lines L1, L2, L3, L4, L5, and L6 activate and deactivate the levels 231, 232, 233, 234, 235, and 236, respectively. Conductive The global word lines L1, L2, L3, L4, L5, and L6 carry the signals generated by the word line voltage generator to the levels 231, 232, 233, 234, 235, and 236, respectively.

The global word line L1 is electrically coupled to the level 231 of the interlayer connector through the word line driver transistor. The global word line L2 is electrically coupled to the level 232 of the interlayer connector through the word line driver transistor. The global word line L3 is electrically coupled to the level 233 of the interlayer connector through the word line driver transistor. The global word line L4 is electrically coupled to the level 234 of the interlayer connector through the word line driver transistor. The global word line L5 is electrically coupled to the level 235 of the interlayer connector through the word line driver transistor. The global word line L6 is electrically coupled to the level 236 of the interlayer connector through the word line driver transistor.

A block decode line (e.g., conductive decode line B#) carries signals from the block decoder to control the word line driver transistors. The word line driver transistor switches whether the signal of the global word line reaches the corresponding interlayer connector and the corresponding intermediate layer of the local word line. For example, the wire word line driver transistor at the intersection of the conductive decoding line B# and the global word line L1 has a gate all around structure. The wraparound gate structure has a vertical channel structure 261 that traverses the dielectric 262 surrounding the vertical channel structure 261. The vertical channel structure 261 of the word line driver transistor is electrically coupled to the global word line L1 and the area word line plane 231 by conductive plugs 263 and 264. The intersection of the conductive decoding line B# and the other global word lines L2, L3, L4, L5, and L6 also has a corresponding word line driver transistor having a surrounding gate structure.

Conductive decoding line B# carries the signal from the block decoder to start And the word line driver transistor and the local word line are turned off. The conductive decoding line B# activates and turns off the word line driver transistor electrically coupled to the global word line L1 and the level 231, and the word line driver transistor electrically coupled to the global word line L2 and the level 232. A word line driver transistor coupled to the global word line L3 and the level 233, a word line driver transistor electrically coupled to the global word line L4 and the level 234, electrically coupled to the global word line The word line driver transistors of L5 and 235 are electrically coupled to the word line driver transistors of the global word line L6 and the level 236.

The memory cells of the array include a vertical channel structure 251 and a memory element 252 accessed by bit line BL1. The remaining bit lines BL2, BL3, and BL4 also access similar memory cells including vertical channel structures and memory elements. The gate and column connected to the memory cell are accessed by the bit lines BL1, BL2, BL3, and BL4. The bit line selects memory cells along different locations of levels 231, 232, 233, 234, 235, and 236.

The same bit line selects the memory cells along different intermediate layers. The reverse gate train has a first end. The first end is connected to the page buffer by bit lines BL1, BL2, BL3, and BL4. The reverse gate train has a second end. The second end is at the grounding point. The first end of the gate string connected to the page buffer has an access transistor controlled by the tandem select line SSL#240. The second end of the reverse gate train has an access transistor controlled by a ground select line plane GSL 210 to electrically connect the reverse gate train to the ground point.

The gate sequence is activated and deactivated by the serial selection line SSL#. Reciprocal The transistor of the word line in the gate string is activated and deactivated by the conductive decoding line B#.

In this way, even if the global word line voltage generated by the word line voltage generator 207 is connected to the local word line of the same intermediate layer, the block decoder 208 can activate only one part of the local word line driver transistor. And, by this, only partial word lines of the same intermediate layer can be activated. For example, the word line voltage generator can conduct the global word line L1 by the level 231 to select the top middle layer.

14 and 15 are a top view and a cross-sectional view of a three-dimensional memory device having a vertical channel structure and having a thin film pass transistor. The via transistor initiates a word line with respect to the tandem select line.

Figure 14 has a section line 312 which is used to indicate the position of the section of Figure 15.

The three-dimensional memory device of Fig. 14 is similar to the three-dimensional memory device of Fig. 11, and the memory cells of the word line opposite to the gate string are activated and turned off by the conductive decoding line B#. The reverse gate sequence is enabled or disabled by the serial select lines SSL1, SSL2, and SSL3. However, in FIG. 11, the transistor controlled by the conductive decoding line B# has a gate all around structure, and the electromorphic system controlled by the conductive decoding line B# in FIG. 14 is a thin film transistor. .

The global word lines L1, L2, L3, L4, L5, and L6 carry the signals generated by the word line voltage generators to the levels 231, 232, 233, 234, 235, and 236. The global word lines L1, L2, L3, L4, L5, and L6 are electrically coupled to the conductive plugs (for example, the conductive plugs 301). Conductive plug (for example, conductive plug 301) Electrically coupled to one of the first ends of the horizontal channel structure 310. In the upper view of Fig. 14, a row of conductive plugs containing conductive plugs 301 are shown in solid lines, which is located above horizontal channel structure 310. The material of the horizontal channel structure 310 can be the same as the material of the vertical channel structure 251. Alternatively, the horizontal channel structure 310 and the vertical channel structure 251 can be selected from different materials. The second end of the horizontal channel structure 310 is electrically coupled to the conductive plug (for example, the conductive plug 302). In the upper view of Fig. 14, a row of conductive plugs containing conductive plugs 302 are shown in dashed solid lines, which are located below horizontal channel structure 310.

Figure 15 illustrates the conductive plug 301 above the horizontal channel structure 310 and the conductive plug 302 under the horizontal channel structure.

In a conductive plug including one of the conductive plugs 302, the conductive plug corresponding to the global word line L1 is electrically coupled to the interlayer connector of the layer 231, and the conductive plug is electrically coupled to the global word line L2. The conductive plug corresponding to the global word line L3 is electrically coupled to the interlayer connection of the layer 233, and the conductive plug corresponding to the global word line L4 is electrically coupled to the layer 234. The interlayer connection member, the conductive plug corresponding to the global word line L5 is electrically coupled to the interlayer connection of the layer 235, and the conductive plug corresponding to the global word line L6 is electrically coupled to the interlayer connection of the layer 236. .

Figure 15 does not show the interlayer connections of the hierarchy 231. Similarly, in the cross-section of the global word line L1, the level 231 is above the level 232, and the second end of the horizontal channel structure 310 is connected to the level 231 by a shorter conductive plug 302. Similarly, in the profile of the global word line L3, the level 233 is located at level 232. Next, the second end of the horizontal channel structure 310 is connected to the level 233 by a longer conductive plug 302. Similarly, in the cross-section of global word line L4, level 234 is below level 232, and the second end of horizontal channel structure 310 is connected to level 234 by a longer conductive plug 302. Similarly, in the cross-section of the global word line L5, the level 235 is below the level 232, and the second end of the horizontal channel structure 310 is connected to the level 235 by a longer conductive plug 302. Similarly, in the cross-section of global word line L6, level 236 is below level 232, and the second end of horizontal channel structure 310 is connected to level 236 by a longer conductive plug 302.

16 and 17 illustrate a top view and a cross-sectional view of another three-dimensional memory device having a vertical channel structure and having a thin film pass transistor. The via transistor initiates a word line with respect to the tandem select line. Figure 16 has a section line 313 which is used to indicate the position of the section of Figure 17.

Figures 16 to 17 are similar to the three-dimensional memory devices of Figures 14-15. However, the horizontal channel structure 310 of FIGS. 14-15 does not extend over the conductive plug 302; in FIGS. 16-17, the horizontal channel structure 310 extends over the conductive plug 302.

In other embodiments, the word line driver transistor controlled by the block decoder has a long channel that is greater than 1.5 um in length.

Figure 18 is a simplified block diagram of an integrated circuit memory in accordance with an embodiment of the present invention.

The integrated circuit 1800 includes a three-dimensional memory array 1860 that is located on an integrated circuit board.

The serial decoder 1840 is coupled to the serial selection and ground selection layer 1845 in the memory array 1860. Bit line decoder 1870 is coupled to bit line 1865 within memory array 1860 for reading and memory cells of programmed memory array 1860. In the layer decoder/block decoder/local word line driver 1850, the block decoder is electrically coupled to a plurality of blocks of the word line driver. The word line driver is, for example, a transistor that can electrically or electrically separate the global word line and the local word line in the memory array 1860. And in the layer decoder/block decoder/local word line driver 1850, the layer decoder controls the stylized, erased, and read voltages provided to the global word lines. The address is provided by bus line 1830 to bit line decoder 1870, serial decoder 1840, and layer decoder/block decoder/local word line driver 1850. A sense amplifiers and data-in structure 1802 is coupled to the bit line decoder 1870 using a data bus 1875. Sensing data from the sense amplifier is provided to an output circuit 1890 by a data output line 1885. The output circuit 1890 outputs the sensing data to a destination outside the integrated circuit 1800. The input data is input from an input/output port of the integrated circuit 1800 or an internal or external data source of the integrated circuit 1800 through a data-in line 1805. The data source is, for example, a general-purpose processor, a special application circuit, and a module supported by a three-dimensional memory array 1860 having a system-on-a-chip function.

In the example of Figure 18, controller 1810 controls the read or program voltage provided by bias arrangement device 1820. The controller 1810 can include a multi-level cell (MLC) stylized and read mode. Controller 1810 Special-purpose logic circuitry can be employed. In another embodiment, the controller includes a general-purpose processor. In other embodiments, the controller can be a combination of a general purpose processor and special application logic.

The integrated circuit 1800 can support a word line driver switch, such as a transistor. These transistors turn on and off the word lines by a block decoder. Memory array 1860 can include a first wire. A first wire is coupled to the top layer of the conductive string to select the first particular stack in accordance with the serial select line decoder. Memory array 1860 can include a second wire. The second wire is electrically coupled to the plurality of intermediate layers to select the first specific stack according to the block decoder. Memory array 1860 can include a third wire. The third wire is electrically connected to the intermediate layer to select a specific layer according to the layer decoder.

In some embodiments, the tandem selection line is twisted such that multiple sets of separate serial select lines can access the array. In some embodiments, the bit lines are warped such that multiple sets of bit lines can access the array.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

11‧‧‧Page Buffer

207‧‧‧Word line voltage generator

208‧‧‧block decoder

231, 232, 233, 234, 235, 236 ‧ ‧

251‧‧‧Vertical channel structure

252‧‧‧ memory components

261‧‧‧Vertical channel structure

262‧‧‧ dielectric

B1, B2, B3‧‧‧ block selection line

BL1, BL2, BL3, BL4‧‧‧ bit line

L1, L2, L3, L4, L5, L6‧‧‧ global character lines

SSL1, SSL2, SSL3‧‧‧ serial selection line

Claims (17)

A memory device includes: a plurality of stacks of conductive strips staggered across a plurality of insulating strips, the stacks comprising the conductive traces a bottom layer of the column, a plurality of intermediate layers of the conductive series, and a top layer of the conductive series; a plurality of semiconductive vertical structures, Orthogonal to the stacks; a plurality of memory elements located at a plurality of contiguous regions of the plurality of intersections of the stacked side surfaces of the semiconductor vertical structures; a plurality of first wires for controlling the location a plurality of transistor switches of the top layer of the conductive series; a plurality of second wires for controlling a plurality of local word line driver switches; a plurality of third wires, Included in the plurality of global word lines, the global word lines are electrically coupled to the intermediate layers by the local word line driver switches; A fourth plurality of conductors, including a plurality of bit line, bit line electrically coupled to the plurality of vertical semiconductor structure; wherein the plurality of third conductive line parallel to the plurality of fourth leads. The memory device of claim 1, further comprising: a control circuitry, wherein the first wires select at least one first particular stack of the stacks, The second wires select the at least one first specific stack of the stacks, and the third wires select one of the intermediate layers. The memory device of claim 1, wherein the local word line driver open relationship is a plurality of transistors having a plurality of lateral gates, the side gates The plurality of side conductive channels are electrically coupled to the conductive series and the third conductive lines. The memory device of claim 1, wherein the local word line driver open relationship is a plurality of transistors having a plurality of gates surrounding a vertical conductive channel (gate The vertical conductive channels are electrically coupled to the conductive strings and the third wires. The memory device of claim 1, wherein the plurality of intermediate layers are electrically coupled to different plurality of staircase contacts, and the third conductors are electrically coupled to Different of these ladder contacts. The memory device of claim 1, wherein the second guide The line includes a specific decoding line, the specific decoding line selects a plurality of the plurality of stacks, and the selected ones are electrically coupled to a first set of the plurality of first wires. The first wires different in the first set select different ones of the stacks. The memory device of claim 1, wherein the first conductive decoding line of one of the second wires selects only one of the stacks. The memory device of claim 1, further comprising: a control loop, wherein the first wires select at least one first specific stack of the stacks, and the second wires select the stacks The at least one first specific stack does not select other portions of the stack, and the third wires select at least one particular layer of the intermediate layers and do not select other portions of the intermediate layers. The memory device of claim 1, wherein a control loop causes the fourth wires to select a subset of the semiconductor vertical structures, the subsets being arranged in a column, the columns being orthogonal to the stacks. The memory device of claim 1, further comprising: a first decoder electrically coupled to the first wires; and a second decoder electrically coupled to the second wires The first decoder and the second decoder are located on one of the first side and the second side of the stack Side, and the first wires are parallel to the second wires. A method of operating a memory device includes: selecting a plurality of first conductors to select at least one first particular stack of a plurality of stacks, the stacks being composed of a plurality of conductive strips, The conductive series is interleaved with a plurality of insulating strips, wherein the stack includes one of the conductive traces, a plurality of intermediate layers of the conductive traces, and a top layer of the conductive traces. The first wires control a plurality of transistor switches located at the top layer; the plurality of second wires control a plurality of local word line driver switches to select the stacks At least one first specific stack; causing the third wires to select at least one particular layer of the intermediate layers by the local word line driver switches, the third wires comprising a plurality of global word lines (global word line); and causing the plurality of fourth wires to select a subset of the plurality of semiconductor vertical structures, the subsets being arranged in a column, the columns being orthogonal to the stacks; The first wires, the second wires, and the third wires assist in the selection of at least one of the plurality of memory elements, the memory elements being located in the stack and a plurality of semiconductive vertical structures a plurality of contiguous regions of the plurality of intersections of the side surface, the semiconductor vertical structures being orthogonal to the stacks, the third wires being parallel to the fourth wires. The method of operating the memory device of claim 11, wherein the local word line driver is in a plurality of transistors, the transistors having a plurality of lateral gates, the side gates being located The plurality of side conductive channels are electrically coupled to the conductive series and the third conductive lines. The method of operating a memory device according to claim 11, wherein the local word line driver open relationship is a plurality of transistors having a plurality of gates surrounding a vertical conductive channel The vertical conductive channels are electrically coupled to the conductive strings and the third wires. The operating method of the memory device of claim 11, wherein the intermediate layers are electrically coupled to different plurality of staircase contacts, and the third conductors are electrically coupled differently. Connect to different step contacts. The operating method of the memory device of claim 11, wherein the second wires comprise a specific decoding line, the specific decoding line selecting a plurality of the stacked, the stacked ones being selected Electrically coupled to a first set of the plurality of first wires, the first set of different first leads The lines select different stacks. The method of operating a memory device according to claim 11, wherein the first conductive decoding line of the one of the second wires selects only one of the stacks. The method of operating the memory device of claim 11, further comprising: selecting the first wires to select at least one first specific stack of the stacks, and causing the second wires to select the at least one of the stacks The first particular stack and the other portions of the stacks, and the third wires select at least one particular layer of the intermediate layers and do not select other portions of the intermediate layers.