TWI547075B - Method for stress suppression during start-up time - Google Patents

Description

Circuit and method for suppressing excessive current during voltage converter startup phase

The present invention mainly relates to a power conversion system, and more particularly to a voltage converter for use in a power supply field, which controls a primary current of a converter during a startup phase, and provides a control circuit and a control method.

In a conventional power conversion system, a switching power supply method that performs constant voltage or constant current control is usually employed. Controlling the opening or opening of the switching element on the primary winding of the transformer in the power conversion system, periodically generating a current flowing through the switching element on the primary winding of the transformer, and transferring the energy of the primary side to the secondary side, The alternating current generated in the windings is rectified and filtered by the injected diodes and capacitors, and then converted into direct current to supply the load.

At the instant of the start-up converter, since the output voltage supplied to the load at the output cannot meet the specification immediately, the conventional feedback mechanism will adjust the duty ratio of the switching switch on the primary winding to the maximum, so as to be on the primary winding. More energy is output, but at the same time the primary winding generates a large amount of inrush current, which exceeds the capability of each device and may burn devices such as switches. In the prior art which avoids a large amount of inrush current, most of them add a soft start circuit device to the power supply system to lengthen the start-up time and allow the voltage to rise relatively smoothly. Although a soft start circuit can alleviate the problem of inrush current to a certain extent, it cannot fundamentally eliminate the problem of excessive input current and voltage. In response to these problems, U.S. Patent Application No. US20120274299 proposes to add a regulating circuit to adjust the PWM signal. The disadvantage is that an additional regulating circuit is added, resulting in an increase in cost and a complicated overall circuit, and it is triggered in each cycle under heavy load conditions. The protection measures are such that this scheme is not suitable under heavy load conditions and the system generates subharmonics.

A circuit for suppressing excessive current in a voltage converter provided by the present invention has a main switch for controlling the primary winding to be turned on or off, comprising: an acquisition unit for shielding a primary current starting spike At the instant when the active state of the leading edge masking signal ends, a first voltage value applied to a sensing resistor in series with the primary winding is detected; a comparator inputs the first voltage value at the non-inverting input of the comparator and is compared The inverting input of the device inputs a reference voltage; the comparison result of the comparator output is transmitted to an oscillator. When the first voltage value exceeds the reference voltage, the comparison result triggers the frequency of the clock signal emitted by the oscillator to decrease to avoid the flow. The primary current through the primary winding exceeds the preset value.

In the above circuit, when the first voltage value does not exceed the reference voltage, the oscillator is configured to output a clock signal at the first frequency in the first operating mode to determine a switching period of the main switch; and when the first voltage value exceeds the reference voltage And setting the oscillator to output a clock signal at the second frequency in the second working mode to determine a switching period of the main switch, the second frequency being lower than the first frequency.

In the above circuit, the second frequency does not exceed one-half of the first frequency. In the above circuit, the acquisition unit detects the first voltage value applied to the sensing resistor at the instant when the leading edge shielding signal is turned over from the logic high level state to the logic low level state.

In the above circuit, the acquisition unit includes a first voltage follower, and the information of the first voltage value is sent to a sample-and-hold latch of the acquisition unit for storage at the end of the effective state of the leading edge masking signal in each cycle, and then stored. The voltage held by the sample-and-hold latch is output by a second voltage follower of the acquisition unit.

In the above circuit, the positive input terminal of the first voltage follower is coupled to a common node connected to both the sense resistor and the main switch, and the voltage sense signal representing the magnitude of the primary current flowing through the sense resistor is delivered to the first voltage at the common node. The positive input of the follower.

In the above circuit, a first switch controlled by the leading edge shielding signal is connected between the output end of the first voltage follower and the sample-and-hold latch, and the first switch is turned off immediately after the active state of the leading edge shielding signal ends. That makes each of the main switches After the timing of the switching period from the high level to the low level and ending the active state, the voltage value data held by the sample and hold latch is maintained at the instant when the leading edge of the active state of the masking signal is applied to the sensing resistor. State first voltage level.

In another embodiment of the present invention, a method of suppressing excessive current in a voltage converter is provided, wherein a primary switch is used to control the primary winding to be turned on or off, including: before shielding one of the primary current starting spikes At the instant when the effective state of the edge masking signal ends, a first voltage value applied to a sense resistor connected in series with the primary winding is detected by an acquisition unit; a first voltage value is input to the comparator at the non-inverting input of the comparator The inverting input terminal inputs a reference voltage; the comparison result of the comparator output is transmitted to an oscillator. When the first voltage value exceeds the reference voltage, the comparison result triggers the frequency of the clock signal emitted by the oscillator to decrease to avoid the flow. The primary current through the primary winding exceeds the preset value.

In the above method, when the first voltage value does not exceed the reference voltage, the oscillator is set to output a clock signal at the first frequency in the first operating mode to determine a switch for controlling a main switch of the primary winding to be turned on or off. a period; and when the first voltage value exceeds the reference voltage, setting the oscillator to output a clock signal at the second frequency in the second operating mode to determine a switching period of the main switch, the second frequency being lower than the first frequency.

In the above method, the second frequency does not exceed one-half of the first frequency. In the above method, when the leading edge masking signal is turned from the logic high level state to the logic low level state, the collecting unit detects the first voltage value that is applied to the sensing resistor at the instant when the effective state of the leading edge masking signal ends.

In the above method, at the instant when the leading edge of the leading edge shielding signal is in an active state, a first voltage follower of the collecting unit supplies the first voltage value to a sample holding latch of the collecting unit for storage, and then one of the collecting units The second voltage follower converts the voltage information held by the sample-and-hold latch into a voltage value equivalent to the first voltage value and outputs it.

In the above method, the positive input terminal of the first voltage follower is coupled to a common node connected to both the sense resistor and the main switch, and characterizes the primary flowing through the sense resistor A current sensed voltage sense signal is delivered to the positive input of the first voltage follower at a common node.

In the above method, a first switch controlled by the leading edge shielding signal is connected between the output end of the first voltage follower and the sample holding latch, and the first switch is turned off immediately after the effective state of the leading edge shielding signal ends. After the time when the leading edge masking signal is turned from the high level to the low level and the active state is ended in each switching period of the main switch, the voltage data held by the sample holding latch is maintained at the end of the effective state of the leading edge masking signal. The transient first voltage level applied to the sense resistor.

101‧‧‧ nodes

102‧‧‧Main control module

130‧‧‧Transformers

130A‧‧‧Primary winding

130B‧‧‧Secondary winding

201‧‧‧Detection module

202‧‧‧Sampling and holding latches

280‧‧‧ acquisition unit

301‧‧‧Oscillator

302‧‧‧Control signal generator

3021‧‧‧ comparator

3022‧‧‧RS trigger

303‧‧‧Power output stage

401‧‧‧First voltage follower

402‧‧‧Second voltage follower

QM‧‧‧ main switch

D _O ‧‧‧ Diode

C _O , C ₁ , C ₂ ‧‧‧ capacitor

R _L ‧‧‧load

R _S ‧‧‧resistance resistor

R10‧‧‧resistance

SW1‧‧‧ first switch

Figure 1 shows a simplified circuit diagram of a flyback converter.

Figure 2 is a schematic diagram of the acquisition of the primary winding current value at the end of the leading edge masking signal.

Fig. 3 is a leading edge occlusion signal waveform for shielding the leading edge of the sensing signal from the moment when the main switch is turned on.

Figure 4 is a diagram showing an example of a control signal generator receiving a clock signal to drive a power stage.

Figure 5 is an example of a control signal generated by a control signal generator.

Figure 6 is an acquisition unit that acquires a voltage sensing signal applied to the sense resistor.

Figure 7 is a comparison of the voltage across the sense resistor at the end of the leading edge masking signal with the reference voltage to determine the output frequency.

Figures 8-9 are waveforms showing the primary current when the current suppression method of the present invention is used instead of the current method.

Referring to FIG. 1, a circuit structure of a flyback Flyback voltage converter according to the present invention, the main switching electronic component QM for controlling the primary side may be, for example, a power MOSFET having an input terminal such as a 汲 terminal and having, for example, a source terminal. An output terminal, and a control terminal having, for example, a gate. The control end of the main switch QM receives the control signal sent by the main control module 102 and performs a corresponding open or open response action, so that the main switch QM is turned on or off to the primary winding of the transformer 130 of the flyback converter. The current flowing over 130A is controlled to be turned on or off to transfer energy from the primary side to the secondary side. The primary winding 130A is for receiving an input DC input voltage V _IN , and the DC input voltage V _IN can be rectified by a rectifying element such as a bridge rectifier such as a commercial AC voltage V _AC . Transformer 130 also has a secondary winding 130B for delivering an output voltage _VOUT , the polarity of secondary winding 130B being opposite to the polarity of primary winding 130A. A rectifying and filtering circuit of a diode D _O and a capacitor C _O is connected to the secondary winding 130B. The main switch QM is in the off phase of the switching cycle, and the transformer current is transmitted from the primary to the secondary, and flows through the secondary winding 130B. The stage current I _S charges the capacitor C _O through the forward-conducting diode D _O for generating the output voltage V _{OUT of the} flyback converter. The DC output voltage V _{OUT is} applied across the load R _L to form an output current I _OUT flowing through the load R _L . In the feedback network of the converter, a sensing resistor R _S is connected between the source terminal and the ground terminal of the main switch QM, and the source terminal and the ungrounded end of the sensing resistor R _S are connected to the node 101, and the sensing resistor R _{S is} used. The primary current I _P flowing through the primary winding 130A is detected and an internal loop feedback voltage equal to the current I _P multiplied by the resistance of the sensing resistor R _S is provided at the node 101, that is, the sensing signal V _CS embodied as a voltage value, the primary current I _P can be used to characterize the secondary current I _S flowing through the secondary winding 130B. The sensing port CS of the main control module 102 detects the primary current I _P signal of the primary winding 130A by the sensing signal V _CS on the sensing resistor R _S and determines whether the main control switch QM is turned on or off as a judgment of whether the control signal needs to be adjusted. Basis. Those skilled in the art are familiar with the topology and working mode of the flyback converter, and the circuit parts and specific operation modes that can be omitted are not described.

Referring to Fig. 2, the approximate waveform of the primary current I _P flowing through the primary winding 130A and the secondary current I _S flowing through the secondary winding 130B is shown. Although the present invention is exemplified only by the current in the continuous current CCM mode, the same applies to the current interrupted DCM mode. The main switch QM is switched by a control signal such as a pulse width modulation signal PWM, and the primary current I _P starts to ramp up at a time t ₁₁ at the beginning of a switching cycle, and the primary current peaks and closes at time t ₁₃ The main switch QM is the conduction period T _{ON of the} main switch QM from the time t _{11 to the} time t ₁₃ . From time t _{13 to} time t ₁₄ is the off period T _OFF of the main switch QM, and the secondary current I _{S is} attenuated from time t ₁₃ to time t ₁₄ until a complete period T _S ends at time t ₁₄ .

Referring to Fig. 3, in order to avoid unnecessary erroneous operations in the step of detecting the primary current I _P , a leading edge blanking signal LEB (Leading edge blanking) which is well known to those skilled in the art is usually employed. In the loop of the primary current control, it is often encountered that the primary current I _P has a pulse start peak phenomenon at the turn-on moment of the main switch QM, and the initial spike of the initial spike is reflected back to the main control module 102 at the sensing port CS. If the current value sampled by the sensing resistor R _S is used as the sensing signal V _CS for switching control, an erroneous triggering action may occur due to the unexpected initial spike Spike 355 of the sensing signal V _CS in FIG. The overcurrent protection mechanism is activated to achieve the purpose of protecting each electronic device, so that the main control module 102 that generates the control signal no longer outputs the modulation signal, thereby actively inducing the wrong power off main switch without real overcurrent abnormality. The action of QM. The variable or fixed leading edge occlusion signal LEB generated by the conventional leading edge shielding circuit is used to eliminate such a false triggering hazard. This signal can be coupled to the control terminal of the main switch QM to ensure that the leading edge occlusion signal LEB has During the high level period, the main switch QM is not turned off, so that after the leading edge masking signal LEB ends, the current signal is sampled on the sensing resistor RS to sample the more realistic and accurate sensing signal V _CS initial value, thereby realizing the use of leading edge shielding. The signal LEB shields the pulse start peak of the primary current I _{P when} the main switch QM is turned on. It is easy to understand that the leading edge masking signal is used to filter out the short-term interference pulse that occurs when the primary current I _P starts to flow and the initial induced spike voltage is generated at the instant of the main switch QM, and thus will be at the end of the sensing resistor R _{S .} The power tube turn-on induced current spike voltage generated at node 101 is filtered out. As for how to design the leading edge shielding circuit is not the focus of the present invention, the existing related solutions are regarded as the prior art by the present invention and will not be repeatedly described. The conventional power supply design instruction manual generally introduces it in detail, and can also Reference is made to the already published U.S. Patent Application No. 12/492,748, the disclosure of which is incorporated herein by reference.

Referring to Figures 2~3, after the main switch QM is turned on, we need to turn the leading edge masking signal LEB from a high level to a low level, that is, the signal is detected at the end of t ₁₂ and flows through the sensing resistor. An instantaneous current value of the primary current I _P of R _S , the instantaneous current value of the sampling of the primary current I _P is recorded as the leading edge shielding current value I _LEB , which represents the moment applied to the sensing resistor R _S at the moment. The voltage value and sampling scheme are described in detail below.

Referring to FIG. 4 and FIG. 5, in the voltage converter, an oscillator 301 outputs the clock signal CLK generated by it to a control signal generator 302, which has the same function as the main control module 102. The control signal generator 302 generates a corresponding control signal CTL to drive the switching elements contained in the power output stage 303 for switching, and the input voltage V _{IN is} converted by the power output stage 303 into an output voltage V _{OUT for} supply to the load. The frequency of the clock signal CLK determines the switching period of the main switch QM in the power output stage 303. For illustrative explanation, in a conventional but non-limiting example of FIG. 5, control signal generator 302 may include a comparator 3021 and an RS flip-flop 3022, wherein the clock generated by oscillator 301 The signal CLK is supplied to the set terminal S of the RS flip-flop 3022, and the output of the comparator 3021 is connected to the reset terminal R of the RS flip-flop 3022, and the switch main switch QM is generated at the Q output by the RS flip-flop 3022 for switching. Control signal CTL. The rising edge of the clock signal CLK may set the Q output of the RS flip-flop 3022 to the logic high level, and the high level comparison result of the comparator 3021 may possibly the Q output of the RS flip-flop 3022. The control signal is reset from a logic high level to a logic low level, thereby switching the cycle switch. If we send the sense signal V _CS reflected at the node 101 at the end of the sense resistor R _S at the end of the sense resistor R _{S in} FIG. 1 to the non-inverting input of the comparator 3021, and input at the inverting input of the comparator 3021. A reference voltage V _TH , when the primary current of the primary winding is excessively larger than the specification, that is, the sensing signal V _{CS is} greater than the reference voltage V _TH , causes the comparator 3021 to output a high level to trigger the RS flip-flop 3022 to turn off the main switch QM. This is the current control mode of the flyback voltage converter. The reference voltage V _TH may be a preset voltage value, or may be an output level obtained by comparing a divided voltage value obtained by the output voltage V _OUT through the voltage divider with a threshold voltage V _REF through an error amplifier.

Referring to FIG. 6, in order to detect the primary current flowing through the inductive resistor R _{S in} series with the primary winding 130A, a voltage sensing signal V _CS at the node 101 at one end of the sensing resistor R _S is detected, which is provided in the present invention. A collection unit 280. At the instant when the effective state of the leading edge occlusion signal LEB for shielding the primary spike of the primary current ends, that is, the leading edge occlusion signal LEB in FIG. 3 is flipped from the high level to the low level at the time t ₁₂ The collecting unit 280 needs to detect the instantaneous voltage value applied to the sensing resistor R _S , that is, the voltage value of the voltage sensing signal V _CS at the node 101 at the instant t ₁₂ , which is recorded as the first voltage value V _LEB .

The collecting unit 280 includes at least one detecting module 201 for detecting and capturing voltage values at different times on the sensing resistor R _S because the primary current I _P flowing through the primary winding 130A and the resistance of the sensing resistor R _S are By multiplying, it can be converted into a sensing signal V _CS which is reflected as a voltage value across the sensing resistor R _S , so that the detecting module 201 is also essentially a current detector here. A first voltage follower 401 of the detection module 201 serves as an input buffer having a high input impedance characteristic for connection with a signal source of the sensing signal V _CS , and the high input impedance can isolate the interaction between the front and the rear stages. And the first voltage follower 401 also has a lower output impedance characteristic to reduce the capture time. The positive input terminal of the first voltage follower 401 is connected to the node 101 at one end of the sense resistor R _S , and the negative input terminal of the first voltage follower 401 is connected to its output terminal, so that the first voltage follower 401 is operated by one operation. The amplifier is configured as a voltage follower or unity gain buffer. As an optional rather than an optional item, a resistor R10 may be connected between the node 101 and the positive input terminal of the first voltage follower 401, and a positive input terminal of the first voltage follower 401 is connected to the ground terminal. the capacitor C _1, thereby feeding a smoother sense signal V _CS at the positive input of the first voltage follower 401.

In addition, the acquisition unit 280 further includes a sample-and-hold latch 202 having a storage capacitor C ₂ disposed between the output of the first voltage follower 401 and the node 122 of the storage capacitor C _{2 that is} not grounded. There is a first switch SW1, and the other end of the storage capacitor C ₂ is grounded. The first switch SW ₁ and the context switch mentioned in the present invention are all three-port electronic switches, and they have various options, such as P-type or N-type MOS transistors or bipolar transistors or junction field effect transistors or The combination switch, etc., can be enhanced or depleted. When the first switch SW1 is turned on, the voltage value output by the first voltage follower 401 can be saved to the storage capacitor C ₂ , and when the first switch SW1 is turned off, the storage capacitor C _{2 is} no longer received from the detection module 201. Voltage information. The leading edge LEB mask signal is applied to the control terminal of the first switch SW1, such as a gate, a leading edge LEB mask signal from time t ₁₁ to t T _{LEB 12} between the time period at a high level logic state, the first switch SW1 at this stage Was connected.

In any one switching cycle of the main switch QM, QM start timing from the main switch is turned t ₁₁ to the leading edge LEB mask signal inverted from the high level to the low level time t _12, the dynamic rise sensing signal V _CS has been are input to the first voltage follower 401, but once the leading edge LEB mask signal inverted from the time t ₁₂ to the low level and the first switch SW1 is turned off, since the time t after the leading edge of the shield ₁₂ to enter its next signal LEB Prior to the high level state of the cycle, the first voltage follower 401 is unable to convert the raw voltage value at node 101 to a secondary voltage to the sample and hold latch 202. And the analog signal corresponding to the sensing signal V _CS at time t ₁₂ is tracked and captured by the detecting module 201, and the actual transient voltage of the voltage sensing signal V _{CS is} output from the first voltage follower 401 at this time. The terminal is sent out to the storage capacitor C ₂ , which is equal to the resistance of the sense resistor R _S multiplied by the leading edge shielding current value I _{LEB at} this moment, the storage capacitor C _{2 of the} sample-and-hold latch 202 is charged, and the sensing signal V _CS becomes The data stored on the storage capacitor C ₂ . With this scheme, the sample-and-hold latch 202 and the detection module 201 are disconnected from the time t ₁₂ until the high level of the next period of the leading edge masking signal LEB, and the sample-and-hold latch 202 only stores t _{12 .} The transient voltage sensing signal V _CS information applied to the sensing resistor R _S at the moment, that is, the voltage value finally outputted by the first voltage follower 401 to the sample-and-hold latch 202 in one period T _S is fixed at t The voltage value represented by the leading edge shielding current value I _LEB information corresponding to time ₁₂ is recorded as the first voltage value V _LEB .

The acquisition unit 280 further includes a second voltage follower 402 having a positive input coupled to the node 122 for reading voltage data on the storage capacitor C ₂ and a negative input coupled to the output of the second voltage follower 402. The second voltage follower 402 is also configured by an operational amplifier as a voltage follower or unity gain buffer. The second voltage follower 402 acts as an output buffer with a higher input impedance characteristic to prevent voltage drops maintained by the storage capacitor and has a lower output impedance characteristic for connection to the load, by the second voltage follower 402 The first voltage value V _LEB stored at the node 122 is output to the next stage.

The first voltage value V _LEB on the sense resistor R _S corresponding to the time t _{12 at} which the leading edge masking signal LEB transitions from the high level to the low level and fails at the positive phase input of the comparator 501 in FIG. 7 is, for example, A first voltage value V _LEB of a known amount acquired by the output of the second voltage follower 402 may be output to the comparator 501, and the reference voltage V _TH mentioned above may be input at the inverting input of the comparator 501. At the same time, the comparison result of the comparator 501 is also output to the oscillator 301, and the operation mode of the oscillator 301 is triggered by the comparison result of the comparator 501. When the comparator 501 compares the result to a low level, that is, the first voltage value V _LEB does not exceed the reference voltage V _TH , the oscillator 301 is in a first operational mode such as a normal operation, and the comparison result triggers the oscillator 301 to The conventional first frequency is used to output the clock signal CLK, and the clock signal CLK having the first frequency determines the switching period of the main switch QM in the first operating mode. Conversely, when the comparator 501 compares the result to a high level, that is, the first voltage value V _{LEB is} greater than the reference voltage V _TH , the oscillator 301 turns down the output frequency to enter the second mode of operation. As a result, the oscillator 301 is triggered to output the clock signal CLK at the second frequency, and the clock signal CLK having the second frequency determines the switching period of the main switch QM in the second mode of operation.

In the startup phase of the voltage converter, when the primary current I _P rises to such that the first voltage value V _LEB on the sense resistor R _S is greater than the reference voltage V _TH at time t ₁₂ , it is generally considered that the current flowing in the primary side is too large. The comparison result of the comparator 501 immediately triggers the oscillator 301 to operate in the second mode of operation, at which time we define the second frequency of the clock signal CLK to be less than the first frequency of the oscillator 301 in the first mode of operation. As an example, for example, the second frequency may be one-half of the first frequency, or even lower. The oscillator 301 is forced to operate in the second mode of operation compared to the first mode of operation of the conventional operation, reducing the clock frequency of the oscillator 301, which is equivalent to forcing the control oscillator 301 to decrease the frequency at which the trigger control signal generator 302 generates the control signal CTL. , so that the main switch QM is turned off during a certain period in which the primary current is overcurrentd, and the main switch QM is compared in a normal period in which no overcurrent occurs (eg, the oscillator 301 operates in the first operational mode phase) The closed period is long to suppress the primary current I _{P from} rising too much beyond the specification value, thereby overcoming the problem of excessive inrush current proposed by the background art. After the frequency of the clock signal CLK transmitted by the oscillator 301 is lowered, the primary current flowing through the primary winding can be prevented from exceeding a preset value, and the preset value multiplied by the resistance value of the sensing resistor R _S should not exceed the reference voltage value V _{TH .} .

In the startup phase of the voltage converter, the primary current waveform 371 in the eighth diagram without the inventive scheme can easily rise above the specification value, and the corresponding induced signal V _CS easily exceeds the reference voltage V _TH , while the primary using the inventive scheme The current waveform 372 is generally within the specification value, which suppresses the inrush current and protects the device. In the normal use phase of the voltage converter even if the primary side overcurrent does not occur, for example, the clock signal CLK output from the oscillator 301 has the first frequency phase, the primary current waveform 382 in the ninth diagram applicable to the inventive scheme is still Within the specification value, as a comparison, the prior art scheme may cause the primary current waveform 381 to generate, for example, subharmonic noise, and although it is based on the protection device during the startup phase, once the converter enters the heavy load phase, it may be erroneous. Triggered protection measures are not suitable. Therefore, in the present invention, during the period of the leading edge masking signal LEB itself, it may be turned to a high level at the timing when the control signal turns on the main switch QM, or may be slightly earlier than the timing at which the control signal turns on the main switch QM, although In the prior art and even in the present invention, the main purpose of the leading edge masking signal LEB is to ignore the initial damped oscillation of the sensing signal V _CS sampled on the resistor R _S at the instant of turning on the main switch QM, preventing the main switch QM from being Premature erroneous termination in each cycle, but the present invention additionally utilizes the leading edge occlusion signal LEB to prevent the primary current flowing through the primary winding from flowing too high in the startup phase beyond the preset value.

The exemplary embodiments of the specific constructions of the specific embodiments have been described above by way of illustration and the accompanying drawings, which set forth the preferred embodiments. Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are intended to cover all such modifications and modifications in The scope and content of any and all equivalents within the scope of the claims are intended to be within the scope and scope of the invention.

301‧‧‧Oscillator

501‧‧‧ Comparator

Claims (12)

A circuit for suppressing excessive current in a voltage converter, having a main switch for controlling a primary winding to be turned on or off, wherein: comprising: an acquisition unit for shielding a primary current starting spike The leading edge masking signal is turned from the logic high level state to the logic low level state, and detects a first voltage applied to one of the sensing resistors in series with the primary winding at the instant when the active state of the leading edge masking signal ends. a comparator, a first voltage value is input to one of the comparator inputs, and a reference voltage is input to an inverting input of the comparator; and a comparison result of the comparator output is transmitted to an oscillator When the first voltage value exceeds the reference voltage, the comparison result triggers a decrease in the frequency of the clock signal from an oscillator to prevent the primary current flowing through the primary winding from exceeding a preset value. A circuit for suppressing an excessive current in a voltage converter according to claim 1, wherein when the first voltage value does not exceed the reference voltage, setting the oscillator to be in a first operating mode a frequency output clock signal to determine a switching period of a main switch; and when the first voltage value exceeds the reference voltage, setting the oscillator to output a clock signal at a second frequency in the second operating mode, Determining a switching period of the main switch, the second frequency being lower than the first frequency. A circuit for suppressing excessive current in a voltage converter according to claim 2, wherein the second frequency does not exceed one-half of the first frequency. A circuit for suppressing excessive current in a voltage converter according to the first aspect of the invention, wherein the acquisition unit comprises a first voltage follower, and the effective state of the leading edge shielding signal ends in each cycle The first The information of the voltage value is sent to one of the sampling and holding latches of the collecting unit for storage, and the voltage held by the sample holding latch is output by the second voltage follower of the one of the collecting units. A circuit for suppressing excessive current in a voltage converter according to claim 4, wherein a positive input terminal of the first voltage follower is coupled to a common one of the sense resistor and the main switch At the node, a voltage sensing signal indicative of the magnitude of the primary current flowing through the sense resistor is delivered to the positive input of the first voltage follower at the common node. A circuit for suppressing excessive current in a voltage converter according to claim 5, wherein a connection between an output of the first voltage follower and the sample-and-hold latch is controlled by the a first switch of the leading edge masking signal, the first switch is turned off at the end of the active state of the leading edge masking signal, so that the leading edge shielding signal is flipped from the high level to the low level in each switching period of the main switch After the time when the active state is terminated, the voltage value data held by the sample hold latch maintains the transient state of the first voltage value applied to the sense resistor at the instant when the leading edge masking signal is valid. A method for suppressing excessive current in a voltage converter, wherein a primary switch is used to control a primary winding to be turned on or off, wherein: a shielding edge signal is shielded from a logic high level for shielding a primary peak of the primary current Instantly flipping the quasi-state into a logic low level state, using an acquisition unit to detect a first voltage value indicative of a sense resistor applied in series with the primary winding at the instant when the active state of the leading edge masking signal ends; One of the comparators inputs the first voltage value at the non-inverting input terminal and a reference voltage at one of the inverting input terminals of the comparator; and Transmitting the comparison result of the comparator output to an oscillator. When the first voltage value exceeds the reference voltage, the comparison result triggers a decrease in the frequency of the clock signal sent by an oscillator to avoid flowing through the primary winding. The primary current is outside the preset value. A method for suppressing excessive current in a voltage converter according to claim 7, wherein when the first voltage value does not exceed the reference voltage, setting the oscillator to be in a first operating mode a frequency output clock signal to determine a switching period for controlling the primary winding to turn on or off one of the main switches; and when the first voltage value exceeds the reference voltage, setting the oscillator in the second operating mode The clock signal is outputted at a second frequency to determine a switching period of the main switch, and the second frequency is lower than the first frequency. A method of suppressing excessive current in a voltage converter according to claim 8 of the invention, wherein the second frequency does not exceed one-half of the first frequency. A method for suppressing excessive current in a voltage converter according to claim 7, wherein a first voltage follower of the acquisition unit is instantaneous at the end of the active state of the leading edge masking signal in each period Transmitting the first voltage value to one of the sampling unit holding the latch storage, and converting, by the second voltage follower of the acquiring unit, the voltage information held by the sample holding latch into the first The voltage value is equivalent to the voltage value and is output. A method for suppressing excessive current in a voltage converter according to claim 10, wherein a positive input terminal of the first voltage follower is coupled to a common one of the sense resistor and the main switch Node, table A voltage sensing signal stimulating the magnitude of the primary current flowing through the sense resistor is delivered to the positive input of the first voltage follower at the common node. A method for suppressing excessive current in a voltage converter according to claim 11 wherein a connection between an output of the first voltage follower and the sample-and-hold latch is controlled by the a first switch of the leading edge masking signal, the first switch is turned off at the end of the active state of the leading edge masking signal, so that the masking signal is flipped from the high level to the low level from the leading edge during each switching period of the main switch After the time when the active state is terminated, the voltage data held by the sample-and-hold latch maintains the transient state of the first voltage value applied to the sense resistor at the instant when the leading edge masking signal is asserted.