TWI546895B - Semiconductor structure and manufacturing method of the same - Google Patents

Description

Semiconductor structure and method of manufacturing same

The present disclosure relates to a semiconductor structure and a method of fabricating the same, and more particularly to a semiconductor structure having an etch barrier structure and a method of fabricating the same.

In recent years, the structure of semiconductor elements has been constantly changing, and the memory storage capacity of the elements has also been increasing. Memory devices are used in many products, such as MP3 players, digital cameras, computer files, and the like. As applications increase, so does the demand for memory devices toward smaller sizes and larger memory capacities. In response to this demand, it is necessary to manufacture a memory device having a high component density and a small size, and thus the difficulty of the process is improved.

Therefore, designers are all committed to developing a three-dimensional memory device that not only has many stacked planes but also achieves higher memory storage capacity, has a smaller size, and has a simplified process and good stability.

The disclosure relates to a semiconductor structure and a method of fabricating the same. In an embodiment, in the semiconductor structure, the conductive layer in the vertical extension region is formed on the etch barrier structure such that the vertically extending conductive layer can obtain good support provided by the etch barrier structure to provide a structure between the stacked structure and the contact plug. Good and stable electrical contact.

In accordance with an embodiment of the present disclosure, a semiconductor structure is proposed. The semiconductor structure includes a substrate, a stacked structure, an etching stop structure, a plurality of memory structures, and a first filled slit groove. The substrate has a trench. The stacked structure has a horizontal extension and a vertical extension, and the vertical extension extends along a sidewall of the recess, wherein the stacked structure comprises a plurality of conductive layers and a plurality of insulating layers, which are interlaced and stacked in the grooves. An etch barrier structure is formed in the vertical extension of the stacked structure. The memory structure passes vertically through the conductive and insulating layers in the horizontal extension of the stacked structure. A first fill sipe is formed in the stacked structure, wherein the conductive layer and the insulating layer in the vertical extension are formed on the etch stop structure and between the etch stop structure and the first fill nip.

In accordance with another embodiment of the present disclosure, a method of fabricating a semiconductor structure is presented. The method of fabricating a semiconductor structure includes the following steps. Providing a substrate having a recess; forming a stack structure having a horizontal extension and a vertical extension, the vertical extension extending along a sidewall of the recess, wherein the stack comprises a plurality of conductive layers and a plurality of An insulating layer, staggeredly stacked in the recess; forming an etch stop structure in the vertical extension of the stacked structure; forming a plurality of memory structures, vertically passing through the conductive layer and the insulating layer in the horizontal extension of the stacked structure; A first fill is scribed in the stacked structure, wherein the conductive layer and the insulating layer in the vertical extension are formed on the etch stop structure and between the etch stop structure and the first fill nip.

In order to better understand the above and other aspects of the present invention, the preferred embodiments are described below, and in conjunction with the drawings, the detailed description is as follows:

10, 20‧‧‧ semiconductor structure
100‧‧‧Substrate
100a‧‧‧ upper surface
100b‧‧‧ bottom
100s‧‧‧ side wall
100t, 6300‧‧‧ grooves
200, 5200‧‧‧ stacked structure
210‧‧‧ Conductive layer
220‧‧‧Insulation
230‧‧‧Material layer
240‧‧ ‧ vacancies
300‧‧‧etch barrier structure
300'‧‧‧etch block
310‧‧‧First side wall
320‧‧‧ second side wall
330‧‧‧ bottom surface
400‧‧‧Dielectric structure
410‧‧‧First fill grooving
420‧‧‧Second fill grooving
510, 520‧ ‧ contact plug
600‧‧‧Oxide spacer
710‧‧‧Top cover
720‧‧‧hard mask layer
730‧‧‧ dielectric materials
800‧‧‧ memory structure
810‧‧‧ memory layer
820‧‧‧channel layer
830‧‧‧Insulation materials
910‧‧‧first slot
920‧‧‧Second slot
2A-2A', 2B-2B', 2C-2C', 6A-6A', 6B-6B', 7A-7A', 7B-7B', 8A-8A', 8B-8B', 8C-8C', 9A-9A', 9B-9B', 10A-10A', 10B-10B', 10C-10C', 11A-11A', 11B-11B', 11C-11C', 12A-12A', 12B-12B', 13~13A‧‧‧ hatching
D1, D2‧‧‧ distance
D3‧‧‧Width
H‧‧‧ horizontal extension
V‧‧‧ vertical extension

1 is a top view of a semiconductor structure in accordance with an embodiment of the present disclosure.
FIG. 1A is a top view of a semiconductor structure of another embodiment of the present disclosure.
Fig. 2A is a schematic cross-sectional view taken along line 2A-2A' of Fig. 1.
2B is a schematic cross-sectional view taken along line 2B-2B' of FIG. 1.
Fig. 2C is a schematic cross-sectional view taken along line 2C-2C' of Fig. 1.
3 to 13A are schematic views showing a method of fabricating a semiconductor structure in accordance with an embodiment of the present invention.

In the embodiments disclosed herein, a semiconductor structure and a method of fabricating the same are presented. In an embodiment, in the semiconductor structure, the conductive layer in the vertical extension region is formed on the etch barrier structure such that the vertically extending conductive layer can obtain good support provided by the etch barrier structure to provide a structure between the stacked structure and the contact plug. Good and stable electrical contact. However, the examples are for illustrative purposes only and are not intended to limit the scope of the invention. In addition, the drawings in the embodiments are omitted in order to clearly show the technical features of the present invention.

Please refer to FIG. 1 , 2A to 2C , FIG. 1 is a top view of the semiconductor structure 10 according to an embodiment of the disclosure, and FIG. 2A is a cross-sectional view along the line 2A-2A′ of FIG. 1 . 2B is a cross-sectional view taken along line 2B-2B' of FIG. 1, and FIG. 2C is a cross-sectional view taken along line 2C-2C' of FIG. 1. In the embodiment, the semiconductor structure 10 is, for example, the main structure of a three-dimensional memory device.

As shown in FIGS. 1 and 2A-2C, the semiconductor structure 10 includes a substrate 100, a stacked structure 200, a plurality of memory structures 800, an etching stop structure 300, and a first filled trench. Groove) 410. The substrate 100 has a trench 100t (please refer to FIG. 3 at the same time). The stacked structure 200 has a horizontal extension H and a vertical extension V. The vertical extension V extends along one sidewall 100s of the recess 100t. The stacked structure 200 includes a plurality of conductive layers 210 and a plurality of insulating layers 220, and a conductive layer 210 and The insulating layers 220 are interlaced and stacked in the recess 100t. The memory structure 800 passes vertically through the conductive layer 210 and the insulating layer 220 in the horizontal extension H of the stacked structure 200. The etch stop structure 300 is formed in the vertical extension V of the stacked structure 200. The first filling grooving 410 is formed in the stacked structure 200, and the conductive layer 210 and the insulating layer 220 in the vertical extending region V are formed on the etch barrier structure 300 and between the etch barrier structure 300 and the first filling grooving 410.

In an embodiment, the conductive layer 210 and the insulating layer 220 in the vertical extension V are formed on the etch barrier structure 300 and between the etch barrier structure 300 and the first fill scribe 410 such that the conductive layer 210 extends vertically in the Z direction. Good support provided by the etch stop structure 300 can be obtained without the conductive layer 210 being deformed or bounced to provide good and stable electrical contact between the stacked structure 200 and the contact plug.

In the embodiment, as shown in FIGS. 1A and 2A-2C, the semiconductor structure 10 more selectively includes an oxide spacer 600. The oxide spacer layer 600 is located between the stacked structure 200 and the sidewall 100s of the recess 100t and is located between the first sidewall 310 of one of the etch barrier structures 300 and the sidewall 100s of the recess 100t.

In another embodiment, the semiconductor structure 10 may not include an oxide spacer layer (not shown), and the first sidewall 310 of the etch barrier structure 300 abuts the sidewall 100s of the recess 100t. In other words, the etch stop structure 300 can extend to and contact the sidewall 100s of the recess 100t.

In the embodiment, as shown in FIGS. 1B and 2B-2C, one of the second sidewalls 320 of the etch barrier structure 300 may be located in the horizontal extension H of the stacked structure 200.

In the embodiment, as shown in the first, second, and second embodiments, the bottom surface 330 of the etch barrier structure 300 can directly contact one of the bottom surfaces 100b of the recess 100t.

In other words, the etch stop structure 300 may cover a cross section of the vertical extension V of the stacked structure 200 in the X-Z direction, and the conductive layers 210 on both sides of the etch barrier structure 300 in the Y direction are separated by the etch barrier structure 300.

In the embodiment, as shown in FIG. 1, the distance D1 between the etching stopper structure 300 and the first filling slit 410 is, for example, 20 to 200 nanometers (nm). In the embodiment, the cross-sectional width of the memory structure 800 is, for example, 5 to 100 nm.

In an embodiment, as shown in FIGS. 2A-2C, the semiconductor structure 10 further includes a dielectric structure 400 and a plurality of contact plugs 510/520. The dielectric structure 400 is located on the substrate 100 and the stacked structure 200. Contact plugs 510 / 520 are formed in the dielectric structure 400 , wherein each of the contact plugs 510 / 520 is electrically connected to each of the corresponding conductive layers 210 of the vertical extensions V of the stacked structure 200, respectively.

In an embodiment, as shown in FIG. 1 , the semiconductor structure 10 further includes a second filling slot 420 . A second fill sipe 420 is formed in the stack structure 200 between the first fill nip 410 and the second fill nip 420. In the embodiment, the distance D2 between the etching stopper structure 300 and the second filling slot 420 is, for example, 20 to 200 nm.

In one embodiment, the first filling slot 410 and the second filling slot 420 may respectively include an insulating layer and a conductive filler, wherein the insulating layer is formed on the surface of all the slots, and the conductive filler is formed on the insulating layer. And fill this slot. In an embodiment, the insulating layer is, for example, a tantalum oxide layer, and the conductive filler is, for example, titanium nitride (TiN) and tungsten, wherein a titanium nitride layer is formed on the insulating layer, and tungsten is formed on the titanium nitride layer and fills the cut. groove. In another embodiment, the first filling slot 410 and the second filling slot 420 can each include an insulating filler. In an embodiment, the distance between the first fill slot 410 and the second fill slot 420 is, for example, about 1000 microns.

In an embodiment, the conductive layer 210 and the insulating layer 220 in the vertical extension V of the stacked structure 200 are further located between the etch stop structure 300 and the second fill scribe 420.

In the embodiment, the conductive layer 210 and the insulating layer 220 in the vertical extension region V are formed on the etch barrier structure 300 and directly contact the etch barrier structure 300, so even if the conductive layer 210 and the insulating layer 220 extend vertically in the Z direction and along the X direction With a very small thickness, good support provided by the etch stop structure 300 can still be obtained, and the conductive layer 210 is not deformed or bounced to provide good and stable electrical properties between the stacked structure 200 and the contact plugs 510/520. Contact, thereby improving the stability of the semiconductor structure 10.

In an embodiment, the conductive layer 210 in the horizontal extension H of the stacked structure 200 may include polysilicon, tungsten, or a combination of the two, and the conductive layer 210 in the vertical extension V of the stacked structure 200 may include tungsten. The conductive layer 210 in the vertical extension V is electrically connected to the contact plugs 510/520, and the resistance of the tungsten is less than the resistance of the polysilicon, so that the conductive layer 210 in the vertical extension V includes tungsten to greatly reduce the stacking. The resistance of the electrical pickup region of the structure.

In an embodiment, the semiconductor structure is, for example, the main structure of a three-dimensional memory device, and the conductive layer 210 is, for example, a word line.

FIG. 1A is a top view of a semiconductor structure 20 of another embodiment of the present disclosure. The same or similar components as those of the above-mentioned embodiments are denoted by the same or similar components, and the related descriptions of the same or similar components are referred to the foregoing, and are not described herein again.

As shown in FIG. 1A, in an embodiment, the etch stop structure 300 can include a plurality of etch stop blocks 300'. In the etch stop block 300', the distance D1 between the etch stop block 300' closest to the first fill grooving 410 and the first fill grooving 410 is, for example, 20 to 200 nm, closest to the second fill. The distance D2 between the etch stop block 300' of the grooving 420 and the second fill grooving 420 is, for example, 20 to 200 nm.

3 to 12A are schematic views showing a method of fabricating a semiconductor structure in accordance with an embodiment of the present invention.

As shown in FIG. 3, a substrate 100 having a groove 100t is provided. In an embodiment, for example, an etching process is performed to form the recess 100t in the substrate 100. In an embodiment, the oxide spacer layer 600 can be selectively formed on the sidewall 100s of the recess 100t.

As shown in FIGS. 4 to 5, a stacked structure is formed in the recess 100t. In the embodiment, the manufacturing method of forming the stacked structure in the recess 100t includes, for example, the following steps.

As shown in FIG. 4, a plurality of material layers 230 and a plurality of insulating layers 220 may be formed, and the material layer 230 and the insulating layer 220 are alternately stacked in the recess 100t and on the substrate 100. In an embodiment, the material layer 230 may be a conductive material layer or a sacrificial layer. The conductive material layer includes, for example, polycrystalline germanium, and the sacrificial layer includes, for example, tantalum nitride (SiN), cerium oxynitride (SiON), lanthanum oxynitride (SiCN), or any combination thereof. In this embodiment, the insulating layer 220 is tantalum oxide, and the material layer 230 is, for example, a sacrificial layer, and the material thereof is tantalum nitride.

As shown in FIG. 5, the material layer 230 and the insulating layer 220 are planarized such that the material layer 230 and the insulating layer 220 are coplanar with the upper surface 100a of the substrate 100, and then a dielectric material 730 is formed on the material layer 230 and the insulating layer 220. And forming a cap layer 710 and a hard mask layer 720 on the planarized material layer 230, the insulating layer 220, and the upper surface 100a of the substrate 100. In an embodiment, the cap layer 710 is, for example, a hafnium oxide layer, and the hard mask layer 720 is, for example, a tantalum nitride layer. So far, the stacked structure 5200 is formed as shown in FIG. 5, the stacked structure 5200 has a horizontal extension H and a vertical extension V, and the vertical extension V extends along the sidewall 100s of the groove 100t, and the material layer 230 and the insulation layer 220 are alternately arranged. Stacked in the groove 100t. After the material layer 230 is replaced with a conductive material in a subsequent step, the stacked structure 200 is formed.

As shown in FIGS. 6-7B, an etch stop structure 300 is formed in the vertical extension V of the stacked structure 5200. The manufacturing method of forming the etching stopper structure 300 includes, for example, the following steps.

Fig. 6A is a cross-sectional view taken along line 6A-6A' of Fig. 6, and Fig. 6B is a cross-sectional view taken along line 6B-6B' of Fig. 6. As shown in FIGS. 6-6B, a recess 6300 is formed in the vertical extension V of the stacked structure 5200. In an embodiment, the recess 6300 is formed, for example, by an etching process that does not have a selection ratio for the material layer 230 and the insulating layer 220.

As shown in Figures 6 and 6B, in an embodiment, one end of the recess 6300 can extend to the oxide spacer layer 600, and the other end of the recess 6300 can extend into the horizontal extension H. In another embodiment, one end of the recess 6300 may even extend to the side wall 100s (not shown) that exposes the recess 100t. Moreover, in the embodiment, the bottom of the recess 6300 may expose the bottom surface 100b of the recess 100t.

Fig. 7A is a cross-sectional view taken along line 7A-7A' of Fig. 7, and Fig. 7B is a cross-sectional view taken along line 7B-7B' of Fig. 7. As shown in FIGS. 7-7B, an etch stop material is filled in the recess 6300 to form an etch stop structure 300. After filling the etch stop material, a CMP process can be performed to planarize the surface of the etch stop structure 300.

8A is a cross-sectional view taken along line 8A-8A' of FIG. 8, FIG. 8B is a cross-sectional view taken along line 8B-8B' of FIG. 8, and FIG. 8C is a view along line 8. A schematic cross-sectional view of section line 8C-8C'. As shown in Figs. 8-8C, a memory structure 800 is formed. In this step, the memory structures 800 pass vertically through the material layer 230 and the insulating layer 220 in the horizontal extension H of the stacked structure 5200. After the material layer 230 is replaced with a conductive material in a subsequent step, the memory structures 800 are vertically passed through the conductive layer 210 and the insulating layer 220 in the horizontal extension H of the stacked structure 200.

As shown in FIGS. 8 to 8C, the method of manufacturing the memory structure 800 includes, for example, the following steps. First, a plurality of through openings are formed by an etching process, and the through openings vertically pass through the material layer 230 and the insulating layer 220 in the horizontal extension H of the stacked structure 5200, and the etching process is performed on the material layer 230 and the insulating layer. 220 does not have a selection ratio. A memory layer 810 is then formed over the sidewalls of the through opening, and then a channel layer 820 is formed over the memory layer 810, and an insulating material 830 is then filled over the channel layer 820 in the through opening. In the embodiment, as shown in FIG. 8C, the through opening extends vertically downward into the substrate 100. In another embodiment, the through opening may also extend vertically downward and stop on the surface of the substrate 100 (not shown).

In an embodiment, the memory layer 810 is, for example, a composite layer of oxide-nitride-oxide (ONO), yttrium-rhenium nitride-ytterbium oxide-yttria-yttrium oxide-oxide (oxide- Nitride-oxide-nitride-oxide, ONONO) composite layer or yttrium oxide-yttria-yttria-yttria-oxide-nitride-oxide-nitride- Oxide, ONONONO) composite layer, but not limited to this. Channel layer 820 is, for example, an undoped polysilicon. Insulating material 830 is, for example, tantalum oxide, tantalum nitride, or other suitable dielectric material.

In one embodiment, the memory structure 800 can all be formed in the horizontal extension H (not shown). In one embodiment, as shown in FIG. 8C, some memory structures 800 may be formed in the etch stop structure 300.

As shown in FIGS. 9-12B, a first fill trench 410 is formed in the stacked structure 200, wherein the conductive layer 210 and the insulating layer 220 in the vertical extension V are located between the etch stop structure 300 and the first fill trench 410. . In the embodiment, as shown in FIGS. 9-12B, a second filling slot 420 may be formed in the stack structure 200, wherein the etch barrier structure 300 is located between the first filling slot 410 and the second filling slot 420. The manufacturing method of forming the first filling slit 410, the second filling slit 420, and the conductive layer 210 of the stacked structure 200 includes, for example, the following steps.

Fig. 9A is a cross-sectional view taken along line 9A-9A' of Fig. 9, and Fig. 9B is a cross-sectional view taken along line 9B-9B' of Fig. 9. As shown in FIGS. 9-9B, a first slot 910 and a second slot 920 are formed in the stack structure 5200. The first slot 910 and the second slot 920 pass through the vertical extension of the stack structure 5200. And a material layer 230 and an insulating layer 220 in the horizontal extension H. In the embodiment, the first slit 910 and the second slit 920 are formed, for example, by an etching process, and the etching process does not have a selection ratio for the material layer 230 and the insulating layer 220.

10A is a cross-sectional view taken along line 10A-10A' of FIG. 10, FIG. 10B is a cross-sectional view taken along line 10B-10B' of FIG. 10, and FIG. 10C is a view along line 10 A schematic cross-sectional view of section line 10C-10C'. As shown in FIGS. 10-10C, the material layer 230 in the vertical extension V is removed.

As shown in FIGS. 10-10C, in the present embodiment, the material layer 230 is, for example, a sacrificial layer, and a phosphoric acid (H ₃ PO ₄ ) solution is used as an etching solution, and the phosphoric acid solution passes through the first slit 910 and the second slit 920. The material layer 230 in the vertical extension V and the horizontal extension H is removed to form a vacancy 240. At the same time, the etching solution can also remove the hard mask layer 720.

As shown in FIGS. 10 to 10C, since the width D3 of the horizontal extension H in the Y direction can be long, for example, about 1000 micrometers (μm), it is necessary to pass the etching of the etching liquid to enable the level. All of the material layers 230 (sacrificial layers) in the extension H located between the first slit 910 and the second slit 920 are removed. In this step, since the vertical memory structure 800 passes through the horizontal extension H, the insulating layer 220 layered by the vacancies 240 may be supported via the vertical memory structure 800, via the first slot 910 and the second slice. The trench 920 is etched into the etchant to etch away all of the material layers 230, while the insulating layer 220, which is spaced apart by the vacancies 240, can be supported via a plurality of vertical memory structures 800 without collapse.

As shown in FIGS. 10-10C, the distance D1 between the etch stop structure 300 in the vertical extension V and the first slot 910 and the second slot 920 is compared to the width D3 of the horizontal extension H in the Y direction. It is much shorter than D2, for example, about 20~200 nm. Compared to the case where the etch stop structure 300 is not provided, when the material layer 230 vertically extending in the vertical extension V is removed, the vertically extending insulating layer 220 separated by the vacancies 240 is easily deformed or collapsed. . According to an embodiment of the present disclosure, since the distances D1 and D2 are relatively short, the material layer 230 in the vertical extension V can be easily completely removed by over-etching of the etching solution and stopped at the etching stopper structure 300; The spaced apart insulating layer 220 extends vertically and is formed on the etch barrier structure 300, that is, the insulating layer 220 directly contacts the etch barrier structure 300, so the insulating layer 220 can obtain good support provided by the etch stop structure 300. , will not deform or collapse, and thus stabilize the entire structure in the process.

In another embodiment, the material layer 230 is, for example, a layer of conductive material, for example, including polysilicon, and the degree of overetching of the etchant can also be adjusted to completely remove the material layer 230 in the vertical extension V and stop at the etch stop structure 300. Only a portion of the material layer 230 (not shown) adjacent to the first slot 910 and the second slot 920 in the horizontal extension H is partially removed. As a result, the insulating layer 220 of the vertical extension region V can still obtain good support provided by the etch barrier structure 300 without being deformed or smashed, and can stabilize the entire structure in the process.

11A is a cross-sectional view taken along line 11A-11A' of FIG. 11, FIG. 11B is a cross-sectional view taken along line 11B-11B' of FIG. 11, and FIG. 11C is a view along line 11 A schematic cross-sectional view of section line 11C-11C'. As shown in FIGS. 11 to 11C, the conductive layer 210 is formed.

In this embodiment, for example, the conductive material is filled into the vacancies 240 of the material layer 230 in the vertical extension region V and the horizontal extension region H through the first slit 910 and the second slit 920 to form the conductive layer 210.

As shown in FIGS. 11 to 11C, the conductive material is introduced into the vacancies 240 through the first slit 910 and the second slit 920. For example, the deposition process is first formed on an outer wall layer of a high dielectric constant material layer 240 in the configuration space memory 800, and the inner wall of the space 240, the high dielectric constant material layer may comprise, for example, aluminum oxide (AlO _x) or oxidation铪 (HfO ₂ ). Next, a conductive fill is formed on the high dielectric constant material layer and fills the vacancies 240. In an embodiment, the conductive filler includes, for example, titanium nitride and tungsten, wherein a titanium nitride layer is formed on the high dielectric constant material layer, and tungsten is formed on the titanium nitride layer and fills the vacancy 240.

Next, an etchant is passed through the first slit 910 and the second slit 920 to remove the conductive filler protruding from the vacancy 240 into the first slit 910 and the second slit 920, so as to be filled in different vacancies. Each of the conductive filler portions in 240 is electrically disconnected from each other to form a conductive layer 210. So far, the stacked structure 200 is formed.

In another embodiment, the material layer 230 is, for example, a conductive material layer, for example, including polysilicon, and the material layer 230 in the horizontal extension H is not completely removed, and the conductive material is passed through the first slit 910 and the second slit. 920 fills in the formed vacancies 240 after the material layer 230 in the vertical extension V is removed. As a result, the conductive material filled in the vacancy 240 in the vertical extension V and the material layer 230 (conductive material layer) in the horizontal extension H form the conductive layer 210.

Fig. 12A is a cross-sectional view taken along line 12A-12A' of Fig. 12, and Fig. 12B is a cross-sectional view taken along line 12B-12B' of Fig. 12. As shown in FIGS. 12 to 12B, a first filling slit 410 and a second filling slit 420 are formed.

In one embodiment, an insulating layer is first formed on the surface of the dicing trench by a deposition process, and then a conductive filler is formed on the insulating layer and filled with the dicing. The insulating layer may include hafnium oxide (SiO2), tantalum nitride (SiN), or a low dielectric constant material. The conductive filler includes, for example, titanium nitride and tungsten, wherein a titanium nitride layer is formed on the insulating layer, and tungsten is formed on the titanium nitride layer and fills the slit.

In another embodiment, for example, an insulating filler is filled in the first slit 910 and the second slit 920 to form a first filling slit 410 and a second filling slit 420.

In an embodiment, after filling the conductive filler or the insulating filler in the first slit 910 and the second slit 920, a chemical mechanical polishing process may be performed to planarize the first filling slit 410 and the second filling slit. The upper surface of 420.

Fig. 13A is a schematic cross-sectional view along section line 13A-13A' of Fig. 13. As shown in FIGS. 13-13A, a dielectric structure 400 is formed on the substrate 100 and the stacked structure 200.

Referring to FIGS. 1 and 2A-2C, a contact plug 510/520 is formed in the dielectric structure 400, wherein each of the contact plugs 510/520 is electrically connected to each of the vertical extensions V of the stacked structure 200. Layer 210. For example, the contact plug 510 located adjacent to the first filling slot 410 is electrically connected to the odd-numbered conductive layer 210, and the contact plug 520 located adjacent to the second filling slot 420 is electrically connected to the even-numbered conductive strips. Layer 210. In this way, according to the embodiment of the present disclosure, the contact plugs 510 / 520 are electrically connected to the spaced conductive layers 210 to increase X, compared to the design in which all the contact plugs are disposed on the same side and in the same row. The pitch of the contact plugs in the direction reduces the misalignment error that can be generated by the process.

In the method of fabricating a semiconductor structure according to another embodiment of the present invention, referring to FIG. 1A and FIGS. 6-7B, a plurality of recesses 6300 may be formed in the vertical extension V of the stacked structure 5200, and then etched. The barrier material is formed in the plurality of recesses 6300 to form a plurality of etch stop structures 300' to form the semiconductor structure 20 as shown in FIG. 1A.

In conclusion, the present invention has been disclosed in the above preferred embodiments, and is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

10‧‧‧Semiconductor structure

300‧‧‧etch barrier structure

310‧‧‧First side wall

410‧‧‧First fill grooving

420‧‧‧Second fill grooving

510, 520‧ ‧ contact plug

800‧‧‧ memory structure

2A-2A’, 2B-2B’, 2C-2C’‧‧‧ hatching

D1, D2‧‧‧ distance

H‧‧‧ horizontal extension

V‧‧‧ vertical extension

Claims (10)

A semiconductor structure comprising:
a substrate having a trench;
a stacked structure having a horizontal extension and a vertical extension extending along a sidewall of the recess, wherein the stacked structure comprises a plurality of conductive layers and a plurality of insulating layers, interlaced on the stack In the groove;
An etching stop structure formed in the vertical extension of the stacked structure;
a plurality of memory structures vertically passing through the conductive layers and the insulating layers in the horizontal extension of the stacked structure; and a first filled slit groove formed in the stacked structure, wherein the memory structure The conductive layers and the insulating layers in the vertical extension are formed on the etch stop structure and between the etch stop structure and the first fill sipe.
The semiconductor structure of claim 1, wherein a first sidewall of the etch barrier structure abuts the sidewall of the recess, and a second sidewall of the etch barrier is located in the horizontal extension of the stack And a bottom surface of the etch barrier structure directly contacts a bottom surface of the recess.
The semiconductor structure of claim 1, wherein the etch barrier structure and the first fill nip are separated by 20 to 200 nanometers (nm).
For example, the semiconductor structure described in claim 1 of the patent scope further includes:
a second filling slot formed in the stack structure, wherein the etch barrier structure is between the first fill trench and the second fill trench, the conductive layers and the insulation in the vertical extension The layer is further between the etch stop structure and the second fill nip.
The semiconductor structure of claim 4, wherein the etch barrier structure comprises:
A plurality of etching stop blocks, wherein the second of the etch stop blocks is closest to the second filling grooving and the second filling grooving system is separated by 20 to 200 nm.
A method of fabricating a semiconductor structure, comprising:
Providing a substrate having a groove;
Forming a stack structure having a horizontal extension region and a vertical extension region extending along a sidewall of the recess, wherein the stack structure comprises a plurality of conductive layers and a plurality of insulating layers, staggered ( Interlaced) stacked in the groove;
Forming an etch stop structure in the vertical extension of the stacked structure;
Forming a plurality of memory structures vertically passing through the conductive layers and the insulating layers in the horizontal extension of the stacked structure; and forming a first filling slit in the stacked structure, wherein the vertical extending region The conductive layers and the insulating layers are formed on the etch stop structure and between the etch stop structure and the first fill dicing.
The method of fabricating a semiconductor structure according to claim 6, wherein a first sidewall of the etch barrier structure abuts the sidewall of the recess, and a second sidewall of the etch barrier is at the level of the stack structure In the extension region, one of the bottom surfaces of the etch barrier structure directly contacts a bottom surface of the recess.
The method of fabricating a semiconductor structure according to claim 6, wherein the etch barrier structure and the first filling grooving system are separated by 20 to 200 nm.
The method for manufacturing a semiconductor structure as described in claim 6 further includes:
Forming a second filling slot in the stack structure, wherein the etch barrier structure is between the first filling slot and the second filling slot, the conductive layer and the insulating layer in the vertical extension More between the etch stop structure and the second fill grooving.
The method of fabricating a semiconductor structure according to claim 9, wherein the forming the etch barrier structure comprises:
A plurality of etch stop blocks are formed, and the second of the etch stop blocks closest to the second fill sipe and the second fill sipe are separated by 20 to 200 nm.