TWI546790B - Source driver device and method for receiving display signal - Google Patents

Description

Source driving device and display signal receiving method

The present invention relates to a source driving device, a timing control device, a display signal receiving method, and a display signal transmitting method, and particularly to a source driving device with frequency band detection, a timing control device, a display signal receiving method, and a display signal transmitting method. .

With the advancement of technology, display panels are gradually becoming popular in people's lives. Whether it's a smart phone with a small-sized panel, an in-vehicle device, a tablet or desktop with a mid-size panel, or even a TV with a large-sized panel, it quickly moves to high-resolution specifications. Furthermore, various multimedia applications, including 3D technology, have also led to an increase in the amount of data supported by the display panel, and the data transmission rate has soared.

However, in practice, due to the increase in panel resolution and data transmission rate, the current panel transmission technology is bound to face bottlenecks. Therefore, how to improve the existing panel transmission technology to match various resolutions and data transmission rates is one of the problems that developers should solve.

The present invention provides a source driving device, a timing control device, a display signal receiving method, and a display signal transmitting method to expand a range of support for display signals of various resolutions and data rates.

The source driving device disclosed in the present invention comprises a locking module, a control module and a decoding module. The locking module selectively performs a locking procedure in the first frequency band or the second frequency band according to the frequency band setting signal, so that the locking module locks the first clock signal synchronized with the first display signal. again The control module is coupled to the locking module for comparing the control voltage and the reference voltage in the locking program to generate a frequency band setting signal. The decoding module is coupled to the locking module to generate a decoding signal according to the first display signal and the first clock signal.

The display signal receiving method disclosed in the present invention is for a source driving device, and includes the following steps. The locking module selectively performs a locking procedure according to the frequency band setting signal in the first frequency band or the second frequency band, and the locking program is configured to lock the first clock signal synchronized with the first display signal. The control module compares the control voltage and the reference voltage in the lock program to generate a band setting signal. Moreover, the decoding module generates a decoding signal according to the first display signal and the first clock signal.

The timing control device disclosed in the present invention comprises a locking module, a control module and an encoding module. The locking module selectively performs a locking procedure in the first frequency band or the second frequency band according to the frequency band setting signal, so that the locking module locks the third clock signal synchronized with the third display signal. Furthermore, the control module is coupled to the locking module for comparing the control voltage and the reference voltage in the locking program to generate a frequency band setting signal. In addition, the encoding module is coupled to the locking module to generate the encoded signal according to the third display signal and the third clock signal.

The signal transmitting method disclosed in the present invention is for a timing control device, and includes the following steps. The locking module selectively performs a locking procedure according to the frequency band setting signal in the first frequency band or the second frequency band, and the locking program is configured to lock the third clock signal synchronized with the third display signal. The control module compares the control voltage and the reference voltage in the lock program to generate a band setting signal. Furthermore, the encoding module generates the encoded signal according to the third display signal and the third clock signal.

According to the source driving device, the timing control device, the display signal receiving method and the display signal transmitting method disclosed in the above, the frequency band detection of the display signal can be automatically detected, which not only improves the efficiency of the clock acquisition but also expands the efficiency. Support range for display signals of various resolutions and data rates.

The above description of the present invention and the following description of the embodiments are intended to illustrate and explain the principles of the invention, and to provide a further explanation of the scope of the invention.

1, 4‧‧‧ source drive

10, 30, 40, 70, 80‧‧‧ locking modules

12, 42, 72, 82‧‧‧ control modules

14, 44‧‧‧ decoding module

20, 22‧‧‧Lock program trace

V _ref ‧‧‧reference voltage

300‧‧‧ phase detection unit

302‧‧‧Voltage generating unit

304‧‧‧ Shock unit

46, 86‧‧‧Switch Module

47, 48, 57, 87, 88, 97‧‧‧ impedance matching module

572, 574, 972, 974‧‧‧ Filter unit

576‧‧‧Multiple units

49, 89‧‧‧Selection module

570, 970‧‧‧ impedance matching unit

7, 8‧‧‧ timing control device

74, 84‧‧‧ coding module

976‧‧ ‧Diversion unit

FIG. 1 is a block diagram of a source driving device according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of frequency band setting according to an embodiment of the present invention.

FIG. 3 is a structural diagram of a locking module according to an embodiment of the present invention.

4 is a block diagram of a source driving device according to another embodiment of the present invention.

FIG. 5 is a structural diagram of a first impedance matching module according to an embodiment of the invention.

FIG. 6 is a flowchart of a method for receiving a display signal according to an embodiment of the present invention.

Figure 7 is a block diagram of a timing control apparatus according to an embodiment of the present invention.

Figure 8 is a block diagram of a timing control apparatus according to another embodiment of the present invention.

FIG. 9 is a structural diagram of a third impedance matching module according to an embodiment of the present invention.

FIG. 10 is a flowchart of a method for transmitting a display signal according to an embodiment of the present invention.

Please refer to FIG. 1 , which is a structural diagram of a source driving device according to an embodiment of the present invention. As shown in FIG. 1 , the source driving device 1 includes a locking module 10 , a control module 12 , and a decoding module 14 . The locking module 10 receives the first display signal from the timing control device, and selectively performs a locking procedure in the first frequency band or the second frequency band according to the frequency band setting signal, so that the locking module 10 is locked with the first display signal. The first clock signal of the synchronization. Furthermore, the control module 12 is coupled to the locking module 10 for comparing the control voltage and the reference voltage in the locking program to generate a frequency band setting signal. In addition, the decoding module 14 is coupled to the locking module 10 to generate a decoding signal according to the first display signal and the first clock signal. The decoded signal includes digital color data. Then, the digital color data is converted into an analog voltage signal by a digital analog conversion (DAC), thereby driving the panel to display the image corresponding to the color data. In practice, the selectivity of the frequency band or the size of the frequency band can be increased according to the capabilities and performance considerations of the locking module 10. For example, when the lock module 10 can support a wide frequency range, it can be divided into more frequency bands. Conversely, when the frequency range that the locking module 10 can support is narrow, it can be divided into fewer frequency bands. For example, when the performance of the locking module 10 is to be improved, the frequency band can be adjusted to increase the stability during locking. Therefore, the locking module 10 and the control The module can extract the synchronized first clock signal from the first display signal of different frequency bands. The decoding module 14 decodes the first display signal according to the first clock signal to generate a decoded signal.

Please refer to FIG. 1 and FIG. 2 together, wherein FIG. 2 is a schematic diagram of frequency band setting according to an embodiment of the present invention. For example, at the beginning of the locking procedure, the locking module 10 is locked in the first frequency band by changing the control voltage. Therefore, the locking procedure is performed on the lock program trace 20. Once the first clock signal synchronized with the first display signal is locked, the control voltage maintains the voltage value at the time of the lock to continuously generate the first clock signal. However, before the first clock signal synchronized with the first display signal has been locked, the control module 12 continuously monitors the change of the control voltage. When the control voltage is greater than the reference voltage V _ref , the control module 12 generates a frequency band setting signal to control the locking module 10 to switch to the second frequency band to continue the locking process. That is, the locking procedure is performed on the lock program trace line 22.

For example, the frequency band can be divided into three frequency bands: 0.1 Gbps to 3.6 Gbps, 3 Gbps to 6.4 Gbps, and 6 Gbps to 10 Gbps. It is assumed that the first display signal received by the source driving device 1 is a signal of about 7.3 Gbps, and the reference voltage V _ref is about 2.35 volts. First, the locking module 10 performs a locking procedure in a frequency band of 0.1 Gbps to 3.6 Gbps. The control voltage begins to increase with an initial value of about 0.5 volts, since the first display signal is not in the frequency band of 0.1 Gbps to 3.6 Gbps. When the control voltage is greater than about 2.35 volts, the control module 12 generates a frequency band setting signal to control the locking module 10 to switch to a frequency band of 3 Gbps to 6.4 Gbps to continue the locking process. Similarly, the control voltage starts to increase with an initial value of about 0.5 volts. When the control voltage is again greater than about 2.35 volts, the control module 12 generates a frequency band setting signal to control the switching module 10 to switch to a frequency band of 6 Gbps to 10 Gbps. Perform a lockout procedure. Finally, the locking module 10 locks the first clock signal synchronized with the first display signal in a frequency band of 6 Gbps to 10 Gbps.

In another embodiment, when the locking module 10 performs the locking process in the first frequency band, the control module 12 compares the control voltage with the reference voltage V _ref and calculates the number of times the control voltage is greater than the reference voltage V _ref . When the number of times is greater than the threshold value, the control module 12 generates a frequency band setting signal to control the locking module 10 to switch to the second frequency band for the locking procedure. For example, the threshold can be set to 31, 63, 127 or 255, but not limited to this. In practice, when the threshold value is set larger, the locking program stability and success rate will be higher, but the locking time may be longer due to the number of retries in the non-target frequency band. Conversely, the smaller the threshold value is set, the lower the lock program stability and success rate, but the lock time may be shorter due to fewer retries in the non-target band. Therefore, comprehensive consideration can be made according to the stability of the locking program, the success rate and the completion of the locking time to determine the appropriate threshold value. So, to avoid lockout procedures when control voltage is near the reference voltage V _ref, the control voltage temporarily exceeds V _ref, but the program is still possible to lock the convergence of misjudgment situation. Thereby, to improve the stability and success rate of the locking program.

Please refer to FIG. 3, which is a structural diagram of a locking module according to an embodiment of the present invention. As shown in FIG. 3, the locking module 30 includes a phase detecting unit 300, a voltage generating unit 302, and an oscillating unit 304. The phase detecting unit 300 is configured to compare the phase of the first display signal with the phase of the second clock signal from the oscillating unit 304 to generate a comparison result. Furthermore, the voltage generating unit 302 generates a control voltage according to the comparison result. In addition, the oscillating unit 304 generates a second clock signal according to the frequency band setting signal and the control voltage. When the comparison result generated by the phase detecting unit 300 indicates that the phase of the first display signal is the same as the phase of the second clock signal, the oscillating unit outputs the second clock signal as the first clock signal, that is, the locking program succeeds. The first clock signal is taken out from the first display signal. Therefore, the output first clock signal can be provided to the decoding module 14 in FIG. 1 as a clock reference for decoding. After successfully acquiring the first clock signal from the first display signal, the phase detecting unit 300 continues to compare the phase of the first display signal with the phase of the second clock signal (ie, the first clock signal) to Ensure the stability of the clock signal. Moreover, when the comparison result generated by the phase detecting unit 300 indicates that the phase of the first display signal is different from the phase of the second clock signal, the oscillating unit 304 still outputs the second clock signal as the first clock signal. However, the output of the first clock signal is not the correct clock signal. Therefore, the output first clock signal can be provided to the decoding module 14 in FIG. 1 as the clock reference of the decoding, but the correct decoding signal cannot be generated. In practice, the above locking mechanism can be repeated again when the correct clock signal cannot be successfully extracted in all frequency bands.

Please refer to FIG. 4, which is a structure of a source driving device according to another embodiment of the present invention. Figure. As shown in FIG. 4 , the source driving device 4 includes a locking module 40 , a control module 42 , and a decoding module 44 . The coupling relationship and operation principle of the foregoing modules are the same as those in the embodiment shown in FIG. 1 . This will not be repeated here. Different from FIG. 1 , the source driving device 4 further includes a switching module 46 , a first impedance matching module 47 , and a second impedance matching module 48 . The switching module 46 receives the second display signal from the timing control device. The first impedance matching module 47 is coupled to the switching module 46 for providing a first impedance value that matches the output impedance of the timing control device in the first frequency band. Furthermore, the second impedance matching module 48 is coupled to the switching module 46 for providing a second impedance value that matches the output impedance of the timing control device in the second frequency band. When the locking module 40 locks the first clock signal synchronized with the first display signal in the first frequency band, the switching module 46 transmits the second display signal to the first impedance matching module 47 to output the first display signal. When the locking module 40 locks the first clock signal synchronized with the first display signal in the second frequency band, the switching module 46 transmits the second display signal to the second impedance matching module 48 to output the first display signal.

In addition, the source driving device 4 further includes a selection module 49. One input end is coupled to the first impedance matching module 47, the other input end is coupled to the second impedance matching module 48, and the output end is coupled to the output end. The module 40 and the decoding module 44 are locked. When the locking module 40 locks the first clock signal synchronized with the first display signal in the first frequency band, the selection module 49 transmits the first display signal from the first impedance matching module 47 to the locking module 40 and decodes Module 44. When the locking module 40 locks the first clock signal synchronized with the first display signal in the second frequency band, the selection module 49 transmits the first display signal from the second impedance matching module 48 to the locking module 40 and decodes Module 44. In practice, the switching module 46 and the selection module 49 are further coupled to the locking module 40 to receive the control signal from the locking module 40 to determine the path of switching or selection. Further, when the locking module 40 has not locked the first clock signal synchronized with the first display signal in any frequency band, the control signal of the locking module 40 can indicate the switching module 46 and the selection module 49. The first switching signal is transmitted to the locking module 40 and the decoding module 44 via the first impedance matching module 47. When the to-be-locked module 40 successfully locks the first clock signal synchronized with the first display signal in one of the frequency bands, the control signal of the locking module 40 instructs the switching module 46 and the selection module 49 to switch to the corresponding path. . By right The display signal in the same frequency band performs matching between the input impedance of the source driving device 4 and the output impedance of the timing control device, thereby improving the accuracy of the impedance matching to achieve the best signal transmission effect.

Please refer to FIG. 4 and FIG. 5 together. FIG. 5 is a structural diagram of a first impedance matching module according to an embodiment of the present invention. As shown in FIG. 5, the first impedance matching module 57 includes an impedance matching unit 570, a first filtering unit 572, a second filtering unit 574, and a multiplexing unit 576. The impedance matching unit 570 is coupled to the first filtering unit 572 and the second filtering unit 574 for providing a first impedance value that matches the output impedance of the timing control device in the first frequency band. In order to further improve the effect of impedance matching, the first frequency band can be divided into a first sub-band and a second sub-band. The first filtering unit 572 is a band pass filter corresponding to the first sub-band, and is configured to filter out signals other than the first sub-band to optimize the second display signal for the first sub-band. The second filtering unit 574 is a band pass filter corresponding to the second sub-band for filtering signals other than the second sub-band to optimize the second display signal for the second sub-band.

The multiplexer 576 is coupled to the first filtering unit 572, and the other input is coupled to the second filtering unit 574 for receiving the first display signal from the first filtering unit 572 and the second filtering unit 574. . In addition, the multiplex unit 576 is further coupled to the locking module 40. When the locking module 40 locks the first clock signal synchronized with the first display signal in the first sub-band, the locking module 40 indicates the multiplex by the control signal. Unit 576 outputs a first display signal from first filtering unit 572. When the locking module 40 locks the first clock signal synchronized with the first display signal in the second sub-band, the locking module 40 outputs the first display signal from the second filtering unit 574 by the control signal indicating multiplexing unit 576. In practice, the system cost and impedance matching effect can be considered at the same time, and the sub-band segmentation and the configuration of the filtering unit are adjusted. For example, the number of sub-bands and their corresponding filtering units can be increased, and the control signals can be adjusted to improve the precision of impedance matching and improve the impedance matching effect. In another embodiment, the second impedance matching module 48 shown in FIG. 4 also has the structure of the first impedance matching module 57 as described above, and details are not described herein again.

Referring to FIG. 1 and FIG. 6 together, a display signal receiving method according to an embodiment of the present invention is described. FIG. 6 is a flowchart of the embodiment. Display signal receiver of this embodiment The method is used in the source driving device 1. In step S60, the locking module 10 selectively performs a locking procedure in the first frequency band or the second frequency band according to the frequency band setting signal, and the locking program is used to lock the synchronization with the first display signal. The first clock signal. In step S62, the control module 12 compares the control voltage and the reference voltage in the locking program to generate a frequency band setting signal. In step S64, the decoding module 14 generates a decoding signal according to the first display signal and the first clock signal. The display signal receiving method of the other embodiments of the present invention has the steps and operation principles as described in the embodiments related to the source driving device, and details are not described herein again.

Please refer to FIG. 7, which is a block diagram of a timing control apparatus according to an embodiment of the present invention. As shown in FIG. 7, the timing control device 7 includes a locking module 70, a control module 72, and an encoding module 74. The locking module 70 selectively performs a locking procedure in the first frequency band or the second frequency band according to the frequency band setting signal, so that the locking module 70 locks the third clock signal synchronized with the third display signal. Moreover, the control module 72 is coupled to the locking module 70 for comparing the control voltage and the reference voltage in the locking program to generate a frequency band setting signal. In addition, the encoding module 74 is coupled to the locking module 70 to generate an encoded signal according to the third display signal and the third clock signal. In practice, the selectivity of the frequency band or the size of the frequency band can be increased according to the capabilities and performance considerations of the locking module 70. For example, when the lock module 70 can support a wide frequency range, it can be divided into more frequency bands. Conversely, when the frequency range that the locking module 70 can support is narrow, it can be divided into fewer frequency bands. For example, when the performance of the locking module 70 is to be improved, the frequency band can be adjusted to increase the stability during locking. Therefore, as in the foregoing embodiment of the source driving device, the frequency band can be divided into three frequency bands of 0.1 Gbps to 3.6 Gbps, 3 Gbps to 6.4 GHz, and 6 Gbps to 10 Gbps to perform a locking procedure. Thereby, the locking module 70 and the control module can extract the synchronized third clock signal from the third display signal of different frequency bands. The encoding module 74 encodes the third display signal according to the third clock signal to generate an encoded signal and transmits the encoded signal to the source driving device. For the operation principle of the frequency band setting and locking module, please refer to the embodiments described in FIG. 2 and FIG. 3, and details are not described herein again.

In the foregoing embodiment, in practice, the timing control device is coupled to the source driving device. The timing control device encodes the received display signal to transmit the display signal to the source driving device via the transmission channel. Among them, the encoded display signal includes digital color material. The source driving device decodes the received display signal, and converts the digital color data into an analog voltage signal through digital analog conversion, thereby driving the panel to display the image corresponding to the color data. For example, the source driving device can be used as the source driving device 1 disclosed in FIG. 1 to automatically detect the frequency band of the input encoded signal to lock the synchronized clock signal for decoding. In another example, the timing control device can automatically detect the frequency of the input display signal as the timing control device 7 disclosed in FIG. 7 to lock the synchronized clock signal for encoding. Furthermore, the source driving device 1 disclosed in FIG. 1 and the timing control device 7 disclosed in FIG. 7 can be used together to optimize the transmission performance of the display signal.

Please refer to FIG. 8 , which is a structural diagram of a timing control apparatus according to another embodiment of the present invention. As shown in FIG. 8 , the timing control device 8 includes a locking module 80 , a control module 82 , and an encoding module 84 . The coupling relationship and the operation principle are the same as those in the embodiment shown in FIG. 7 , and details are not described herein again. Different from FIG. 7 , the timing control device 8 further includes a switching module 86 , a third impedance matching module 87 , and a fourth impedance matching module 88 . The switching module 86 receives the encoded signal from the encoding module 84. The third impedance matching module 87 is coupled to the switching module 86 for providing a third impedance value that matches the input impedance of the first frequency band and the source driving device. Furthermore, the fourth impedance matching module 88 is coupled to the switching module 86 for providing a fourth impedance value that matches the input impedance of the second frequency band with the source driving device. When the locking module 80 locks the third clock signal synchronized with the third display signal in the first frequency band, the switching module 86 transmits the encoded signal to the third impedance matching module 87 to output the fourth display signal to the source driving. Device. When the locking module 80 locks the third clock signal synchronized with the third display signal in the second frequency band, the switching module 86 transmits the encoded signal to the fourth impedance matching module 88 to output the fourth display signal to the source driving. Device.

In addition, the timing control device 8 further includes a selection module 89. One input end is coupled to the third impedance matching module 87, the other input end is coupled to the fourth impedance matching module 88, and the output end is coupled to the source. Extreme drive unit. When the locking module 80 locks the third clock signal synchronized with the third display signal in the first frequency band, the selection module 89 outputs the fourth display signal from the third impedance matching module 87 to the source driving device. When the locking module 80 locks the third frequency band and synchronizes with the third display signal in the second frequency band During the clock signal, the selection module 89 outputs the fourth display signal from the fourth impedance matching module 88 to the source driving device. In practice, the switching module 86 and the selection module 89 are further coupled to the locking module 80 to receive the control signal from the locking module 80 to determine the path of the switching or selection. Further, when the locking module 80 has not locked the third clock signal synchronized with the third display signal in any one frequency band, the control signal of the locking module 80 can instruct the switching module 86 and the selection module 89 to The preset switching path, for example, via the third impedance matching module 87, transmits the third display signal to the source driving device. When the module to be locked 80 successfully locks the third clock signal synchronized with the third display signal in one of the frequency bands, the control signal of the locking module 80 instructs the switching module 86 and the selection module 89 to switch to the corresponding path. . By matching the display signals of different frequency bands, the output impedance of the timing control device 8 and the input impedance of the source driving device can improve the accuracy of the impedance matching to achieve the best signal transmission effect.

Please refer to FIG. 8 and FIG. 9 together. FIG. 9 is a structural diagram of a third impedance matching module according to an embodiment of the present invention. As shown in FIG. 9, the third impedance matching module 97 includes a shunt unit 976, a first filtering unit 972, a second filtering unit 974, and an impedance matching unit 970. In order to further improve the effect of impedance matching, the first frequency band can be divided into a first sub-band and a second sub-band. The shunt unit 976 receives the encoded signal and is coupled to the locking module 80. When the locking module 80 locks the third clock signal synchronized with the third display signal in the first sub-band, the locking module 80 outputs the encoded signal to the first filtering unit 972 by the control signal indicating multiplexing unit 976. When the locking module 80 locks the third clock signal synchronized with the third display signal in the second sub-band, the locking module 80 outputs the encoded signal to the second filtering unit 974 by the control signal indicating multiplexing unit 976. The first filtering unit 972 is a band pass filter corresponding to the first sub-band, and is configured to filter out signals other than the first sub-band to optimize the encoded signal for the first sub-band. The second filtering unit 974 is a band pass filter corresponding to the second sub-band for filtering signals other than the second sub-band to optimize the encoded signal for the second sub-band. The impedance matching unit 970 is coupled to the first filtering unit 972 and the second filtering unit 974 for providing a third impedance value that matches the input impedance of the first frequency band and the source driving device to generate a fourth display signal. In practice, the system cost and impedance matching effect can be considered at the same time, and the sub-band segmentation and filtering unit Configuration to make adjustments. For example, the number of sub-bands and their corresponding filtering units can be increased, and the control signals can be adjusted to improve the precision of impedance matching and improve the impedance matching effect. In another embodiment, the fourth impedance matching module 88 shown in FIG. 8 also has the structure of the third impedance matching module 97 as described above, and details are not described herein again.

Referring to FIG. 7 and FIG. 10 together, a display signal transmitting method according to an embodiment of the present invention is described. FIG. 10 is a flowchart of the embodiment. The display signal transmitting method of this embodiment is used for the timing control device 7. In step S100, the locking module 70 selectively performs a locking procedure according to the frequency band setting signal in the first frequency band or the second frequency band, and the locking program is used to lock and The third display signal is synchronized with the third clock signal. In step S102, the control module 72 compares the control voltage and the reference voltage in the locking program to generate a frequency band setting signal. In step S104, the encoding module 74 generates an encoded signal according to the third display signal and the third clock signal. The display signal transmitting method of the other embodiments of the present invention has the steps and the operating principles as described in the embodiments related to the timing control device, and details are not described herein again.

In summary, the detection of the frequency band of the display signal automatically in the source driving device and the timing control device not only improves the efficiency of the clock acquisition, but also expands the support for display signals of various resolutions and data rates. range. In addition, by optimizing the impedance matching of the display signals of different frequency bands, the optimal signal transmission effect can be achieved and the display quality can be effectively improved.

Although the embodiments of the present invention are disclosed above, it is not intended to limit the present invention, and those skilled in the art, regardless of the spirit and scope of the present invention, the shapes, configurations, and features described in the scope of the present application. And the number of modifications may be made, and the scope of patent protection of the present invention shall be determined by the scope of the patent application attached to the specification.

1‧‧‧Source drive

10‧‧‧Locking module

12‧‧‧Control Module

14‧‧‧Decoding module

Claims (10)

A source driving device includes: a locking module, configured to selectively perform a locking process in a first frequency band or a second frequency band according to a frequency band setting signal, wherein the locking program is used to lock the locking module with a locking module a first clock signal of the first display signal synchronization; a control module coupled to the lock module for comparing a control voltage and a reference voltage in the lock program to generate the frequency band setting signal; A decoding module is coupled to the locking module to generate a decoding signal according to the first display signal and the first clock signal. The source driving device of claim 1, wherein when the locking module performs the locking procedure in the first frequency band, the control module compares the control voltage with the reference voltage when the control voltage is greater than the reference voltage The control module generates the frequency band setting signal to control the locking module to perform the locking procedure in the second frequency band. The source driving device of claim 1, wherein when the locking module performs the locking procedure in the first frequency band, the control module compares the control voltage with the reference voltage, and calculates that the control voltage is greater than the reference When the number of times is greater than a threshold, the control module generates the frequency band setting signal to control the locking module to perform the locking procedure in the second frequency band. The source driving device of claim 1, wherein the locking module comprises a phase detecting unit, a voltage generating unit and an oscillating unit, wherein the phase detecting unit compares the phase of the first display signal And a phase of the second clock signal to generate a comparison result, the voltage generating unit generates the control voltage according to the comparison result, and the oscillating unit generates the second clock signal according to the frequency band setting signal and the control voltage, when When the phase of the first display signal is the same as the phase of the second clock signal, the oscillating unit outputs the second clock signal as the first clock signal. The source driving device of claim 1, further comprising: a switching module, receiving a second display signal from a timing control device; and a first impedance matching module coupled to the switching module for Providing a first impedance value that matches the output impedance of the timing control device in the first frequency band; and a second impedance matching module coupled to the switching module for providing the second frequency band and the timing The second impedance value of the output impedance of the control device is matched; wherein, when the locking module locks the first clock signal synchronized with the first display signal in the first frequency band, the switching module uses the second The display signal is transmitted to the first impedance matching module to output the first display signal. When the locking module locks the first clock signal synchronized with the first display signal in the second frequency band, the switching module And transmitting the second display signal to the second impedance matching module to output the first display signal. A display signal receiving method is provided for a source driving device, comprising: performing a locking process selectively in a first frequency band or a second frequency band according to a frequency band setting signal, wherein the locking program is used for locking and first Displaying a first clock signal of the signal synchronization; comparing a control voltage and a reference voltage in the locking program to generate the frequency band setting signal; Generating a decoded signal according to the first display signal and the first clock signal. The method for receiving a display signal according to claim 6, wherein the comparing the control voltage and the reference voltage in the locking procedure, the step of generating the frequency band setting signal comprises: when the locking procedure is performed in the first frequency band Comparing the control voltage with the reference voltage; and when the control voltage is greater than the reference voltage, generating the frequency band setting signal to perform the locking procedure in the second frequency band. The method for receiving a display signal according to claim 6, wherein the comparing the control voltage and the reference voltage in the locking procedure, the step of generating the frequency band setting signal comprises: when the locking procedure is performed in the first frequency band Comparing the control voltage with the reference voltage; calculating the control voltage for a number of times greater than the reference voltage; and when the number of times is greater than a threshold, generating the frequency band setting signal to perform the locking procedure in the second frequency band. The method for receiving a display signal according to claim 6, wherein the step of selectively performing the locking procedure in the first frequency band or the second frequency band according to the frequency band setting signal comprises: comparing phases of the first display signal And a phase of a second clock signal in the first frequency band or the second frequency band to generate a comparison result; generating the control voltage according to the comparison result; generating the second clock according to the frequency band setting signal and the control voltage a signal; and when the phase of the first display signal is the same as the phase of the second clock signal, the second The clock signal output is the first clock signal. The method for receiving a display signal according to claim 6, further comprising: receiving a second display signal from a timing control device; providing a first impedance value in the first frequency band that matches an output impedance of the timing control device; a second impedance value that matches the output impedance of the timing control device in the second frequency band; and when the first clock signal synchronized with the first display signal is locked in the first frequency band, according to the second display signal Generating the first display signal associated with the first impedance value; and when the first clock signal synchronized with the first display signal is locked in the second frequency band, generating a correlation with the second display signal according to the second display signal The first display signal of the two impedance values.