TWI545999B - Printed circuit board and fabrication thereof - Google Patents

Description

Printed circuit board and manufacturing method thereof

The present invention relates to a printed circuit board and a method of fabricating the same, and more particularly to a printed circuit board that does not include a core board and a method of fabricating the same.

Printed circuit boards (PCBs) are widely used in various electronic devices, such as mobile phones, personal digital assistants, and thin film transistor liquid crystal displays (TFT-LCDs). The printed circuit board is used to fix various electronic components, and its main function is to provide mutual current connection of each electronic component.

With the evolution of technology, the wiring density of printed circuit boards is getting higher and higher, and the structure and process of printed circuit boards need to be continuously improved to make the density higher and higher, which can solve the problems caused by high wiring density.

In light of the above, there is a need in the industry for a printed circuit board having a higher wiring density and associated fabrication methods.

According to an embodiment of the present invention, a printed circuit board includes: an insulating layer including a first side and a second side opposite to the first side; a first pad layer embedded in the insulating layer, And adjacent to the first side; a second pad layer on the second side of the insulating layer; a conductive hole, located at the In the edge layer, and connecting the first pad layer and the second pad layer; and a plurality of wires, wherein at least one of the wires is located on the first side of the insulating layer.

An embodiment of the present invention provides a method of fabricating a printed circuit board, comprising: providing a core board; forming a first insulating layer on the core board; forming a first conductive layer on the first insulating layer; forming a second An insulating layer is disposed on the first conductive layer and the first insulating layer; separating the second insulating layer from the first insulating layer; and inverting the separated second insulating layer, wherein the inverted second insulating layer includes a first side and a second side opposite to the first side; forming a first pad layer embedded in the second insulating layer according to the first conductive layer, and the first pad layer is adjacent to the first side of the second insulating layer; and the second insulating layer After being separated from the first insulating layer, a plurality of wires are formed, wherein at least one of the wires is on the first side of the second insulating layer.

An embodiment of the invention provides a printed circuit board comprising: an insulating layer comprising a first side and a second side opposite to the first side; a first pad layer and a wire respectively embedded in the insulating layer And adjacent to the first side; a second pad layer on the second side of the insulating layer; a conductive hole in the insulating layer, and connecting the first pad layer and the second pad layer; and a copper bump, located at On the first cushion.

An embodiment of the present invention provides a method of fabricating a printed circuit board, comprising: providing a core board; forming a first insulating layer on the core board; forming a first conductive layer on the first insulating layer; forming a second An insulating layer is disposed on the first conductive layer and the first insulating layer; separating the second insulating layer from the first insulating layer; and inverting the separated second insulating layer, wherein the inverted second insulating layer includes a first side and a second side opposite to the first side; forming a first pad layer and a wire embedded in the second insulating layer according to the first conductive layer, and the first pad layer and the wire are adjacent to the first side of the second insulating layer; form A copper bump is on the first underlayer.

102‧‧‧Insulation

104‧‧‧ second side

106‧‧‧ first side

108‧‧‧Electrical hole

110‧‧‧First cushion

112‧‧‧Wire

302‧‧‧ core board

304‧‧‧First conductive layer

306‧‧‧First insulation

308‧‧‧Second conductive layer

310‧‧‧ Third conductive layer

312‧‧‧Photosensitive layer

314‧‧‧ openings

316‧‧‧4th conductive layer

318‧‧‧Second insulation

320‧‧‧ fifth conductive layer

322‧‧‧ plating initiation layer

324‧‧ ‧ blind holes

326‧‧‧Second photosensitive layer

328‧‧‧ openings

330‧‧‧ sixth conductive layer

333‧‧‧Electrical hole

334‧‧‧ cushion

336‧‧‧third photosensitive layer

337‧‧‧4th photosensitive layer

338‧‧‧ openings

340‧‧‧ seventh conductive layer

342‧‧‧ first side

344‧‧‧ second side

346‧‧‧Wire

350‧‧‧Second cushion

352‧‧‧Printed circuit board

356‧‧‧ Fifth photosensitive layer

358‧‧‧ openings

360‧‧‧8th conductive layer

362‧‧‧Printed circuit board

364‧‧‧Wire

366‧‧‧Protective layer

368‧‧‧ openings

370‧‧‧ plating initiation layer

372‧‧‧ copper bumps

402‧‧‧ core board

404‧‧‧First conductive layer

406‧‧‧First insulation

408‧‧‧Second conductive layer

410‧‧‧3rd conductive

412‧‧‧First photosensitive layer

414‧‧‧4th conductive layer

416‧‧‧Second insulation

418‧‧‧ fifth conductive layer

420‧‧‧ first side

422‧‧‧ second side

424‧‧‧ plating initiation layer

426‧‧ ‧ blind holes

428‧‧‧Second photosensitive layer

430‧‧‧ third photosensitive layer

432‧‧‧ openings

434‧‧‧ openings

436‧‧‧ sixth conductive layer

438‧‧‧Electrical hole

440‧‧‧Second cushion

442‧‧‧ wire

450‧‧‧Printed circuit board

502‧‧‧ core board

504‧‧‧First conductive layer

506‧‧‧First insulation

508‧‧‧Second conductive layer

510‧‧‧ Third conductive layer

512‧‧‧first photosensitive layer

514‧‧‧ openings

516‧‧‧fourth conductive layer

518‧‧‧Second insulation

520‧‧‧ fifth conductive layer

522‧‧‧ first side

524‧‧‧ second side

526‧‧‧ plating initiation layer

528‧‧‧through hole

530‧‧‧Second photosensitive layer

532‧‧‧ Third photosensitive layer

534‧‧‧ openings

536‧‧‧ openings

538‧‧‧6th conductive layer

539‧‧‧Electrical hole

540‧‧‧Wire

542‧‧‧ cushion

544‧‧‧First cushion

550‧‧‧Printed circuit board

602‧‧‧ core board

604‧‧‧First conductive layer

606‧‧‧First insulation

608‧‧‧Second conductive layer

610‧‧‧ Third conductive layer

612‧‧‧First photosensitive layer

614‧‧‧4th conductive layer

616‧‧‧Second insulation

618‧‧‧ fifth conductive layer

620‧‧‧through hole

622‧‧‧ plating initiation layer

624‧‧‧ first side

626‧‧‧ second side

628‧‧‧Second photosensitive layer

630‧‧‧ Third photosensitive layer

632‧‧‧ sixth conductive layer

633‧‧‧Electrical hole

634‧‧‧Wire

636‧‧‧ cushion

638‧‧‧First cushion

650‧‧‧Printed circuit board

702‧‧‧ core board

704‧‧‧First conductive layer

706‧‧‧First insulation

708‧‧‧Second conductive layer

710‧‧‧ Third conductive layer

712‧‧‧First photosensitive layer

714‧‧‧ openings

715‧‧‧ openings

716‧‧‧fourth conductive layer

717‧‧‧Wire

718‧‧‧Second insulation

720‧‧‧ fifth conductive layer

722‧‧‧ plating initiation layer

724‧‧‧Blind hole

726‧‧‧Second photosensitive layer

728‧‧‧ openings

730‧‧‧6th conductive layer

733‧‧‧Electrical hole

734‧‧‧ cushion

736‧‧‧ Third photosensitive layer

737‧‧‧4th photosensitive layer

738‧‧‧ openings

740‧‧‧ copper bumps

742‧‧‧ first side

744‧‧‧ second side

752‧‧‧Printed circuit board

Figure 1 shows a plan view of a printed circuit board.

Figure 2 shows a cross-sectional view of a printed circuit board.

3A to 3K are cross-sectional views showing respective stages of a method of fabricating a printed circuit board according to an embodiment of the present invention.

3J-1, 3K-1, 3L, and 3M are cross-sectional views showing stages of a method of fabricating a printed circuit board according to an embodiment of the present invention.

4A to 4J are cross-sectional views showing respective stages of a method of fabricating a printed circuit board according to an embodiment of the present invention.

5A to 5J are cross-sectional views showing respective stages of a method of fabricating a printed circuit board according to an embodiment of the present invention.

6A to 6J are cross-sectional views showing respective stages of a method of fabricating a printed circuit board according to an embodiment of the present invention.

7A to 7K are cross-sectional views showing respective stages of a method of fabricating a printed circuit board according to an embodiment of the present invention.

Embodiments embodying the invention are discussed in detail below. It will be appreciated that the embodiments provide many applicable inventive concepts that can be implemented in a wide variety of variations. The specific embodiments discussed are merely illustrative of specific ways to use the embodiments and are not intended to limit the scope of the invention. In order to make the features of the present invention more comprehensible, the following detailed description and the accompanying drawings are described in detail as follows: FIG. 1 shows a plan view of a printed circuit board, and FIG. 2 shows a printed circuit board. Sectional view. Please refer to Figure 1 and Figure 2 for an insulation layer. The first pad layer 110 is located on the first side 106 of the insulating layer 102, and the second pad layer 114 is located on the second side 104 of the insulating layer 102. The first pad layer 110 passes through the conductive hole 108. The second pad layer 114 is connected. A wire 112 is located on the first side 106 of the insulating layer 102.

As shown in Figures 1 and 2, the distance d between the first underlayer 110 and the wire 112 is limited by the ability of the process or the material, and is spaced a specific distance. According to this particular distance limitation, the wiring density of printed circuit boards is limited.

According to the above, a printed circuit board and related manufacturing method are provided below, so that the pad layer and the wires are located in different layers. Therefore, the distance between the pad layer and the wires is not limited to the process capability of image transfer to increase the wiring density.

Hereinafter, a method of fabricating a printed circuit board according to an embodiment of the present invention will be described based on FIGS. 3A to 3K. Please refer to FIG. 3A to provide a core board 302. In some embodiments, the core sheet 302 comprises a paper phenolic resin, a composite epoxy, a polyimide resin, or a glass fiber.

Subsequently, a first conductive layer 304 is formed on the core board 302. In some embodiments, the first conductive layer 304 comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations of the foregoing, or alloys thereof. The manner in which the first conductive layer 304 is formed includes a deposition, press bonding, or coating process. Next, a first insulating layer 306 is formed on the first conductive layer 304. The first insulating layer 306 may be an epoxy resin, a bismaleimie triacine (BT), or a poly Polyimide (PI), ajinomoto build-up film, polyphenylene oxide (PPO), polypropylene (PP), polymethyl methacrylate (PMMA) Teflon (polytetrafluorethylene, PTFE). In some embodiments, the first insulating layer 306 may be formed on the first conductive layer 304 by press bonding or coating.

Thereafter, a second conductive layer 308 and a third conductive layer 310 are formed on the first insulating layer 306. In some embodiments, the second conductive layer 308 and the third conductive layer 310 may comprise nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations thereof, or alloys thereof. The second conductive layer 308 and the third conductive layer 310 may comprise the same material or, in another embodiment, comprise a different material. For example, the second conductive layer 308 may be a thick copper layer for carrying the third conductive layer 310, and the third conductive layer 310 may be a thin copper layer. In some embodiments, the second conductive layer 308 may have a thickness of 12 μm to 36 μm, and the third conductive layer 310 may have a thickness of 1 μm to 6 μm. In some embodiments, the second conductive layer 308 and the third conductive layer 310 may be formed on the first insulating layer 306 by press bonding or electroplating.

Referring to FIG. 3B, a first photosensitive layer 312 including a plurality of openings 314 is formed on the third conductive layer 310. The first photosensitive layer 312 can be formed by laminating dry film or coating and subsequent lithography processes.

Referring to FIG. 3C, a fourth conductive layer 316 is formed on a region of the third conductive layer 310 that is not covered by the first photosensitive layer 312 (ie, in the opening 314). In some embodiments, the fourth conductive layer 316 comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations of the foregoing, or alloys thereof. The fourth conductive layer 316 may be grown in the opening 314 of the first photosensitive layer 312 by electroplating. Subsequently, the first photosensitive layer 312 is removed.

Referring to FIG. 3D, a second insulating layer 318 is formed on the third conductive layer 310, the fourth conductive layer 316, and the first insulating layer 306. In some embodiments, the second insulating layer 318 may be an epoxy resin, a bismaleimie triacine (BT), or a polyaluminum. Amine (PI), ajinomoto build-up film, polyphenylene oxide (PPO), polypropylene (PP), polymethyl methacrylate (PMMA) or poly Polytetrafluorethylene (PTFE). The second insulating layer 318 may be formed on the third and fourth conductive layers 310, 316 by press bonding or coating.

Next, a fifth conductive layer 320 is formed on the second insulating layer 318. In some embodiments, the fifth conductive layer 320 comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations thereof, or alloys thereof. Referring to FIG. 3E, a drilling process is performed to form a blind via 324 in the fifth conductive layer 320 and the second insulating layer 318 to expose the fourth conductive layer 316. In some embodiments, the method of forming the blind holes 324 includes a laser drilling process. Thereafter, an electroplated starting layer 322 is formed in the blind vias 324 and on the second insulating layer 318. In some embodiments, the plating initiation layer 322 comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations of the foregoing, or alloys thereof. The plating starting layer 322 can be formed by electroless plating.

Referring to FIG. 3F, a second photosensitive layer 326 including a plurality of openings 328 is formed on the plating initiation layer 322. The second photosensitive layer 326 can be formed by screen printing, dry film coating or coating, and subsequent lithography processes.

Subsequently, the electroplating process is performed by using the electroplating starting layer 322 as a seed layer for electroplating, and a sixth conductive layer 330 is grown in a region (ie, the opening 328) where the electroplating starting layer 322 is not covered by the second photosensitive layer 326. . The sixth conductive layer 330 may be filled into the blind vias to form a conductive via 333, and/or a pad layer 334 may be formed in the opening 328. In some embodiments, the sixth conductive layer 330 comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations of the foregoing, or alloys thereof.

Referring to FIG. 3G, the second photosensitive layer 326 is removed and the plating starting layer 322 and the fifth conductive layer 320 covering the second photosensitive layer 326 are removed. In some embodiments, the step of removing the plating start layer 322 and the fifth conductive layer 320 covering the second photosensitive layer 326 may be performed by chemical etching. Referring to FIG. 3H, a dicing process is performed to cut off portions of the first insulating layer 306 and the second insulating layer 318 so that the second conductive layer 308 can be separated from the third conductive layer 310 in a subsequent step.

Referring to FIG. 3I, the second conductive layer 308 is separated from the third conductive layer 310 such that the core plate 302 is separated from the second insulating layer 318. And a step of turning over the separated second insulating layer 318 and the conductive layers thereon so that the bottom of the original is facing upward and the top is facing downward, as shown in FIG. 3J.

Referring to FIG. 3J, after inversion, the second insulating layer 318 includes a first side 342 and a second side 344 opposite the first side 342. A third photosensitive layer 336 including a plurality of openings 338 is formed on the first side 342 of the second insulating layer 318. A fourth photosensitive layer 337 is formed on the second side 344 of the second insulating layer 318. In some embodiments, the fourth photosensitive layer 337 completely covers the second side 344 of the second insulating layer 318 and the sixth conductive layer 330 thereon. The third photosensitive layer 336 and the fourth photosensitive layer 337 may be formed by laminating a dry film, or coating and subsequent lithography processes. Subsequently, a seventh conductive layer 340 is grown in the opening 338 of the third photosensitive layer 336. In some embodiments, the seventh conductive layer 340 comprises a combination of nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, or the like, and the seventh conductive layer 340 can be fabricated by electroplating. Thereafter, referring to FIG. 3K, the third photosensitive layer 336 and the fourth photosensitive layer 337 are removed, and an etching process is performed to remove the third conductive layer 310 not covered by the seventh conductive layer 340 to form a pattern as shown in FIG. 3K. Printed circuit board 352 is shown. In some embodiments, the printed circuit board 352 does not include a core board.

In FIG. 3K, an insulating layer 318 includes a first side 342 and a second side 344 opposite the first side 342. A plurality of first pad layers 316 are embedded in the insulating layer 318 adjacent to the first side 342 of the insulating layer 318. A plurality of second pad layers 350 are on the second side 344 of the insulating layer 318. A conductive via 333 is located in the insulating layer 318 and connects the first pad layer 316 and the second pad layer 350. In some embodiments, the conductive via 333 includes a sloped sidewall, and more particularly, the portion of the conductive via 333 adjacent the second pad layer 350 has a larger dimension than the portion adjacent the first pad layer 316.

A plurality of wires 346, some of which are located on the first pad layer 316, and some of the wires 346 are located on the first side 342 of the insulating layer 318. In some embodiments, the wire 346 is in a different layer than the first pad layer 316. Therefore, the distance between the wire 346 and the first pad layer 316 is not limited by the process capability of image transfer, such as the wire 346 on the insulating layer 318. The minimum distance from the adjacent first pad layer 316 may be 10 μm or less.

Hereinafter, a method of fabricating a printed circuit board according to another embodiment of the present invention will be described based on the 3J-1, 3K-1, 3L, and 3M, wherein the components of the third to third embodiments are used. The same reference numerals are used and the description thereof is omitted. Referring to FIG. 3J-1, a structure similar to that of FIG. 3H is provided, and the second conductive layer 308 is separated from the third conductive layer 310 such that the core plate 302 is separated from the second insulating layer 318, as shown in FIG. . Thereafter, a step of inverting the separated second insulating layer 318 and each of the conductive layers thereon is performed such that the bottom portion faces upward and the top portion faces downward. After the flipping, a step similar to that of FIG. 3J is performed, except that a fifth photosensitive layer 356 including an opening 358 is formed on the first side 342 of the second insulating layer 318, and the opening 358 is located outside the first pad layer 316. The first insulating layer 318 is on the first side 342. Forming a fourth photosensitive layer 337 on the second side 344 of the second insulating layer 318 to completely cover the second The second side 344 of the edge layer 318 and the sixth conductive layer 330 and the second pad layer 350 thereon. Subsequently, an eighth conductive layer 360 is grown in the opening 358 of the fifth photosensitive layer 356. In some embodiments, the eighth conductive layer 360 comprises a combination of nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, or the like, and the eighth conductive layer 360 can be fabricated by electroplating. Thereafter, referring to FIG. 3K-1, the fifth photosensitive layer 356 is removed, and an etching process is performed to remove the third conductive layer 310 not covered by the eighth conductive layer 360, and formed as shown in FIG. 3K-1. A printed circuit board 362 is shown with a conductor 364 on the first side 342 of the second insulating layer 318. In some embodiments, the printed circuit board 362 does not include a core board.

Referring to FIG. 3L, a protective layer 366 including an opening 368 is formed on the first side 342 of the second insulating layer 318 and the wire 364, wherein the opening 368 corresponds to the exposed first pad layer 316.

Referring to FIG. 3M, a plating initiation layer 370 is formed in the opening 368. The plating initiation layer 370 includes a combination of nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, or the like. The plating starting layer 370 can be formed by electroless plating. The plating starting layer 370 is used as a seeding layer for electroplating, and an electroplating process is performed to grow at least one copper bump 372 in the region of the plating starting layer 370 (that is, in the opening 368). Thereafter, the fourth photosensitive layer 337 on the second side 344 of the second insulating layer 318 is removed.

Hereinafter, a method of fabricating a printed circuit board according to another embodiment of the present invention will be described based on FIGS. 4A to 4J. Referring to FIG. 4A, a core board 402 is provided. In some embodiments, the core sheet 402 comprises a paper phenolic resin, a composite epoxy, a polyimide resin, or a glass fiber.

Subsequently, a first conductive layer 404 is formed on the core board 402. In some embodiments, the first conductive layer 404 comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations of the foregoing, or alloys thereof. The manner in which the first conductive layer 404 is formed includes a deposition, press or coating process. Next, a first insulating layer 406 is formed on the first conductive layer 404. The first insulating layer 406 may be an epoxy resin, a bismaleimie triacine (BT), or a poly Polyimide (PI), ajinomoto build-up film, polyphenylene oxide (PPO), polypropylene (PP), polymethyl methacrylate (PMMA) Or polytetrafluorethylene (PTFE). In some embodiments, the first insulating layer 406 may be formed on the first conductive layer 404 by press bonding or coating.

Thereafter, a second conductive layer 408 and a third conductive layer 410 are formed on the first insulating layer 406. In some embodiments, the second conductive layer 408 and the third conductive layer 410 may comprise nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations of the foregoing, or alloys thereof. The second conductive layer 408 and the third conductive layer 410 may comprise the same material or, in another embodiment, comprise a different material. For example, the second conductive layer 408 may be a thick copper layer for carrying the third conductive layer 410, and the third conductive layer 410 may be a thin copper layer. In some embodiments, the second conductive layer 408 may have a thickness of 12 μm to 36 μm, and the third conductive layer 410 may have a thickness of 1 μm to 6 μm. In some embodiments, the second conductive layer 408 and the third conductive layer 410 may be formed on the first insulating layer 406 by press bonding or electroplating.

Referring to FIG. 4B, a first photosensitive layer 412 including a plurality of openings is formed on the third conductive layer 410. The first photosensitive layer 412 can be formed by laminating a dry film, or by coating and subsequent lithography.

Please refer to FIG. 4C, which is not the first on the third conductive layer 410. The region covered by the photosensitive layer 412 (that is, in the opening) forms a fourth conductive layer 414. In some embodiments, the fourth conductive layer 414 comprises a combination of nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, or alloys thereof. The fourth conductive layer 414 can be grown in the opening of the first photosensitive layer 412 by electroplating. Subsequently, the first photosensitive layer 412 is removed.

Referring to FIG. 4D, a second insulating layer 416 is formed on the third conductive layer 410, the fourth conductive layer 414, and the first insulating layer 406. In some embodiments, the second insulating layer 416 may be an epoxy resin, a bismaleimie triacine (BT), a polyimide (PI), or an increase. Ajinomoto build-up film, polyphenylene oxide (PPO), polypropylene (PP), polymethyl methacrylate (PMMA) or polytetrafluorethylene (PTFE) . The second insulating layer 416 may be formed on the third and fourth conductive layers 410, 414 by press bonding or coating.

Next, a fifth conductive layer 418 is formed on the second insulating layer 416. In some embodiments, the fifth conductive layer 418 comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations thereof, or alloys thereof.

Referring to FIG. 4E, a dicing process is performed to cut off portions of the first insulating layer 406 and the second insulating layer 416, so that the second conductive layer 408 can be separated from the third conductive layer 410 in a subsequent step.

Referring to FIG. 4F, the second conductive layer 408 is separated from the third conductive layer 410 such that the core plate 402 is separated from the second insulating layer 416. The step of turning over the separated second insulating layer 416 and the conductive layers thereon is such that the bottom portion faces upward and the top portion faces downward, as shown in FIG. 4G.

Please refer to FIG. 4G. After the flipping, the second insulating layer 416 is wrapped. A first side 420 and a second side 422 opposite the first side 420 are included. A drilling process is performed from the second side 422 of the second insulating layer 416 to form a blind via 426 in the fifth conductive layer 418 and the second insulating layer 416 to expose the fourth conductive layer 414. In some embodiments, the method of forming blind holes 426 includes a laser drilling process. Thereafter, a plating initiation layer 424 is formed in the blind vias 426 and on the fifth conductive layer 418. In some embodiments, the plating initiation layer 424 comprises a combination of nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, or alloys thereof. The plating initiation layer 424 can be formed by electroless plating.

Referring to FIG. 4H, a second photosensitive layer 428 including a plurality of openings 432 is formed over the third conductive layer 410. A third photosensitive layer 430 including a plurality of openings 434 is formed under the plating initiation layer 424. The second photosensitive layer 428 and the third photosensitive layer 430 may be formed by laminating dry film, or coating and subsequent lithography processes. Subsequently, referring to FIG. 4I, an electroplating process is performed to form a sixth conductive layer 436 in the opening 432 of the second photosensitive layer 428 and the opening 434 of the third photosensitive layer 430. The sixth conductive layer 436 can be filled into the blind vias 426 to form a conductive via 438, and/or a pad layer 440 can be formed in the opening 434. In some embodiments, the sixth conductive layer 436 comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations of the foregoing, or alloys thereof. Thereafter, referring to FIG. 4J, the second photosensitive layer 428 and the third photosensitive layer 430 are removed, and an etching process is performed to remove the third conductive layer 410 and the plating initiation layer 424 that are not covered by the sixth conductive layer 436. And a fifth conductive layer 418, forming a printed circuit board 450 as shown in FIG. 4J. In some embodiments, the printed circuit board does not include a core board.

In FIG. 4J, the insulating layer 416 includes a first side 420 and a second side 422. A plurality of first pad layers 414 are embedded in the insulating layer 416 adjacent to the first side 420 of the insulating layer 416. A plurality of second pad layers 440 are located at the first of the insulating layer 416 On the two sides 422. A plurality of conductive vias 438 are located in the insulating layer 416 and connect the first pad layer 414 and the second pad layer 440. In some embodiments, the conductive vias 438 include sloped sidewalls, and more particularly, portions of the conductive vias 438 adjacent the second underlayer 440 have a larger diameter than portions adjacent the first underlayer 414.

A plurality of wires 442 are located on the first side 420 of the first pad layer 414 and the insulating layer 416. In some embodiments, the wire 442 is in a different layer than the first pad layer 414. Therefore, the distance between the wire 442 and the first pad layer 414 is not limited to the process capability of image transfer, such as the wire 442 on the insulating layer 416. The minimum distance from the adjacent first pad layer 414 may be 10 μm or less.

Hereinafter, a method of fabricating a printed circuit board according to another embodiment of the present invention will be described based on FIGS. 5A to 5J. Referring to FIG. 5A, a core board 502 is provided. In some embodiments, the core sheet 502 comprises a paper phenolic resin, a composite epoxy, a polyimide resin, or a glass fiber.

Subsequently, a first conductive layer 504 is formed on the core board 502. In some embodiments, the first conductive layer 504 comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations of the foregoing, or alloys thereof. The manner in which the first conductive layer 504 is formed includes a deposition, press or coating process. Next, a first insulating layer 506 is formed on the first conductive layer 504. The first insulating layer 506 may be an epoxy resin, a bismaleimie triacine (BT), or a poly Polyimide (PI), ajinomoto build-up film, polyphenylene oxide (PPO), polypropylene (PP), polymethyl methacrylate (PMMA) Or polytetrafluorethylene (PTFE). In some embodiments, the first insulating layer 506 can be formed on the first conductive layer 504 by press bonding or coating.

Thereafter, a second conductive layer 508 and a third conductive layer 510 are formed on the first insulating layer 506. In some embodiments, the second conductive layer 508 and the third conductive layer 510 may comprise nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations of the foregoing, or alloys thereof. The second conductive layer 508 and the third conductive layer 510 may comprise the same material or, in another embodiment, comprise a different material. For example, the second conductive layer 508 may be a thick copper layer for carrying the third conductive layer 510, and the third conductive layer 510 may be a thin copper layer. In some embodiments, the second conductive layer 508 may have a thickness of 12 μm to 36 μm, and the third conductive layer 510 may have a thickness of 1 μm to 6 μm. In some embodiments, the second conductive layer 508 and the third conductive layer 510 may be formed on the first insulating layer 506 by press bonding or electroplating.

Referring to FIG. 5B, a first photosensitive layer 512 including a plurality of openings 514 is formed on the third conductive layer 510. The first photosensitive layer 512 can be formed by laminating a dry film, or by coating and subsequent lithography.

Referring to FIG. 5C, a fourth conductive layer 516 is formed on a region of the third conductive layer 510 that is not covered by the first photosensitive layer 512 (ie, in the opening 514). In some embodiments, the fourth conductive layer 516 comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations thereof, or alloys thereof. The fourth conductive layer 516 can be grown in the opening 514 of the first photosensitive layer 512 by electroplating. Subsequently, the first photosensitive layer 512 is removed.

Referring to FIG. 5D, a second insulating layer 518 is formed on the third conductive layer 510, the fourth conductive layer 516, and the first insulating layer 506. In some embodiments, the second insulating layer 518 may be an epoxy resin, a bismaleimie triacine (BT), a polyimide (PI), or an increase. Ajinomoto build-up film, polyphenylene oxide (PPO), polypropylene (polypropylene, PP), polymethyl methacrylate (PMMA) or polytetrafluoroethylene (PTFE). The second insulating layer 518 can be formed by pressing or coating.

Next, a fifth conductive layer 520 is formed on the second insulating layer 518. In some embodiments, the fifth conductive layer 520 comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations thereof, or alloys thereof.

Referring to FIG. 5E, a dicing process is performed to cut off portions of the first insulating layer 506 and the second insulating layer 518 so that the second conductive layer 508 can be separated from the third conductive layer 510 in a subsequent step.

Referring to FIG. 5F, the second conductive layer 508 is separated from the third conductive layer 510 such that the core plate 502 is separated from the second insulating layer 518. The step of turning over the separated second insulating layer 518 and the conductive layers thereon is such that the bottom is facing upward and the top is facing downward, as shown in FIG. 5G.

Referring to FIG. 5G, after inversion, the second insulating layer 518 includes a first side 522 and a second side 524 opposite the first side 522. A second drilling process is performed on the second insulating layer 518 to form a via 528 extending through the second insulating layer 518. In some embodiments, the method of forming vias 528 includes a mechanical drilling process. Thereafter, a plating initiation layer 526 is formed in the via 528, the third conductive layer 510, and the fifth conductive layer 520. In some embodiments, the plating initiation layer 526 comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations of the foregoing, or alloys thereof. The plating initiation layer 526 can be formed by electroless plating.

Referring to FIG. 5H, a second photosensitive layer 530 including a plurality of openings 534 is formed over the plating initiation layer 526 of the first side 522 of the second insulating layer 518. A third photosensitive layer 532 including a plurality of openings 536 is formed under the plating initiation layer 526 of the second side 524 of the second insulating layer 518. The second photosensitive layer 530 and the third photosensitive layer 532 may be formed by laminating a dry film. Or coating and subsequent lithography processes. In some embodiments, the size of the opening 534 of the second photosensitive layer 530 is smaller than the size of the opening 536 of the third photosensitive layer 532.

Subsequently, an electroplating process is performed to form a sixth conductive layer 538 in the opening 534 of the second photosensitive layer 530, the opening 536 of the third photosensitive layer 532, and the via 528. The sixth conductive layer 538 is filled in the through hole 528 to form a conductive hole 539. The wire 540 is formed in the opening 534 of the second photosensitive layer 530, and the pad layer 542 is formed in the opening 536 of the third photosensitive layer 532. In some embodiments, the sixth conductive layer 538 comprises a combination of nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, or alloys thereof. Thereafter, referring to FIG. 5J, the second photosensitive layer 530 and the third photosensitive layer 532 are removed, and an etching process is performed to remove the third conductive layer 510 and the fifth conductive layer 520 which are not covered by the sixth conductive layer 538. And the plating start layer 526, forming a printed circuit board 550 as shown in Fig. 5J. In some embodiments, this printed circuit board 550 does not include a core board.

It should be noted that in the present embodiment, after the above etching step, the fourth conductive layer 516 and the portion of the conductive holes 539 together constitute the first pad layer 544.

In FIG. 5J, insulating layer 518 includes a first side 522 and a second side 524. A plurality of first pad layers 544 are embedded in the insulating layer 518 adjacent to the first side 522 of the insulating layer 518. A plurality of second pad layers 542 are located on the second side 524 of the insulating layer 518. A plurality of conductive vias 539 are located in the insulating layer 518 and connect the first pad layer 544 and the second pad layer 542. In some embodiments, the conductive vias 539 include vertical sidewalls, that is, portions of the conductive vias 539 adjacent the second underlayer 542 have substantially the same dimensions as portions adjacent the first underlayer 544.

A plurality of wires 540 are located in the first pad layer 544 and the insulating layer 518 On the first side 522. In some embodiments, the wire 540 is in a different layer than the first pad layer 544. Therefore, the distance between the wire 540 and the first pad layer 544 is not limited to the process capability of image transfer, such as the wire 540 on the insulating layer 518. The minimum distance from the adjacent first pad layer 544 may be 10 μm or less.

Hereinafter, a method of fabricating a printed circuit board according to another embodiment of the present invention will be described based on FIGS. 6A to 6J. Please refer to FIG. 6A to provide a core board 602. In some embodiments, the core sheet comprises a paper phenolic resin, a composite epoxy, a polyimide resin, or a glass fiber.

Subsequently, a first conductive layer 604 is formed on the core board 602. In some embodiments, the first conductive layer 604 comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations of the foregoing, or alloys thereof. The manner in which the first conductive layer 604 is formed includes a deposition, press or coating process. Next, a first insulating layer 606 is formed on the first conductive layer 604. The first insulating layer 606 may be an epoxy resin, a bismaleimie triacine (BT), or a poly Polyimide (PI), ajinomoto build-up film, polyphenylene oxide (PPO), polypropylene (PP), polymethyl methacrylate (PMMA) Or polytetrafluorethylene (PTFE). In some embodiments, the first insulating layer 606 can be formed on the first conductive layer 604 by press bonding or coating.

Thereafter, a second conductive layer 608 and a third conductive layer 610 are formed on the first insulating layer 606. In some embodiments, the second conductive layer 608 and the third conductive layer 610 may comprise nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations of the foregoing, or alloys thereof. The second conductive layer 608 and the third conductive layer 610 may comprise the same material or, in another embodiment, comprise different materials material. For example, the second conductive layer 608 may be a thick copper layer for carrying the third conductive layer 610, and the third conductive layer 610 may be a thin copper layer. In some embodiments, the second conductive layer 608 may have a thickness of 12 μm to 36 μm, and the third conductive layer 610 may have a thickness of 1 μm to 6 μm. In some embodiments, the second conductive layer 608 and the third conductive layer 610 may be formed on the first insulating layer 606 by press bonding or electroplating.

Referring to FIG. 6B, a first photosensitive layer 612 including a plurality of openings is formed on the third conductive layer 610. The first photosensitive layer 612 can be formed by laminating a dry film, or by coating and subsequent lithography. It should be noted that the size of the opening of the first photosensitive layer 612 in this embodiment is smaller than the size of the opening of the first photosensitive layer 512 in FIG. 5B. For example, the size of the opening of the first photosensitive layer 612 in the embodiment of FIG. 6B may be 20 μm. ~110 μm, and the opening of the first photosensitive layer 512 of FIG. 5B may have a size of 100 μm to 300 μm.

Referring to FIG. 6C, a fourth conductive layer 614 is formed on a region of the third conductive layer 610 that is not covered by the first photosensitive layer 612 (that is, in the opening). In some embodiments, the fourth conductive layer 614 comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations thereof, or alloys thereof. The fourth conductive layer 614 may be grown in the opening of the first photosensitive layer 612 by electroplating. Subsequently, the first photosensitive layer 612 is removed.

Referring to FIG. 6D, a second insulating layer 616 is formed on the third conductive layer 610, the fourth conductive layer 614, and the first insulating layer 606. In some embodiments, the second insulating layer 616 may be an epoxy resin, a bismaleimie triacine (BT), a polyimide (PI), or an increase. Ajinomoto build-up film, polyphenylene oxide (PPO), polypropylene (PP), polymethyl acrylate (polymethyl methacrylate) Methacrylate, PMMA) or polytetrafluorethylene (PTFE). The second insulating layer 616 can be formed by pressing or coating.

Next, a fifth conductive layer 618 is formed on the second insulating layer 616. In some embodiments, the fifth conductive layer 618 comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations of the foregoing, or alloys thereof.

Referring to FIG. 6E, a dicing process is performed to cut off portions of the first insulating layer 606 and the second insulating layer 616, so that the second conductive layer 608 can be separated from the third conductive layer 610 in a subsequent step.

Referring to FIG. 6F, the second conductive layer 608 is separated from the third conductive layer 610 such that the core plate 602 is separated from the second insulating layer 616. The step of turning over the separated second insulating layer 616 and the conductive layers thereon is such that the bottom portion faces upward and the top portion faces downward, as shown in FIG. 6F.

Referring to FIG. 6G, after inversion, the second insulating layer 616 includes a first side 624 and a second side 626 opposite the first side 624. A second drilling process is performed on the second insulating layer 616 to form a through hole 620 through the second insulating layer 616. In some embodiments, the method of forming the via 620 includes a laser double sided pair drill, that is, a laser drilling process from the first side 624 and the second side 626 of the first insulating layer 606. It should be noted that the through hole 620 formed by the laser double-sided drilling process has a funnel shape, that is, the through hole 620 is adjacent to the opening portion of the first side 624 and the second side 626 of the second insulating layer 616. The large size, while the central portion of the second insulating layer 616 has a smaller size.

Thereafter, a plating initiation layer 622 is formed in the via 620, the third conductive layer 610, and the fifth conductive layer 618. In some embodiments, the plating initiation layer 622 comprises a combination of nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, or alloys thereof. The plating initiation layer 622 can be fabricated by electroless plating.

Referring to FIG. 6H, a second photosensitive layer 628 including a plurality of openings is formed over the plating initiation layer 622 of the first side 624 of the second insulating layer 616. A third photosensitive layer 630 including a plurality of openings is formed under the plating initiation layer 622 of the second side 626 of the second insulating layer 616. The second photosensitive layer 628 and the third photosensitive layer 630 may be formed by laminating a dry film, or coating and subsequent lithography processes. In some embodiments, the size of the opening of the second photosensitive layer 628 is smaller than the size of the opening of the third photosensitive layer 630.

Subsequently, an electroplating process is performed to form a sixth conductive layer 632 in the opening of the second photosensitive layer 628, the opening of the third photosensitive layer 630, and the via 620. The sixth conductive layer 632 is filled in the through hole 620 to form a conductive hole 633. The wire 634 is formed in the opening of the second photosensitive layer 628, and the pad layer 636 is formed in the opening of the third photosensitive layer 630. In some embodiments, the sixth conductive layer 632 comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations thereof, or alloys thereof. Thereafter, referring to FIG. 6J, the second photosensitive layer 628 and the third photosensitive layer 630 are removed, and an etching process is performed to remove the third conductive layer 610 and the fifth conductive layer 618 that are not covered by the sixth conductive layer 632. And the plating start layer 622, forming a printed circuit board 650 as shown in Fig. 6J. In some embodiments, the printed circuit board 650 does not include a core board.

It should be noted that in the present embodiment, after the above etching step, the fourth conductive layer 614 together with a portion of the conductive vias 633 constitute a pad layer 638.

In FIG. 6J, insulating layer 616 includes a first side 624 and a second side 626. A plurality of first pad layers 638 are embedded in the insulating layer 616 adjacent to the first side 624 of the insulating layer 616. A plurality of second pad layers 636 are located on the second side 626 of the insulating layer 616. A plurality of conductive vias 633 are located in the insulating layer 616 and connect the first pad layer 638 and the second pad layer 636. In some embodiments, the conductive via 633 has a drain The bucket shape, that is, the portion of the conductive via 633 adjacent to the first pad layer 638 and the second pad layer 636 has a larger size than the portion adjacent to the center of the second insulating layer 616.

A plurality of wires 634 are located on the first side 624 of the first pad layer 638 and the insulating layer 616. In some embodiments, the wire 634 is in a different layer than the first pad layer 638. Therefore, the distance between the wire 634 and the first pad layer 638 is not limited by the process capability of image transfer, such as the wire 634 on the insulating layer 616. The minimum distance from the adjacent first pad layer 638 may be 10 μm or less.

Hereinafter, a method of fabricating a printed circuit board according to an embodiment of the present invention will be described based on FIGS. 7A to 7K. Referring to Figure 7A, a core board 702 is provided. In some embodiments, the core sheet 702 comprises a paper phenolic resin, a composite epoxy, a polyimide resin, or a glass fiber.

Subsequently, a first conductive layer 704 is formed on the core board 702. In some embodiments, the first conductive layer 704 comprises a combination of nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, or alloys thereof. The manner in which the first conductive layer 304 is formed includes a deposition, press bonding, or coating process. Next, a first insulating layer 706 is formed on the first conductive layer 704. The first insulating layer 706 may be an epoxy resin, a bismaleimie triacine (BT), or a poly Polyimide (PI), ajinomoto build-up film, polyphenylene oxide (PPO), polypropylene (PP), polymethyl methacrylate (PMMA) Or polytetrafluorethylene (PTFE). In some embodiments, the first insulating layer 706 can be formed on the first conductive layer 704 by press bonding or coating.

Thereafter, a second conductive layer is formed on the first insulating layer 706. 708 and a third conductive layer 710. In some embodiments, the second conductive layer 708 and the third conductive layer 710 may comprise nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations of the foregoing, or alloys thereof. The second conductive layer 708 and the third conductive layer 710 may comprise the same material or, in another embodiment, comprise a different material. For example, the second conductive layer 708 can be a thicker copper layer for carrying the third conductive layer 710, and the third conductive layer 710 can be a thinner copper layer. In some embodiments, the second conductive layer 708 may have a thickness of 12 μm to 36 μm, and the third conductive layer 710 may have a thickness of 1 μm to 6 μm. In some embodiments, the second conductive layer 708 and the third conductive layer 710 may be formed on the first insulating layer 706 by press bonding or electroplating.

Referring to FIG. 7B, a first photosensitive layer 712 including an opening 714 and an opening 715 is formed on the third conductive layer 710. The first photosensitive layer 712 can be formed by laminating dry film or coating and subsequent lithography processes.

Referring to FIG. 7C, a fourth conductive layer 716 and a wire 717 are formed on a region of the third conductive layer 710 that is not covered by the first photosensitive layer 712 (ie, in the opening 714 and the opening 715). In some embodiments, the fourth conductive layer 716 and the wires 717 comprise nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations thereof, or alloys thereof. The fourth conductive layer 716 and the wires 717 can be grown in the opening 714 and the opening 715 of the first photosensitive layer 712 by electroplating. Subsequently, the first photosensitive layer 712 is removed.

Referring to FIG. 7D, a second insulating layer 718 is formed on the third conductive layer 710, the fourth conductive layer 716, the wires 717, and the first insulating layer 706. In some embodiments, the second insulating layer 718 may be an epoxy resin, a bismaleimie triacine (BT), a polyimide (PI), or an increase. Aginomoto build-up film, polyphenylene oxide (PPO), polyacrylic acid Polypropylene (PP), polymethyl methacrylate (PMMA) or polytetrafluorethylene (PTFE). The second insulating layer 718 may be formed on the third and fourth conductive layers 710, 716 and the wires 717 by press bonding or coating.

Next, referring to FIG. 7E, a fifth conductive layer 720 is formed on the second insulating layer 718. In some embodiments, the fifth conductive layer 720 comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations thereof, or alloys thereof. A hole drilling process is performed to form a blind via 724 in the fifth conductive layer 720 and the second insulating layer 718 to expose the fourth conductive layer 716. In some embodiments, the method of forming the blind holes 724 includes a laser drilling process. Thereafter, a plating initiation layer 722 is formed in the blind vias 724 and on the second insulating layer 718. In some embodiments, the plating initiation layer 722 comprises a combination of nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, or alloys thereof. The plating initiation layer 722 can be formed by electroless plating.

Referring to FIG. 7F, a second photosensitive layer 726 including a plurality of openings 728 is formed on the plating initiation layer 722. The second photosensitive layer 726 can be formed by screen printing, dry film coating or coating, and subsequent lithography processes.

Subsequently, the plating initiation layer 722 is used as a seed layer for electroplating, and an electroplating process is performed to grow a sixth conductive layer 730 in a region (ie, opening 728) where the electroplating initiation layer 722 is not covered by the second photosensitive layer 726. . The sixth conductive layer 730 can be filled into the blind vias to form a conductive via 733, and/or a pad layer 734 can be formed in the other opening 728. In some embodiments, the sixth conductive layer 730 comprises nickel, gold, tin, lead, copper, aluminum, silver, chromium, tungsten, combinations of the foregoing, or alloys thereof.

Referring to FIG. 7G, the second photosensitive layer 726 is removed and the plating initiation layer 722 and the fifth conductive layer covering the second photosensitive layer 726 are removed. 720. In some embodiments, the step of removing the plating start layer 722 and the fifth conductive layer 720 over the second photosensitive layer 726 may be performed by chemical etching. Referring to FIG. 7H, a dicing process is performed to cut off portions of the first insulating layer 706 and the second insulating layer 718, so that the second conductive layer 708 can be separated from the third conductive layer 710 in a subsequent step.

Referring to FIG. 7I, the second conductive layer 708 is separated from the third conductive layer 710 such that the core plate 702 is separated from the second insulating layer 718. The step of turning over the separated second insulating layer 718 and the conductive layers thereon is such that the bottom is facing upward and the top is facing downward, as shown in Fig. 7J.

Referring to FIG. 7J, after inversion, the second insulating layer 718 includes a first side 742 and a second side 744 opposite the first side 742. A third photosensitive layer 736 including an opening 738 is formed on the first side 742 of the second insulating layer 718, wherein the opening 738 corresponds to the fourth conductive layer 716. A fourth photosensitive layer 737 is formed on the second side 744 of the second insulating layer 718. In some embodiments, the fourth photosensitive layer 737 completely covers the second side 744 of the second insulating layer 718 and the sixth conductive layer 730 and the pad layer 734 thereon. The third photosensitive layer 736 and the fourth photosensitive layer 737 may be formed by laminating dry film, or coating and subsequent lithography processes.

Subsequently, referring to FIG. 7K, a copper bump 740 is grown in the opening 738 of the third photosensitive layer 736. Thereafter, the third photosensitive layer 736 and the fourth photosensitive layer 737 are removed, and an etching process is performed to remove the third conductive layer 710 not covered by the copper bumps 740 to form the printed circuit board 752 as shown in FIG. 7K. . In some embodiments, the printed circuit board 752 does not include a core board.

An embodiment of the present invention provides a printed circuit board comprising: an insulating layer including a first side and a second side opposite to the first side; a first pad layer embedded in the insulating layer and adjacent to the first One side; one second pad a layer on the second side of the insulating layer; a conductive hole in the insulating layer and connecting the first pad layer and the second pad layer; and a plurality of wires, wherein at least one of the wires is on the first side of the insulating layer.

An embodiment of the present invention provides a method of fabricating a printed circuit board, comprising: providing a core board; forming a first insulating layer on the core board; forming a first conductive layer on the first insulating layer; forming a second An insulating layer is disposed on the first conductive layer and the first insulating layer; separating the second insulating layer from the first insulating layer; and inverting the separated second insulating layer, wherein the inverted second insulating layer includes a first side and a second side opposite to the first side; forming a first pad layer embedded in the second insulating layer according to the first conductive layer, and the first pad layer is adjacent to the first side of the second insulating layer; and the second insulating layer After being separated from the first insulating layer, a plurality of wires are formed, wherein at least one of the wires is on the first side of the second insulating layer.

A printed circuit board comprising: an insulating layer comprising a first side and a second side opposite to the first side; a first pad layer and a wire respectively embedded in the insulating layer and adjacent to the first side; a second pad layer on the second side of the insulating layer; a conductive hole in the insulating layer and connecting the first pad layer and the second pad layer; and a copper bump on the first pad layer.

A manufacturing method of a printed circuit board, comprising: providing a core board; forming a first insulating layer on the core board; forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first conductive layer And separating the second insulating layer from the first insulating layer; inverting the separated second insulating layer, wherein the inverted second insulating layer comprises a first side and a first side opposite to the first side Forming a first pad layer and a wire embedded in the second insulating layer according to the first conductive layer, and the first pad layer and the wire are adjacent to the first side of the second insulating layer; and forming a copper bump in the first On a mat.

Although the preferred embodiments of the present invention are described above, it is not intended to limit the present invention, and any person skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

310‧‧‧ Third conductive layer

316‧‧‧4th conductive layer

318‧‧‧Second insulation

320‧‧‧ fifth conductive layer

322‧‧‧ plating initiation layer

330‧‧‧ sixth conductive layer

333‧‧‧Electrical hole

334‧‧‧ cushion

336‧‧‧third photosensitive layer

342‧‧‧ first side

344‧‧‧ second side

346‧‧‧Wire

350‧‧‧Second cushion

352‧‧‧Printed circuit board

Claims (34)

A printed circuit board comprising: an insulating layer comprising a first side and a second side opposite the first side; a first pad layer embedded in the insulating layer adjacent to the first side; a second pad layer on the second side of the insulating layer; a conductive hole in the insulating layer and connecting the first pad layer and the second pad layer; and at least one wire located at the insulating layer On one side; wherein the first mat has a greater width than the lead. The printed circuit board of claim 1, wherein the wire is on the first mat. The printed circuit board of claim 1, wherein the conductive via has a sloped sidewall. The printed circuit board of claim 1, wherein a portion of the conductive hole adjacent to the first pad layer is smaller in size than a portion adjacent to the second side of the insulating layer. The printed circuit board of claim 1, wherein the conductive via has vertical sidewalls. The printed circuit board of claim 1, wherein the minimum distance between the wire on the insulating layer and the first pad layer is 10 μm or less. The printed circuit board of claim 1, wherein the conductive hole is funnel shaped. The printed circuit board of claim 1, wherein the printed circuit board is a coreless printed circuit board. The printed circuit board of claim 1, wherein the wire is on the first side of the insulating layer other than the first pad layer. The printed circuit board of claim 9, further comprising: a protective layer covering the wire and the insulating layer, wherein the protective layer has at least one opening to expose the first pad layer, and at least one A copper bump is located in the opening and electrically connected to the first pad layer. A manufacturing method of a printed circuit board, comprising: providing a core board; forming a first insulating layer on the core board; forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first a conductive layer and the first insulating layer; separating the second insulating layer from the first insulating layer; inverting the separated second insulating layer, wherein the inverted second insulating layer comprises a first side And a second side opposite to the first side; forming a first pad layer embedded in the second insulating layer according to the first conductive layer, and the first pad layer is adjacent to the first side of the second insulating layer; And after the second insulating layer is separated from the first insulating layer, at least one is formed a wire on the first side of the second insulating layer; wherein the first pad has a greater width than the wire. The method of fabricating a printed circuit board according to claim 11, wherein before the second insulating layer is separated from the first insulating layer, a conductive hole is formed in the second insulating layer. The method of fabricating a printed circuit board according to claim 12, wherein before the separating the second insulating layer from the first insulating layer, forming a second pad layer on the second insulating layer. The method for fabricating a printed circuit board according to claim 13, wherein the conductive via is formed in the same step as the second underlayer. The method of fabricating a printed circuit board according to claim 11, wherein after the second insulating layer is separated from the first insulating layer, a conductive hole is formed in the second insulating layer. The method for fabricating a printed circuit board according to claim 15, wherein after the second insulating layer is separated from the first insulating layer, the second pad layer is further formed on the second insulating layer. side. The method for fabricating a printed circuit board according to claim 16, wherein the wire, the conductive hole and the second pad are produced in the same step. The method for fabricating a printed circuit board according to claim 11, wherein after the second insulating layer is separated from the first insulating layer, a mechanical drilling step is performed on the second insulating layer to form a pass. a hole, and the conductive material is filled in the through hole to form a conductive hole. The method for fabricating a printed circuit board according to claim 18, further comprising forming a second underlayer on the second side of the second insulating layer. The method for fabricating a printed circuit board according to claim 19, wherein the second underlayer, the wires and the conductive holes are formed in the same step. The method of fabricating a printed circuit board according to claim 11, wherein after the second insulating layer is separated from the first insulating layer, the first side and the second side of the second insulating layer are further included A laser drilling step is separately performed to form a through hole, and a conductive material is filled in the through hole to form a conductive hole. The method for fabricating a printed circuit board according to claim 21, further comprising forming a second pad layer on a second side of the second insulating layer, and the second pad layer, the wire and the conductive hole are Made in the same step. The method of fabricating a printed circuit board according to claim 11, wherein the wire is formed on the first side of the second insulating layer other than the first pad layer. The method for manufacturing a printed circuit board according to claim 11, further comprising: forming a protective layer on the wire and covering the second insulating layer; forming at least one opening in the protective layer to expose the a first pad layer; and forming at least one copper bump in the opening and electrically connected to the first pad layer. A printed circuit board comprising: an insulating layer comprising a first side and a second side opposite to the first side; a first pad layer and a wire respectively embedded in the insulating layer and adjacent to the first a first pad, wherein the first pad layer has a larger width than the wire; a second pad layer is located on the second side of the insulating layer; a conductive hole is located in the insulating layer, and the first pad is connected a layer and the second pad; and a copper bump on the first pad. The printed circuit board of claim 25, wherein the conductive via has a sloped sidewall. The printed circuit board of claim 25, wherein a portion of the conductive hole adjacent to the first pad layer is smaller in size than a portion adjacent to the second side of the insulating layer. The printed circuit board of claim 25, wherein the printed circuit board is a coreless printed circuit board. A manufacturing method of a printed circuit board, comprising: providing a core board; forming a first insulating layer on the core board; forming a first conductive layer on the first insulating layer; forming a second insulating layer on the first a conductive layer and the first insulating layer; separating the second insulating layer from the first insulating layer; inverting the separated second insulating layer, wherein the second insulating layer is inverted The edge layer includes a first side and a second side opposite to the first side; forming a first pad layer and a wire embedded in the second insulating layer according to the first conductive layer, and the first pad layer And the wire is adjacent to the first side of the second insulating layer, wherein the first pad layer has a larger width than the wire; and a copper bump is formed on the first pad layer. The method of fabricating a printed circuit board according to claim 29, wherein before the second insulating layer is separated from the first insulating layer, a conductive hole is formed in the second insulating layer. The method of fabricating a printed circuit board according to claim 29, wherein before the second insulating layer is separated from the first insulating layer, forming a second pad layer on the second insulating layer. The method for fabricating a printed circuit board according to claim 29, wherein the conductive via is formed in the same step as the second underlayer. The method for fabricating a printed circuit board according to claim 29, wherein after the second insulating layer is separated from the first insulating layer, a conductive hole is formed in the second insulating layer. The method for fabricating a printed circuit board according to claim 29, wherein after the second insulating layer is separated from the first insulating layer, the second pad layer is further formed on the second insulating layer. side.