TWI544605B - An electro-static discharge protection device with nmos trigger - Google Patents

Description

Electrostatic discharge protection element triggered by N-type gold oxide semi-transistor

The invention relates to a protection technology for electrostatic discharge, and is an electrostatic discharge protection component based on a laterally controlled rectifier.

In recent years, although semiconductor technology continues to advance, Electro-Static Discharge (ESD) protection is becoming more and more difficult to handle. In general, the lateral-controlled parallel rectifier (SCR) is considered to be the most effective ESD protection component because it is compared to other protection components. It has a better human body model (HBM) failure threshold voltage and a second breakdown current (I _t2 ).

However, the holding voltage (V _H ) of the step-controlled rectifier is lower than the operating voltage of the above-mentioned circuit component compared to the circuit component to be protected, so that under the normal operation of the above-mentioned circuit component External noise is easy to trigger the rectifier rectifier and cause it to enter a latch-up state, which will further cause malfunction or permanent damage to the above circuit components. Therefore, it is necessary to develop new electrostatic discharge protection technologies to improve the above problems.

In order to achieve the object, according to an aspect of the present invention, an embodiment provides an electrostatic discharge protection component including: an anode terminal and a cathode terminal; and a floating gated rectifier unit, including: a P-type semiconductor substrate and a formation An N-type semiconductor well region in the P-type semiconductor substrate; a first insulating region, a second insulating region, a third insulating region and a fourth insulating region are formed in the N-type semiconductor well region; An N ⁺ -type semiconductor region is formed between the first insulating region and the second insulating region; a second N ⁺ -type semiconductor region is formed between the second insulating region and the third insulating region; a P ⁺ -type semiconductor region is formed between the third insulating region and the fourth insulating region; a fifth insulating region and a sixth insulating region are formed in the P-type semiconductor substrate; a third N ⁺ type a semiconductor region formed between the fourth insulating region and the fifth insulating region; and a second P ⁺ -type semiconductor region formed between the fifth insulating region and the sixth insulating region; and a trigger switch unit Including a gold-oxygen half-field effect transistor with a drain connected to the anode , And its gate connected to its source; source wherein the first N ⁺ type semiconductor region connected to the anode terminal of the second N ⁺ type semiconductor region connected to the metal oxide semiconductor field effect transistor of the electrode, the second P ⁺ type semiconductor region and said third N ⁺ type semiconductor region connected to the cathode terminal, and the P ⁺ type first semiconductor region in contact with the third addition to the insulating region, the insulating region and the fourth N-type semiconductor well region unconnected To other places.

According to another aspect of the present invention, an embodiment provides an electrostatic discharge protection component including: an anode terminal and a cathode terminal; and a floating gated rectifier unit, including: a P-type semiconductor substrate and a P-type semiconductor substrate formed thereon An N-type semiconductor well region in the semiconductor substrate; a first insulating region, a second insulating region and a third insulating region are formed in the N-type semiconductor well region; and a first N ⁺ -type semiconductor region is formed in the semiconductor region Between the first insulating region and the second insulating region; a first P ⁺ -type semiconductor region formed between the second insulating region and the third insulating region; a fourth insulating region and a fifth insulating region And a sixth insulating region formed in the P-type semiconductor substrate; a second N ⁺ -type semiconductor region formed between the third insulating region and the fourth insulating region; and a second P ⁺ -type semiconductor region, Formed between the fourth insulating region and the fifth insulating region; and a third P ⁺ -type semiconductor region formed between the fifth insulating region and the sixth insulating region; and a trigger switch unit, including a a gold-oxygen half-field effect transistor whose source is connected to the cathode terminal and its gate Its source is connected; wherein the first N ⁺ type first semiconductor region and the P ⁺ type semiconductor region connected to the anode terminal, the second P ⁺ type semiconductor region connected to the drain of the mosfet transistor poles, the The third P ⁺ -type semiconductor region is connected to the cathode terminal, and the second N ⁺ -type semiconductor region is not connected to other portions except the third insulating region, the fourth insulating region, and the P-type semiconductor substrate.

100, 200, 300‧‧‧ Electrostatic discharge protection components

110‧‧‧Anode end

120‧‧‧ cathode end

130‧‧‧Floating controlled rectifier unit

131‧‧‧P type semiconductor substrate

132‧‧‧N type semiconductor well area

1331‧‧‧First insulation zone

1332‧‧‧Second insulation zone

1333‧‧‧3rd insulation zone

1334‧‧‧4th insulation zone

1335‧‧‧5th insulation zone

1336‧‧‧6th insulation zone

1341‧‧‧First N ⁺ type semiconductor region

1342‧‧‧Second N ⁺ type semiconductor region

1343‧‧‧Third N ⁺ type semiconductor region

1351‧‧‧First P ⁺ type semiconductor region

1352‧‧‧Second P ⁺ type semiconductor region

1353‧‧‧ third P ⁺ type semiconductor region

160‧‧‧Trigger switch unit

C‧‧‧ capacitor

R _P , R _N ‧‧‧resistance

PNP‧‧‧PNP type bipolar junction transistor

NPN‧‧‧NPN type bipolar junction transistor

D‧‧‧ diode

Q1‧‧‧Gold oxygen half-field effect transistor

Fig. 1 is a block diagram showing an electrostatic discharge protection element according to an embodiment of the present invention.

Fig. 2 is a schematic view of an electrostatic discharge protection element according to a first embodiment of the present invention.

Figure 3 is a schematic view of an electrostatic discharge protection element in accordance with a second embodiment of the present invention.

In order to further understand and understand the features, objects and functions of the present invention, the embodiments of the present invention are described in detail with reference to the drawings. In all of the specification and the drawings, the same component numbers will be used to designate the same or similar components.

In the description of the various embodiments, when an element is described as "above/on" or "below/under" another element, it is meant to be directly or indirectly above or below the other element. , which may contain other elements set in between; the so-called "directly" means that no other intermediary elements are set in between. The descriptions of "Upper/Upper" or "Bottom/Lower" are based on the schema, but also include other possible direction changes. The so-called "first", "second", and "third" are used to describe different elements that are not limited by such predicates. For the convenience and clarity of the description, the thickness or size of each element in the drawings is expressed in an exaggerated or omitted or schematic manner, and the size of each element is not completely the actual size.

1 is a block diagram of an electrostatic discharge protection component 100 in accordance with an embodiment of the present invention. The ESD protection component 100 has two component end points: an anode end 110 and a cathode end 120, and And comprising two main circuit units: the control rectifier unit 130 and the trigger switch unit 160, the main function of which is to prevent external integrated circuit components from being damaged by electrostatic discharge (ESD). The anode end 110 and the cathode end 120 are for connection to the external circuit component that is intended to protect against electrostatic discharge. The controlled rectifier unit 130 is based on a lateral SCR which is commonly used for electrostatic discharge protection, and changes its circuit structure to a floating state to improve its electrostatic discharge protection performance. In addition, the voltage-controlled rectifying unit 130 is further equipped with the trigger switch unit 160 to provide a trigger switch mechanism, so that the ESD protection component 100 can determine whether to activate the 外部 according to whether the external circuit component is subjected to an electrostatic discharge attack. The electrostatic discharge protection function of the rectifying unit 130 is controlled. The internal circuit structure of the pilot rectification unit 130 and the trigger switch unit 160 and its operation will be described in detail below according to different embodiments.

2 is a schematic diagram of an electrostatic discharge protection component 200 having an N-type MOS transistor trigger according to a first embodiment of the present invention; wherein block 130 illustrates the component cross-sectional structure of the quaternary rectification unit 130 and its equivalent The circuit diagram, and block 160 illustrates the circuit configuration of the trigger switch unit 160. The controlled rectifier unit 130 is a semiconductor component constructed on a P-type semiconductor substrate 131, and includes: an N-type semiconductor well region 132 formed in the P-type semiconductor substrate 131, and six isolation semiconductor regions. An insulating region (a first insulating region 1331, a second insulating region 1332, a third insulating region 1333, and a fourth insulating region 1334 are formed in the N-type semiconductor well region 132, and the fifth insulating region 1335 and the sixth insulating region 1336 are formed. In the P-type semiconductor substrate 131, three N ⁺ -type semiconductor regions (the first N ⁺ -type semiconductor region 1341 is formed between the first insulating region 1331 and the second insulating region 1332, and the second N ⁺ -type semiconductor) a region 1342 is formed between the second insulating region 1332 and the third insulating region 1333, a third N ⁺ -type semiconductor region 1343 is formed between the fourth insulating region 1334 and the fifth insulating region 1335, and two a P ⁺ -type semiconductor region (a first P ⁺ -type semiconductor region 1351 is formed between the third insulating region 1333 and the fourth insulating region 1334), and a second P ⁺ -type semiconductor region 1352 is formed in the fifth insulating region 1335 and the Between the sixth insulating regions 1336).

As shown, the first P ⁺ type semiconductor region 1351, the N-type semiconductor well region 132 and the P-type semiconductor substrate 131 may be formed equivalently a bipolar junction PNP type transistor (Bipolar Junction Transistor 2 in FIG. , abbreviated as BJT), and the third N ⁺ -type semiconductor region 1343, the P-type semiconductor substrate 131 and the N-type semiconductor well region 132 can equivalently form an NPN-type bipolar junction transistor; a P ⁺ -type semiconductor region 1351 , the N-type semiconductor well region 132 and the P-type semiconductor substrate 131 are respectively an emitter, a base and a collector of the PNP-type bipolar junction transistor, and the third N ⁺ -type semiconductor The region 1343, the P-type semiconductor substrate 131 and the N-type semiconductor well region 132 are respectively an emitter, a base and a collector of the NPN-type bipolar junction transistor. Therefore, the two PNP type and NPN type bipolar junction transistors can be combined into a PNPN type of controlled rectifier.

In this embodiment, the first N ⁺ -type semiconductor region 1341 is connected to the anode terminal 110, and the third N ⁺ -type semiconductor region 1343 and the second P ⁺ -type semiconductor region 1352 are connected to the cathode terminal 120 in common. The first P ⁺ -type semiconductor region 1351 floats, that is, the first P ⁺ -type semiconductor region 1351 is structurally in contact with the third insulating region 1333, the fourth insulating region 1334, and the N-type semiconductor well region 132. It is not connected to other circuits or components. In addition, the first P ⁺ -type semiconductor region 1351 , the N-type semiconductor well region 132 , and the first N ⁺ -type semiconductor region 1341 can equivalently form a reverse biased diode D, and the diode D The anode is connected to the emitter of the PNP type bipolar junction transistor. As shown in FIG. 2, the N-type semiconductor well region 132 can equivalently form a resistor R _N , and the P-type semiconductor substrate 131 can equivalently form a resistor R _P .

On the other hand, the trigger switch unit 160 includes a MOS field-effect transistor Q1, the drain of which is connected to the anode terminal 110, and the gate thereof is connected to its source such that the gate of the MOS field-effect transistor Q1 and the potential difference between the source (V _GS) is zero, to ensure that the potential difference V _GS is less than the metal oxide semiconductor field effect transistor Q1 is the threshold voltage (V _th). In addition, the source of the MOS field-effect transistor Q1 is connected to the second N ⁺ -type semiconductor region 1342, thereby connecting the thyristor unit 130 to the trigger switch unit 160.

In general, when an electrostatic discharge occurs, an ESD pulse of about 100 to 200 ns is generated between the anode terminal 110 and the cathode terminal 120. In this embodiment, the cathode end 120 is grounded, and the MOS field-effect transistor Q1 is an N-type MOS field-effect transistor. Please refer to the equivalent circuit of the controlled rectifier unit 130 and the circuit of the trigger switch unit 160 shown in FIG. 2 . When the ESD protection component 200 is in normal operation, no ESD pulse enters the anode terminal 110, and the V _GS of the N-type MOS field-effect transistor Q1 of the trigger switch unit 160 is zero, less than its threshold voltage. (V _th ), and thus will be in an OFF state, in that the floating control rectifier unit 130 is not actuated, without affecting the normal operation of the external integrated circuit components. Conversely, when the ESD protection component 200 is subjected to electrostatic discharge, there will be an ESD pulse entering the anode terminal 110, causing the gate/source short-circuiting of the MOS field-effect transistor Q1 to collapse. The effect is ON, thus generating a sufficiently large current at the output of the triggering switch unit 160, triggering the reverse bias diode D via the second N ⁺ -type semiconductor region 1342 to cause it to enter a collapse state early. Turning on, the controlled rectifier unit 130 is activated to perform a protection mechanism for electrostatic discharge.

For the control rectifier unit 130 alone, the purpose of floating the first P ⁺ -type semiconductor region 1351 is to enable the voltage-controlled rectifying unit 130 to maintain its anode when the electrostatic discharge protection element 200 is normally operated. An open state between the first N ⁺ -type semiconductor region 1341) and the cathode (the third N ⁺ -type semiconductor region 1343); that is, the controlled rectifier unit 130 is hardly triggered or activated, so that it remains The holding voltage (V _H ) is sufficient to exceed the supply voltage to enhance the immunity of the latch-up. In this embodiment, the trigger switch unit 160 is configured to trigger the reverse bias diode D in the early stage of the electrostatic discharge attack, so that the reverse bias diode D is prematurely collapsed and turned on, thereby achieving the early control. The secondary breakdown current/I _{t2 of the} rectifying unit 130. The trigger switch unit 160 may be subjected to an electrostatic discharge attack or a general circuit operation condition to determine whether to trigger or turn on the reverse bias diode D to achieve the purpose of electrostatic discharge protection, and is in normal condition. Provides good latch-up immunity in the case of operation.

3 is a schematic diagram of an electrostatic discharge protection component 300 according to a second embodiment of the present invention; wherein an element cross-sectional structure of the floating gated rectification unit 130 and an equivalent circuit diagram thereof, and a circuit of the trigger switch unit 160 are illustrated. structure. The controlled rectifier unit 130 is a semiconductor component constructed on a P-type semiconductor substrate 131, and includes: an N-type semiconductor well region 132 formed in the P-type semiconductor substrate 131, and six isolation semiconductor regions. An insulating region (a first insulating region 1331, a second insulating region 1332, and a third insulating region 1333) are formed in the N-type semiconductor well region 132, and the fourth insulating region 1334, the fifth insulating region 1335, and the sixth insulating region 1336 are formed. inside the P type semiconductor substrate 131), two N ⁺ -type semiconductor region (N ⁺ type first semiconductor region 1341 is formed in the insulating region between the first 1331 and the second insulating region 1332, a second N ⁺ -type semiconductor a region 1342 is formed between the third insulating region 1333 and the fourth insulating region 1334), and three P ⁺ -type semiconductor regions (the first P ⁺ -type semiconductor region 1351 is formed in the second insulating region 1332 and the third Between the insulating regions 1333, a second P ⁺ -type semiconductor region 1352 is formed between the fourth insulating region 1334 and the fifth insulating region 1335, and a third P ⁺ -type semiconductor region 1353 is formed in the fifth insulating region 1335 and the Between the sixth insulating regions 1336).

As shown in FIG. 3, the first P ⁺ -type semiconductor region 1351, the N-type semiconductor well region 132, and the P-type semiconductor substrate 131 can equivalently form a PNP-type bipolar junction transistor, and the first The N ⁺ -type semiconductor region 1342, the P-type semiconductor substrate 131 and the N-type semiconductor well region 132 can equivalently form an NPN-type bipolar junction transistor; wherein the first P ⁺ -type semiconductor region 1351 The N-type semiconductor well region 132 and the P-type semiconductor substrate 131 are respectively an emitter, a base and a collector of the PNP-type bipolar junction transistor, and the second N ⁺ -type semiconductor region 1342 and the P-type semiconductor substrate 131 and the N-type semiconductor well region 132 are respectively an emitter, a base and a collector of the NPN-type bipolar junction transistor. Therefore, the two PNP type and NPN type bipolar junction transistors can be combined into a PNPN type of controlled rectifier.

In this embodiment, the first N ⁺ -type semiconductor region 1341 and the first P ⁺ -type semiconductor region 1351 are connected in common to the anode terminal 110, the second P ⁺ -type semiconductor region 1352 and the third P ⁺ -type semiconductor region. 1353 ends respectively connected to the trigger switch unit 160, and the second N ⁺ type floating semiconductor region 1342 (floating), i.e. the second N ⁺ type semiconductor region 1342 in contact with the third insulating region in addition to the structure 1333, the fourth insulating region 1334, and the P-type semiconductor substrate 131 are not connected to other circuits or elements. In addition, the second N ⁺ -type semiconductor region 1342, the P-type semiconductor substrate 131, and the third P ⁺ -type semiconductor region 1353 can equivalently form a reverse biased diode D, and the cathode of the diode D Connected to the emitter of the NPN-type bipolar junction transistor. As shown in FIG. 3, the N-type semiconductor well region 132 can equivalently form a resistor R _N , and the P-type semiconductor substrate 131 can equivalently form a resistor R _P .

On the other hand, the trigger switch unit 160 comprises a metal-oxide-semiconductor field-effect transistor Q1, a drain connected to the silicon controlled rectifier unit of the second P ⁺ type semiconductor region 1,352,130, and its gate connected to its source, such that The potential difference (V _GS ) between the gate and the source of the MOS field Q1 is zero to ensure that the potential difference V _{GS is} less than the threshold voltage (V _th ) of the MOS field Q1. In addition, the source of the MOS field-effect transistor Q1 is connected to the third P ⁺ -type semiconductor region 1353, thereby connecting the thyristor unit 130 to the trigger switch unit 160.

In this embodiment, the cathode end 120 is grounded, and the MOS field-effect transistor Q1 is an N-type MOS field-effect transistor. Please refer to the equivalent circuit of the controlled rectifier unit 130 and the circuit of the trigger switch unit 160 shown in FIG. When the ESD protection component 300 is in normal operation, no ESD pulse enters the cathode terminal 120, and the V _GS of the N-type MOS field-effect transistor Q1 of the trigger switch unit 160 is zero, less than its threshold voltage. (V _th ), and thus will be in an OFF state, so that the throttle rectifier unit 130 is not actuated, without affecting the normal operation of the external integrated circuit components. Conversely, when the ESD protection component 200 is subjected to electrostatic discharge, there will be an ESD pulse entering the cathode end 120, causing the gate/source short circuit of the MOS field-effect transistor Q1 to collapse. The effect is ON, thus generating a sufficiently large current at the output of the triggering switch unit 160, triggering the reverse bias diode D via the second P ⁺ -type semiconductor region 1352 to cause it to enter a collapse state early. Turning on, the controlled rectifier unit 130 is activated to perform a protection mechanism for electrostatic discharge.

For the control rectifier unit 130 alone, the purpose of floating the second N ⁺ -type semiconductor region 1342 is to enable the voltage-controlled rectifying unit 130 to maintain its anode when the ESD protection device 300 is operating normally. 1341 between the off-state) and the cathode (the third P ⁺ type semiconductor region 1353) of the first N ⁺ -type semiconductor region; that is, the silicon controlled rectifier unit 130 is hardly started or triggered, such that it remains The holding voltage (V _H ) is sufficient to exceed the supply voltage to enhance the immunity of the latch-up. In this embodiment, the trigger switch unit 160 is configured to be turned on in the early stage of the electrostatic discharge attack to trigger the early collapse of the reverse bias diode D, thereby achieving the secondary collapse of the controlled rectifier unit 130 early. Second breakdown current/I _t2 . The trigger switch unit 160 may be subjected to an electrostatic discharge attack or a general circuit operation condition to determine whether to trigger or turn on the reverse bias diode D to achieve the purpose of electrostatic discharge protection, and is in normal condition. Provides good latch-up immunity in the case of operation.

The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited thereto. It is to be understood that the scope of the present invention is not limited by the spirit and scope of the present invention, and should be considered as a further embodiment of the present invention.

100‧‧‧Electrostatic discharge protection components

110‧‧‧Anode end

120‧‧‧ cathode end

130‧‧‧Floating controlled rectifier unit

131‧‧‧P type semiconductor substrate

132‧‧‧N type semiconductor well area

1331‧‧‧First insulation zone

1332‧‧‧Second insulation zone

1333‧‧‧3rd insulation zone

1334‧‧‧4th insulation zone

1335‧‧‧5th insulation zone

1336‧‧‧6th insulation zone

1341‧‧‧First N ⁺ type semiconductor region

1342‧‧‧Second N ⁺ type semiconductor region

1343‧‧‧Third N ⁺ type semiconductor region

1351‧‧‧First P ⁺ type semiconductor region

1352‧‧‧Second P ⁺ type semiconductor region

160‧‧‧Trigger switch unit

200‧‧‧Electrostatic discharge protection components

R _P , R _N ‧‧‧resistance

PNP‧‧‧PNP type bipolar junction transistor

NPN‧‧‧NPN type bipolar junction transistor

D‧‧‧ diode

Claims (10)

An electrostatic discharge protection component with an N-type MOS transistor triggering includes: an anode terminal and a cathode terminal; and a floating gate-controlled rectifier unit, comprising: a P-type semiconductor substrate and a P-type semiconductor substrate formed thereon An N-type semiconductor well region; a first insulating region, a second insulating region, a third insulating region and a fourth insulating region are formed in the N-type semiconductor well region; a first N ⁺ -type semiconductor region a P ⁺ type first semiconductor region; forming the insulating region between the first and the second insulating region; a second N ⁺ type semiconductor region formed in the insulating region between the second and the third insulating region Formed between the third insulating region and the fourth insulating region; a fifth insulating region and a sixth insulating region are formed in the P-type semiconductor substrate; a third N ⁺ -type semiconductor region is formed in the Between the fourth insulating region and the fifth insulating region; and a second P ⁺ -type semiconductor region formed between the fifth insulating region and the sixth insulating region; and a trigger switch unit including a gold oxide half field An effect transistor with its drain connected to the anode terminal and its gate connected to its source ; Wherein the first N ⁺ type semiconductor region connected to the anode terminal of the second N ⁺ type semiconductor region connected to the source of the metal oxide semiconductor field effect transistor of the electrode, the second P ⁺ type semiconductor region and said third N ⁺ The semiconductor region is connected to the cathode terminal, and the first P ⁺ -type semiconductor region is not connected to other portions except the third insulating region, the fourth insulating region, and the N-type semiconductor well region. The electrostatic discharge protection element of claim 1, wherein the cathode end is grounded. The electrostatic discharge protection device according to claim 1, wherein the MOS field effect transistor is an N-type MOS field effect transistor. The electrostatic discharge protection device of claim 1, wherein the first P ⁺ -type semiconductor region, the N-type semiconductor well region, and the P-type semiconductor substrate form a PNP-type bipolar junction transistor, The third N ⁺ -type semiconductor region, the P-type semiconductor substrate, and the N-type semiconductor well region form an NPN-type bipolar junction transistor. The electrostatic discharge protection device of claim 1, wherein the first P ⁺ -type semiconductor region, the N-type semiconductor well region, and the first N ⁺ -type semiconductor region form a reverse biased diode. An electrostatic discharge protection component with an N-type MOS transistor triggering includes: an anode terminal and a cathode terminal; and a floating gate-controlled rectifier unit, comprising: a P-type semiconductor substrate and a P-type semiconductor substrate formed thereon An N-type semiconductor well region; a first insulating region, a second insulating region and a third insulating region are formed in the N-type semiconductor well region; a first N ⁺ -type semiconductor region is formed in the first Between the insulating region and the second insulating region; a first P ⁺ -type semiconductor region formed between the second insulating region and the third insulating region; a fourth insulating region, a fifth insulating region, and a first a sixth insulating region formed in the P-type semiconductor substrate; a second N ⁺ -type semiconductor region formed between the third insulating region and the fourth insulating region; a second P ⁺ -type semiconductor region formed in the Between the fourth insulating region and the fifth insulating region; and a third P ⁺ -type semiconductor region formed between the fifth insulating region and the sixth insulating region; and a trigger switch unit including a gold oxide half field An effect transistor having a source connected to the cathode terminal and a gate connected to its source ; Wherein the first N ⁺ type first semiconductor region and the P ⁺ type semiconductor region connected to the anode terminal, the second P ⁺ type semiconductor region connected to the drain of the metal oxide semiconductor field effect transistor of the electrode, the third P ⁺ The semiconductor region is connected to the cathode terminal, and the second N ⁺ -type semiconductor region is not connected to other portions except for contacting the third insulating region, the fourth insulating region, and the P-type semiconductor substrate. The electrostatic discharge protection element of claim 6, wherein the cathode end is grounded. The electrostatic discharge protection component of claim 6, wherein the MOS field effect transistor is an N-type MOS field effect transistor. The electrostatic discharge protection device of claim 6, wherein the first P ⁺ -type semiconductor region, the N-type semiconductor well region, and the P-type semiconductor substrate form a PNP-type bipolar junction transistor, The second N ⁺ -type semiconductor region, the P-type semiconductor substrate, and the N-type semiconductor well region form an NPN-type bipolar junction transistor. The electrostatic discharge protection device of claim 6, wherein the first P ⁺ -type semiconductor region, the P-type semiconductor substrate, and the second N ⁺ -type semiconductor region form a reverse biased diode.