TWI544596B - Lead frame for IC package and manufacturing method - Google Patents

Description

Lead frame for IC package and manufacturing method

This patent application is generally related to integrated circuit (IC) packaging technology and, in particular, but not limited to, a lead frame for IC packaging and a method of fabricating the same.

This application claims the benefit of U.S. Provisional Application No. 61/166,547, filed on Apr. 3, 2009, and the Provisional Application No. 61/226,361, filed on Jul. 17, 2009, which is hereby incorporated by reference. in.

The IC package is one of the final stages of the fabrication of IC devices. During IC packaging, one or more IC chips are mounted on a package substrate, connected (equal) to electrical contacts, and then packaged as an electrical insulator including a compound such as an epoxy or polyoxymethylene molding compound. Encapsulation material coating. The resulting IC package can then be mounted on a printed circuit board (PCB) and/or connected to other electrical components.

Typically, an IC package can include electrical contacts instead of external leads, wherein the electrical contacts are covered by an encapsulation material and exposed to the bottom of the IC package, so that they can be connected to electrical circuitry under the IC package. Component. In general, the use of a metal leadframe to form portions of the IC package can be more cost effective than using a laminate or laminate tape material because, for example, more cost effective use of materials such as copper, nickel or other metals or metal alloys can be used. Materials and the use of such materials may allow for more cost effective manufacturing procedures, such as stamping or etching rather than multi-step lamination procedures.

The various embodiments disclosed in this application attempt to apply a partially etched and selectively plated leadframe to an integrated circuit (IC) package having high density contact points and fabrication methods. The above summary is not intended to represent each embodiment or aspects of the invention.

A more complete understanding of the various embodiments of the present invention can be obtained by referring

Various embodiments of the present invention will now be described more fully with reference to the accompanying drawings. However, the present invention may be embodied in many different forms and should not be construed as being limited to the embodiments described herein. The embodiments are provided so that this disclosure will be thorough and complete, and Those who are familiar with this technology.

Referring now to Figures 1A-1E, there are shown cross-sectional side views of one embodiment of an IC package at various stages of a fabrication process. For the purposes of this description, a manufacturing procedure with respect to a single IC package has been described, but as will be described in more detail below, the steps of the manufacturing process can be applied to some or all of the plurality of devices disposed on a lead frame strip region. Referring now to Figure 1A, the process begins with a lead frame 100, such as one of a metal strip having a substantially flat top surface and a flat bottom surface, which is unetched. Typically, a manufacturer will receive design criteria for an IC package, such as, for example, the size of an IC wafer to be mounted to the leadframe and the number of bond regions to be placed on one of the top surfaces of the leadframe. The design criteria may also include the size and location of the contact area to be placed on one of the bottom surfaces of the lead frame. The distance or spacing between the contact areas may depend on the minimum requirements of the electrical components on which the IC package is mounted, such as, for example, a PCB. In FIG. 1B, one of the top surfaces of the leadframe 100 is partially etched to create a recess 126 defining a metal trace 122 thereon. In the illustrated embodiment, a metal plating has been applied to the bonding regions 118 disposed on one of the top surfaces of the metal traces 122 and the contact regions 106 disposed on one of the metal traces 122. Formable by applying a bondable or solderable material to the metal traces 122, such as a plated or clad metal such as silver (Ag), gold (Au), copper (Cu), or other bondable material. Metallization of the bonding regions 118 and the contact regions 106. In various embodiments, the top surface of the leadframe 100 can be etched at a first location, such as a manufacturing plant, and can be, for example, in one of a different area of the manufacturing plant or a different manufacturing plant. The second position completes the remaining steps. In such embodiments, by partially etching the leadframe 100, the metal traces 122 are more stable and less likely to move than if the leadframe 100 were all etched.

In FIG. 1C, an IC wafer 104 has been secured to the leadframe 100 using an adhesive material 110 such as epoxy. After the IC wafer is mounted to the leadframe 100, the IC wafer can be electrically coupled to the bonding regions disposed outside the die attach regions, for example, via wire bonds 114. In FIG. 1D, an encapsulation compound 108 (shown as a shaded area) has been applied to encapsulate the IC wafer 104 and the wire bonds 114. In addition, the encapsulation compound 108 has also filled the recesses 126, including the recesses 126 disposed under the IC wafer 104. In FIG. 1E, one of the bottom surfaces of the lead frame 100 has been etched back. In various embodiments, the etch back of the bottom surface can include etching the portion 108a of the lead frame 100 corresponding to the recesses formed on one of the top surfaces of the lead frame 100 to completely etch the lead frame 100, thereby The metal traces 122 are electrically isolated from each other such that the remaining portion of the leadframe 100 electrically couples the bonding regions 118 to the contact regions 106 via the metal traces 122. In some embodiments, the etch back can include exposing a bottom surface of a portion of the encapsulation compound 108. In various embodiments, the etch back can include etching some of the etched portions 122a of the metal traces 122. As can be seen in the illustrated embodiment, the joint regions 118 are disposed laterally distal from the contact regions 106 such that no lines perpendicular to the top surface of the lead frame 100 intersect a joint region and a contact region. In various embodiments, the metal traces 122 can be configured to provide an electrical pathway or routing from the bond region 118 to a contact region 106 disposed at a laterally distal end of the IC wafer 104. In some embodiments, a protective coating 129 can be applied to the various lower surfaces of the leadframe 100 and encapsulation compound 108.

Referring now to Figures 2A-2B, various aspects of one embodiment of a portion of the etched leadframe 200 are shown. 2A is a top plan view of one of the etched lead frames 200 before an IC wafer is mounted thereon. 2B is a cross-sectional side view of one of the portions of the lead frame 200 corresponding to detail A of FIG. 2A. The leadframe 200 is shown having a plurality of recesses 226 (shown as unshaded portions) that are etched into a top surface of a predetermined pattern to define an upper portion of a plurality of metal traces 222 (shown as shaded portions). In the illustrated embodiment, each metal trace 222 has a bond region 218 disposed at one of its ends and a contact region 206 disposed at one of its opposite ends. Although only the top surface is etched in the illustration of this embodiment, the position on which the contact areas 206 are disposed on one of the bottom surfaces of the lead frame 200 has been shown as an unshaded square for the purpose of description. In FIG. 2B, a cross-sectional side view of detail A of FIG. 2A shows the leadframe 200 after the notches 226 are etched into the top surface of the leadframe 200 to define the upper portions of the metal traces 222.

Referring now to Figures 3A-3B, a top view and a bottom view of one embodiment of a partially etched leadframe 300 for an IC package fabrication process are shown. In FIG. 3A, an illustration of an IC wafer 304 is shown for purposes of description. In this embodiment, one of the fascia regions 318 (as shown by the solid square display) is disposed directly on the corresponding contact region (as shown by the dashed squares). In addition, an inner row of display joint regions 318 is disposed laterally distal from corresponding contact regions 306 and is electrically coupled to the contact regions 306 via metal traces 322.

Referring now to Figure 3B, a bottom view of the leadframe 300 can be seen. In the illustrated embodiment, the location of the bottom surface of the leadframe 300 in which the contact regions 306 can be disposed is shown as a solid square. In some embodiments, a metal plating may be applied to the contact regions 306 prior to etching. These metal traces 322 have been shown to be shaded portions for purposes of description. In some embodiments, the contact regions 306 are spaced apart by at least a minimum distance from each other, such as a minimum distance required by a PCB design specification. In the illustrated embodiment, the respective bonding regions 318 (shown as dashed squares) surrounding the perimeter of the leadframe 300 are disposed directly on a corresponding contact region 306 and thus the bonding regions 318 must also be at least spaced apart from one another. The minimum distance interval. However, because the inner rows of the metal traces 322 electrically coupled to the bond regions 318 are disposed laterally distal from the corresponding contact regions 306, the bond regions 318 can be less than the minimum distance interval required by the PCB design specifications. The contact areas 306 are still allowed to be spaced apart by at least the minimum distance from each other.

Referring now to Figure 4A, a top view of one embodiment of a portion of an etched and selectively plated leadframe 400 is shown. For the purpose of description, the outline of the location at which an IC wafer 404 can be mounted is shown as a dashed line. In this embodiment, a recess 426 is formed by etching away a portion of the top surface of the leadframe 400 to define an upper portion of the metal trace 422 on which the bonding region 418 is disposed. In this embodiment, the position on the bottom surface of the lead frame 400 on which the contact regions 406 are disposed is shown as being broken. As will be described in more detail below, all of the efflux of the bond regions 418 are disposed directly on the corresponding contact regions 406, while at least a portion of the inner rows of the bond regions 418 are not disposed directly on the corresponding contact regions 406, allowing within the bond regions 418. The rows are more closely spaced.

Referring now to Figure 4B, a top view and a side view of detail A and detail B of Figure 4A are shown. In detail A, the notch 426 has been etched into the top surface of one of the lead frames 400 to define a bonding region 418 coupled to the top surface of the lead frame 400 to the bottom surface of one of the lead frames 400. The upper portion of the metal trace 422 at the location of 406. Additionally, the top and bottom surfaces of the leadframe 400 have been selectively plated, for example, with a metal coating. As can be seen in the illustrated embodiment, the joint regions 418 and the contact regions 406 have substantially the same width. Because the bonding regions 418 are disposed directly on the contact regions 406, the spacing between the bonding regions 418 must be equal to the spacing between the contact regions 406, which is subject to the minimum requirements of the PCB on which the IC package will be mounted.

Referring now to detail B, there is provided a top view and a side view showing the insertion of the joint region 418 between the two joint regions 418 having the contact regions 406 directly below. In the illustrated embodiment, the bonding regions 418 are disposed on a top surface of the lead frame 400 and are displayed as a rectangle and a position on the bottom surface of the lead frame 400 on which the contact regions 406 are disposed are displayed as a circle. shape. In the embodiment shown in detail B, the width of the joint regions 418 has a reduced width relative to the joint regions shown in detail A. Since one of the contact areas (not shown) is disposed laterally distally from directly below the intermediate joint region 418, the width of the all joint regions 418 can be less than the width of the contact regions 406, thus allowing for such joints. Region 418 is disposed more closely than the contact regions 406.

Referring now to FIG. 5, there is shown a lead having an inner row surrounding one of the bond regions 518 at the periphery of a lead frame 500 and having an inner row of lands 518 disposed in a contact region 506 where an IC wafer 504 is to be mounted. A top view of one embodiment of the frame 500. In this embodiment, the ends of the metal traces 522 that are disposed within the inner regions of the bond regions 518 have a width that is greater than one of the remaining metal traces 522 that couple the bond regions 518 to the corresponding contact regions 506. For example, in various embodiments, the metal traces 522 can have a pitch of about 5.5 mils, with a width of about 1.5 mils and about 4 mils apart from one another. In various embodiments, the joint regions 518 can have a pitch of about 5.5 mils, with a width of about 2.5 mils and a spacing of about 3 mils from one another. In various embodiments, the minimum spacing of the contact regions 506 is determined by the need to mount the PCB of the IC package. In various embodiments, the contact regions 506 can have a diameter of about 6 mils and a pitch of 15.7 mils, a diameter of 7.9 mils, a pitch of 19.7 mils, or a diameter of 9.8 mils and 25.6. One of the mil spacing.

Referring now to Figures 6A-6C, top views of various embodiments of a portion of the etched leadframe 600 are shown. In FIG. 6A, an embodiment of a leadframe 600 is shown having a die attach pad (DAP) 602 partially defined on a top surface on which at least a portion of an IC die 604 can be mounted. In the illustrated embodiment, the area in which the IC wafer 604 is mounted (the die attachment area) includes both the DAP 602 and portions of the metal traces 622. In various embodiments, the DAP 602 can provide enhanced thermal dissipation and/or structural support, particularly for the IC wafer 604. In the embodiment shown in FIG. 6B, metal traces 622a are electrically coupled to the DAP 602 (for example) to provide electrical grounding for one of the IC wafers 604. In some embodiments, one or more channels may be formed in the DAP 602 to facilitate the flow of the encapsulating material into other isolated or hard to reach locations.

Referring now to Figure 6C, a top view of one of the lead frames 600 that can be used for etching a portion of an IC package is shown. In the illustrated embodiment, a location at which an IC die 604 can be mounted is displayed. As can be seen, in this embodiment, the IC die 604 is smaller than the IC wafers 604 of FIGS. 6A and 6B, showing that the metal traces allow at least a portion of the contact regions to be disposed distally from the corresponding bonding regions, This increase can be used for the number of I/O connections of a given size combination of one of the IC wafer and the lead frame. As can be seen from the illustrated embodiment, the use of metal traces on the leadframe 600 to provide the contact regions distally from the bonding regions can be configured to provide a plurality of rows of bonding regions and a plurality of rows of contact regions. In various embodiments, three or four rows of bonding regions may be partially etched into the leadframe and metal plating corresponding to five or more contact regions may be disposed on one of the bottom surfaces of the leadframe. For example, a 5x5 mm lead frame can be constructed to provide more than 100 I/O connections. As can be seen in the illustrated embodiment, various embodiments can utilize a combination of one of an outward routing and an inward routing.

Referring now to Figure 7, a flow diagram of one embodiment of an IC package fabrication process 700 is shown. The process begins with step 702 of providing a portion of the etched leadframe design criteria to a manufacturer. In various embodiments, at least a portion of the design criteria can be received via a customer order and/or can be developed by a manufacturer. The design criteria may include information about a final IC package and/or may include information about only a portion of the etched lead frame. For example, the design criteria can include the length, width, and height of a desired lead frame, the size of the IC wafer to be mounted on the lead frame, the number of bonding regions, the location of the bonding regions, the number of contact regions, Location of the contact area and/or other design criteria. At step 704, an unetched metal strip (such as, for example, a copper metal strip) is provided to a first location. At step 706, one of the top surfaces of the metal strip is partially etched using any number of etch procedures to create a pattern defining a recess above the metal trace on which the bond area is disposed. The pattern of the notches may correspond to the metal traces required to couple the bonding regions to the locations of the contact regions as may be provided in the design guidelines. In some embodiments, the etch may be half etched such that the notches formed in the leadframe extend halfway therebetween. For example, in a 4 mil leadframe, the half etch would be a 2 mil etch. In various embodiments, the leadframe can be etched more or less than half therebetween. For example, in some embodiments, the partial etch can be to a depth of about 3 mils +/- 0.5 mils. After the top surface is partially etched, one or both of the top and bottom surfaces of the lead frame may be selectively selected by, for example, plating the bonding regions and/or the locations at which the contact regions are to be disposed. Ground plating. The metallization of the bonding regions can be formed by applying an adhesive material to the metal traces. In various embodiments, a surface adhesion enhancement process ("AE treatment") can be performed after the metal plating, such as, for example, roughening and/or cleaning the surface to increase adhesion.

At step 708, the partially etched leadframe can be transported from the first location to a second location. In various embodiments, the partially etched leadframe provides stability to the metal traces during shipping. For example, in some embodiments, the first location can be a portion of a fabrication facility suitable for etching the top surface of the leadframe and the second location can be the same for the manufacturing facility suitable for completing the IC packaging process Or different parts. In some embodiments, the first location can be a first manufacturing facility and the second location can be a second manufacturing facility. In some embodiments, the first location can be a first manufacturing facility and the second location can be a customer location or other location. At step 710, an IC wafer is mounted on the partially etched leadframe. Next, after the IC wafer is wire bonded to the partially etched leadframe at step 712, the IC wafer is encapsulated at step 714. The process ends with etchback at the bottom of one of the strips at step 716.

Referring now to Figure 8, there is shown, for example, one of the metal strips 800 of the type that can be used in an IC package fabrication process. The metal strip 800 includes a plurality of device regions 801 disposed thereon. In some embodiments, the metal strip 800 can be copper or other metal or metal alloy and can have a thickness of 5 mils, greater than 5 mils, or less than 5 mils. In various embodiments, the size of the device regions 801 can vary and the number of device regions 801 on a metal strip 800 can also vary. For example, in some embodiments, the number of device regions 801 on a metal strip 800 can be any number from less than 100 to greater than 1000. One or more IC wafers may be attached to each device region 801 and encapsulated with an encapsulation compound during an IC fabrication process. In various embodiments, the IC chips can be electrically coupled to the device region 801 via wire bonding or directly electrically coupled into a flip chip configuration. The IC fabrication process can also include singulating the device regions 801 with each other to form a plurality of IC packages that can be configured to be mounted to an external device such as a PCB. When the IC packages are mounted on a PCB, the IC chips can be electrically coupled to the PCB via contact areas disposed on a bottom surface of one of the IC packages.

Although the various embodiments of the method and the system of the present invention have been described in the accompanying drawings and described in the foregoing embodiments, it is understood that the invention is not limited to the disclosed embodiments, but Some of the rearrangements, modifications, and substitutions are made in the spirit of the invention as set forth.

100. . . Unetched metal frame

104. . . IC chip

106. . . Contact area

108. . . Encapsulating compound

108a. . . Etched part

110. . . Adhesive material

114. . . Wire bonding

118. . . Joint area

122. . . Metal trace

122a. . . Etched portion of metal trace

126. . . Notch

129. . . Protective coating

200. . . Partially etched lead frame

206. . . Contact area

218. . . Joint area

222. . . Metal trace

226. . . Notch

300. . . Partially etched lead frame

304. . . IC chip

306. . . Contact area

318. . . Joint area

322. . . Metal trace

400. . . Partially etched and selectively plated leadframe

404. . . IC chip

406. . . Contact area

418. . . Joint area

422. . . Metal trace

426. . . Notch

500. . . Lead frame

504. . . IC chip

506. . . Contact area

518. . . Joint area

522. . . Metal trace

600. . . Partially etched lead frame

602. . . Die attach liner (DAP)

604. . . IC chip

622. . . Metal trace

622a. . . Metal trace

700. . . IC package manufacturing program

800. . . Metal strips

801. . . Device area

1A-1E illustrate aspects of an embodiment of a leadless IC package at various stages of a fabrication process;

2A-2B are two views of one embodiment of a metal lead frame forming one of a plurality of metal traces on a top surface;

3A-3B are a top view and a bottom view of an embodiment of a lead frame having two rows of bonding regions and a plurality of rows of contact regions;

4A-4B illustrate various aspects of an embodiment of a portion of an etched and selectively plated leadframe;

5 shows an illustrative embodiment of a partially etched leadframe having a plurality of metal traces having a coupling junction region to a contact region;

6A-6C illustrate top views of various embodiments of a partially etched leadframe for a leadless IC package;

Figure 7 is a flow diagram of one embodiment of a process for fabricating a portion of an etched leadframe; and

Figure 8 illustrates an embodiment of a leadframe strip for forming a plurality of partially etched leadframes.

100. . . Unetched metal frame

104. . . IC chip

106. . . Contact area

108. . . Encapsulating compound

108a. . . Etched part

110. . . Adhesive material

114. . . Wire bonding

118. . . Joint area

122. . . Metal trace

122a. . . Etched portion of metal trace

126. . . Notch

129. . . Protective coating

Claims (14)

A method of fabricating a leadframe for an integrated circuit (IC) package, the method comprising: receiving design criteria for a partially patterned leadframe for an IC package, the design criteria comprising a top surface to be disposed on the leadframe a first number of bonding regions and a second number of bonding regions to be disposed on a bottom surface of the lead frame; providing a metal strip having a top surface and a substantially flat bottom surface at the first location; etching the metal at the first location The top surface of the strip defines a plurality of joint regions equal to the number of joint regions from the design criteria and defines a plurality of metal trace upper portions, each metal trace extending from the top surface of the metal strip to the bottom surface and coupled One of the plurality of bonding regions to the bonding surface disposed on the bottom surface of the metal strip defines a region of a contact region; wherein at least one metal trace couples one of the plurality of bonding regions to the bonding region One contact area is disposed laterally distally below the region; the metal strip is transported from the first position to the second position before the IC chip is mounted on the metal strip The first position is a first manufacturing device, and the second position is a second manufacturing device disposed remotely from the first manufacturing device; and wherein the substantially flat bottom surface is integrally formed therewith during transport of the metal strip The metal traces provide support. The method of claim 1, wherein the second location is a location of a customer who sent the design criteria. The method of claim 1, comprising mounting the IC wafer to the top surface of the metal strip at the second location. The method of claim 3, wherein the IC chip is mounted on at least one metal trace, the at least one metal trace being coupled to a contact region under the IC wafer to a bonding region disposed at a periphery of the IC wafer. A method of fabricating a leadframe for an integrated circuit (IC) package, the method comprising: receiving design criteria for a partially patterned leadframe for an IC package, the design criteria comprising a top surface to be disposed on the leadframe a first pattern of locations of the plurality of bonding regions and a second pattern of locations of the plurality of contact regions to be disposed on a bottom surface of the lead frame; providing a top surface and a substantially flat bottom surface at the first location a metal strip; the top surface of the metal strip is etched at a first location to define a plurality of bonding regions at the location of the first pattern and to define an upper portion of the plurality of metal traces, the plurality of metal traces being coupled a position of the first pattern of the plurality of bonding regions on the top surface of the metal strip to a position of the second pattern of the plurality of contact regions on the bottom surface of the metal strip; applying a metal plating layer to the plurality of bonding regions a position of the first pattern and a position of the second pattern of the plurality of contact regions on the bottom surface of the metal strip; transporting the etched metal strip to a second position, A position to a first manufacturing device, and wherein the second location is a second manufacturing device remotely disposed from the first manufacturing device; and wherein at least one of the plurality of metal traces is electrically coupled to a laterally disposed bonding region of the contact region A line that is not perpendicular to the top surface of the metal strip intersects the bonding region and a contact region that is electrically coupled to the bonding region via the metal trace. The method of claim 5, comprising: cleaning the etched metal strip at the first location; and preparing the etched metal strip to be transported to the second location. The method of claim 6, wherein receiving the design criteria is combined with a customer order. The method of claim 5, comprising installing an IC chip on the top surface of the metal strip at the second location. The method of claim 5, comprising transporting the etched metal strip to a customer location transmitting the design criteria of the IC package to the first location. A method of fabricating a leadframe for an integrated circuit (IC) package, the method comprising: performing a first leadframe fabrication process at a first location, the first fabrication process comprising: providing a top surface and a substantially flat bottom surface a metal strip; a pattern defining an upper portion of the plurality of metal traces is etched into the top surface of the metal strip, each metal trace extending from the top surface of the metal strip to the bottom surface and having a top surface disposed thereon a joint area and a contact area disposed on a bottom surface thereof; and Applying a metal plating to each of the bonding regions to form a leadframe subassembly suitable for transport; transporting the leadframe subassembly from the first location to a second location, the first location being a first manufacturing device, and the a second location is a second manufacturing device remotely disposed from the first manufacturing device; and performing a second manufacturing process at the second location, the second manufacturing process comprising: mounting an IC chip on the top of the metal strip Electrically coupling the IC wafer to the plurality of bonding regions; encapsulating the IC wafer with an encapsulating compound; and etching the bottom surface of the lead frame to electrically isolate the metal traces from each other such that the plurality of metals At least one of the traces is electrically coupled to a laterally disposed junction region of the contact region, wherein no line perpendicular to the top surface of the metal strip and the junction region and a contact region electrically coupled to the junction region via the metal trace Intersect. The method of claim 10, wherein the first manufacturing process is performed at least in part by design criteria of the IC package. A method of fabricating a leadframe for an integrated circuit (IC) package, the method comprising: providing a metal strip having a top surface and a substantially flat bottom surface at a first location; defining a plurality of metal traces at the first location An upper pattern is etched into the top surface of the metal strip, each metal trace extending from the top surface of the metal strip to the bottom surface and having a bonding region disposed on the top surface thereof a contact region disposed on the bottom surface thereof; applying a metal plating pattern on the top surface and the bottom surface, the metal plating pattern covering each of the bonding regions and each contact region; facilitating transporting the etched metal strip to the second position The first location is a first manufacturing device, and the second location is a second manufacturing device remotely disposed from the first manufacturing device; wherein the metal is disposed between the plurality of metal traces When the remaining portion of the strip is etched away, the plurality of metal traces are electrically isolated from each other; and wherein at least one of the plurality of metal traces is electrically coupled to the laterally disposed joint region of the contact region such that there is no perpendicular to the A line of the top surface of the metal strip intersects the bonding region and a contact region electrically coupled to the bonding region via the metal trace. The method of claim 12, comprising: transporting the etched metal strip to a customer location transmitting the design criteria of the IC package to the first location. The method of claim 12, wherein the pattern is etched into the top surface of the metal strip based at least in part on the design criteria of the IC package.