TWI544491B - Shift register circuit - Google Patents

Description

Shift register circuit

The present invention relates to a shift register circuit, and more particularly to a shift register having a better charge and discharge capability.

The conventional shift register determines whether to output a gate driving signal according to one of the internal control signals, and outputs the gate driving signal in a period in which the shift register does not need to output the gate driving signal. And the control signal is stabilized at a low potential to prevent the shift register from outputting the gate drive signal at the wrong time to drive the wrong gate line. Therefore, how to correctly and quickly stabilize the output gate driving signal and the control signal at a low potential during the period in which the shift register does not need to output the gate driving signal, and reduce the internal components of the shift register due to process offset It is an important issue to cause malfunctions due to factors such as shifting or stress effects (Stress).

In order to prevent the output gate drive signal and the control signal from being stable at a low potential during the period in which the shift register does not need to output the gate drive signal, and reduce the internal offset of the shift register due to the process offset Or a situation in which a malfunction or the like causes a malfunction, and the present invention proposes an embodiment of a shift register circuit.

The shift register circuit embodiment proposed by the present invention includes a Pull-up control circuit, a pull-up circuit, a pull-down control circuit and a pull-down circuit, the pull-up control circuit is configured to receive a high voltage level, and determine whether to output the nth level according to the n-1th gate control signal Control signal; the pull-up circuit and the pull-up control circuit are electrically coupled to receive the high-frequency clock signal, and determine whether to output the n-th gate control signal according to the n-th control signal; the pull-down control circuit and the pull-up The control circuit and the pull-up circuit are electrically coupled to stabilize the nth control signal and the nth gate control signal at a low voltage level during the non-operation period; the pull-down circuit is electrically coupled to the pull-up circuit The system is configured to receive the nth gate control signal and determine whether to be electrically coupled to the pulldown control circuit according to the n+1th gate control signal.

The pull-down control circuit further includes: a first transistor having a first end, a second end, and a control end, wherein the first end of the first transistor and the control end of the first transistor are configured to receive the high frequency a second transistor having a first end, a second end, and a control end, wherein the first end of the second transistor is configured to receive a high frequency clock signal, and the control end of the second transistor The second end of the second transistor is electrically coupled to the second end of the second transistor for outputting the pull-down control signal; the third transistor has a first end, a second end, and a control end, and the third The first end of the crystal is electrically coupled to the second end of the first transistor, and the second end of the third transistor is electrically coupled to the low voltage level; a fourth transistor having a first end, a second end and a control end, the first end of the fourth transistor is electrically coupled to the second end of the second transistor, and the second end of the fourth transistor is electrically coupled to the low voltage level; a crystal having a first end, a second end, and a control end, wherein the first end of the fifth transistor is configured to receive the nth control signal, and the fifth The control end of the crystal is electrically coupled to the second end of the second transistor for receiving the pull-down control signal, the second end of the fifth transistor and the control end of the third transistor, and the control end of the fourth transistor And the pull-down circuit is electrically coupled; a sixth battery a crystal having a first end, a second end, and a control end, wherein the first end of the sixth transistor is electrically coupled to the second end of the fifth transistor, and the control end of the sixth transistor and the second transistor The second end is electrically coupled to receive the pull-down control signal, and the second end of the sixth transistor is electrically coupled to the low voltage level; a seventh transistor having a first end and a second end And a control terminal, the first end of the seventh transistor is configured to receive the nth gate control signal, and the control end of the seventh transistor is electrically coupled to the second end of the second transistor to receive the pulldown a control signal, the second end of the seventh transistor is electrically coupled to the low voltage level; an eighth transistor having a first end, a second end, and a control end, and the first end of the eighth transistor is used Receiving a high frequency clock signal, the control end of the eighth transistor is configured to receive the nth stage control signal, and the second end of the eighth transistor is electrically coupled to the second end of the fifth transistor; a nine-electrode having a first end, a second end, and a control end, wherein the first end of the ninth transistor is configured to receive the nth-level control signal A ninth electric control terminal for receiving the system crystal of the n + 1 stage gate control signal, a second terminal of the ninth transistor and the low voltage level is electrically coupled.

In the period in which the gate control signal is not required to be output, the control signal system is stabilized at a low voltage level by using two voltage stabilization methods, and the pull-down control circuit uses the clock signal to determine whether the output will be output. The gate drive signal and the control signal are stable at a low potential, so that the malfunction can be effectively reduced due to the process offset, and the pull-down circuit determines whether the gate drive signal is stabilized at the low voltage level according to the gate control signal. The embodiment of the shift register circuit of the invention can not only quickly and correctly stabilize the control signal at a low voltage level, but also greatly improve the circuit reliability and tolerance of the process offset error, and further reduce the pressure effect of the pull-down circuit. , thereby improving the use efficiency of the embodiment of the shift register of the present invention.

CK, CK1, CK2‧‧‧ high frequency clock signal

G(n-1)‧‧‧n-1th gate control signal

G(n)‧‧‧n-th gate control signal

Q(n)‧‧‧n level control signal

G(n+1)‧‧‧n+1th gate control signal

VGH‧‧‧high voltage level

VGL1‧‧‧ first low voltage level

VGL2‧‧‧ second low voltage level

C‧‧‧ capacitor

A‧‧‧ node

T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13‧‧‧ transistors

10‧‧‧ Pull-up control circuit

20‧‧‧ Pull-up circuit

30‧‧‧ Pulldown circuit

40‧‧‧ Pull-down control circuit

1 is a schematic diagram of an embodiment of a timing diagram of the present invention.

2 is a schematic diagram of an embodiment of a shift register of the present invention.

3 is a schematic diagram of another embodiment of a shift register of the present invention.

The embodiment of the present invention is described below with reference to FIG. 1 and FIG. 2. FIG. 1 is a timing diagram of an embodiment of the present invention, including a high frequency clock signal CK and an n-1th gate control signal G (n- 1), timing diagram of the nth gate control signal G(n), the n+1th gate control signal G(n+1), and the nth control signal Q(n). 2 is a first embodiment of the shift register of the present invention, which includes a pull-up control circuit 10, a pull-up circuit 20, a pull-down circuit 30, and a pull-down control circuit 40. The pull-up control circuit 10 is configured to output the n-th control signal Q(n), so that the pull-up circuit 20 can output the n-th gate control signal G(n) according to the n-th control signal Q(n), and pull down The circuit 30 and the pull-down control circuit 40 stabilize the n-th control signal Q(n) and the n-th gate control signal G(n) at a low voltage level during a period in which the gate control signal is not required to be output. To avoid driving the wrong gate line during the period when the gate control signal is not required, causing a malfunction.

The pull-up control circuit 10 includes a transistor T1. The transistor T1 includes a first end, a second end, and a control end. The first end of the transistor T1 is configured to receive a high voltage level VGH, and the transistor T1 The control terminal is configured to receive the n-1th gate control signal G(n-1), and the second end of the transistor T1 is used to output the nth control signal Q(n), that is, the transistor T1 is used. Whether to determine the received high voltage level according to the n-1th gate control signal G(n-1) The VGH output is the nth stage control signal Q(n).

The pull-up circuit 20 includes a transistor T2 and a capacitor C. The transistor T2 includes a first end, a second end, and a control end. The first end of the transistor T2 is configured to receive the high frequency clock signal CK. The control terminal of the transistor T2 is configured to receive the nth stage control signal Q(n), and the second end of the transistor T2 is used to output the nth stage gate control signal G(n), that is, the transistor T2 system. It is used to determine whether to output the received high frequency clock signal CK as the nth gate control signal G(n) according to the nth stage control signal Q(n). In addition, the capacitor C has a first end and a second end. The first end of the capacitor C is electrically coupled to the second end of the transistor T2, and the second end of the capacitor C is electrically coupled to the control end of the transistor T2. Capacitor C is used to compensate the nth gate control signal G(n) to the nth stage control signal Q(n).

The lower pull circuit 30 includes a transistor T3. The transistor T3 includes a first end, a second end, and a control end. The first end of the transistor T3 is electrically coupled to the second end of the transistor T2 for receiving. The nth gate control signal G(n), the control terminal of the transistor T3 is configured to receive the n+1th gate control signal G(n+1), and the second end of the transistor T3 For electrically connecting to the node A of the pull-down control circuit 40, that is, the transistor T3 is used to determine whether to connect the second end of the transistor T2 according to the n+1th gate control signal G(n+1). The node A of the pull-down control circuit 40 is electrically coupled.

The pull-down control circuit 40 includes a transistor T4. The transistor T4 includes a first end, a second end, and a control end. The first end of the transistor T4 is electrically coupled to the second end of the transistor T1. The n-th control signal Q(n), the control terminal of the transistor T4 is configured to receive the n+1th gate control signal G(n+1), and the second end of the transistor T4 is used to be the first low The voltage level VGL1 is electrically coupled, that is, the transistor T4 is used to be based on the n+1th gate The control signal G(n+1) is used to determine whether to pull the nth control signal Q(n) to the first low voltage level VGL1.

The pull-down control circuit 40 further includes a transistor T5. The transistor T5 includes a first end, a second end, and a control end. The first end and the control end of the transistor T5 are configured to receive the high frequency clock signal CK. That is, the transistor T5 is configured to determine whether to transmit the received high frequency clock signal CK to the second end of the transistor T5 according to the high frequency clock signal CK.

The pull-down control circuit 40 further includes a transistor T6. The transistor T6 includes a first end, a second end, and a control end. The first end of the transistor T6 is configured to receive the high-frequency clock signal CK, and the control end of the transistor T6. The system is electrically coupled to the second end of the transistor T5, that is, the transistor T6 is configured to determine whether to transmit the received high frequency clock signal CK to the power according to the voltage level of the second end of the transistor T5. The second end of the crystal T6 is output as a pull-down control signal.

The pull-down control circuit 40 further includes a transistor T7. The transistor T7 includes a first end, a second end, and a control end. The first end of the transistor T7 is configured to receive the high-frequency clock signal CK, and the control end of the transistor T7. The system is configured to receive the nth stage control signal Q(n), that is, the transistor T7 determines whether to be electrically coupled to the node A of the pull-down control circuit 40 according to the nth stage control signal Q(n).

The pull-down control circuit 40 further includes a transistor T8. The transistor T8 includes a first end, a second end, and a control end. The first end of the transistor T8 is configured to receive the voltage level of the second end of the transistor T5. The control terminal of the T8 is configured to receive the second terminal of the transistor T7, that is, the voltage level of the node A. The second end of the transistor T8 is electrically coupled to the first low voltage level VGL1, that is, the electricity. The crystal T8 is used to determine whether to pull down the voltage level of the second end of the transistor T5 to the first low voltage level VGL1 according to the voltage level of the second end of the transistor T7.

The pull-down control circuit 40 further includes a transistor T9. The transistor T9 includes a first end, a second end, and a control end. The first end of the transistor T9 is configured to receive the voltage level of the second end of the transistor T6. The control terminal of the T9 is configured to receive the voltage level of the second end of the transistor T7, and the second end of the transistor T9 is electrically coupled to the first low voltage level VGL1, that is, the transistor T9 is used. According to the voltage level of the second end of the transistor T7, it is determined whether the voltage level of the second end of the transistor T6 is pulled down to the first low voltage level VGL1.

The pull-down control circuit 40 further includes a transistor T10. The transistor T10 includes a first end, a second end, and a control end. The first end of the transistor T10 is configured to receive the n-th control signal Q(n), the transistor T10. The control terminal is configured to receive the voltage level of the second end of the transistor T6, that is, the pull-down control signal, and the second end of the transistor T10 is electrically coupled to the second end node A of the transistor T7, that is, The transistor T10 is configured to determine whether to be electrically coupled to the second end node A of the transistor T7 according to the voltage level of the second end of the transistor T6.

The pull-down control circuit 40 further includes a transistor T11. The transistor T11 includes a first end, a second end, and a control end. The first end of the transistor T11 is configured to receive the voltage level of the node A, and the control end of the transistor T11. The second end of the transistor T11 is electrically coupled to the first low voltage level VGL1, that is, the transistor T11 is used according to the transistor T6. The voltage level of the second terminal determines whether the voltage level of the node A is pulled down to the first low voltage level VGL1.

The pull-down control circuit 40 further includes a transistor T12. The transistor T12 includes a first end, a second end, and a control end. The first end of the transistor T12 is configured to receive the n-th gate control signal G(n). The control terminal of the crystal T12 is configured to receive the voltage level of the second end of the transistor T6, and the second end of the transistor T12 is electrically coupled to the second low voltage level VGL2, that is, the electro-crystal The body T12 is configured to determine whether to pull the nth gate control signal G(n) to the second low voltage level VGL2 according to the voltage level of the second end of the transistor T6, wherein the first low voltage level VG1 The voltage level is lower than the second low voltage level VGL2.

The operation of the embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

When the high-frequency clock signal CK is at a high voltage potential, as shown in FIG. 1 , CK1, at this time, since only the high-frequency clock signal CK is a high voltage potential, the control terminal receives the transistor T5 of the high-frequency clock signal CK. Actuated, the high frequency clock signal CK is thus transmitted to the second end of the transistor T5, so that the transistor T6 whose control terminal is electrically coupled to the second end of the transistor T5 is also actuated, and the high frequency clock signal is activated. The CK is thus transmitted to the second end of the transistor T6 and output as a pull-down control signal. The transistor T10, the transistor T11 and the transistor T12 of the second end of the control terminal electrically coupled to the transistor T6 are all actuated by the pull-down control signal. . The transistor T10 pulls down the nth control signal Q(n) to the voltage level of the node A, and the second end of the transistor T10 is electrically coupled to the first end of the transistor T11. The control signal Q(n) is again pulled down to the first low voltage level VG1 electrically coupled to the second end of the transistor T11 by the transistor T11, and the transistor T12 controls the nth gate at this time. The signal G(n) is pulled down to the second low voltage level VGL2, so the shift register embodiment stabilizes the nth stage control signal Q(n) at a low voltage level by means of two voltage stabilization methods. The n-level gate control signal G(n) is also maintained at a low voltage level by the transistor T12.

Then, when the n-1th gate control signal G(n-1) is at a high voltage potential, the transistor T1 that receives the n-1th gate control signal G(n-1) is actuated. Therefore, the high voltage level VGH received by the first end of the transistor T1 is transmitted to the second end of the transistor T1 and output as the nth level control signal. Q(n), the transistor T7 and the transistor T2 that the control terminal receives the nth stage control signal Q(n) are also activated at this time.

When the high frequency clock signal CK is again at a high voltage potential, as shown by the CK2 in FIG. 1, since the transistor T2 and the transistor T7 are still actuated by the nth stage control signal Q(n), the transistor T2 will receive The high frequency clock signal CK is transmitted to the second end of the transistor T2 and output as the nth gate control signal G(n), and the capacitor C is electrically coupled to the control terminal and the second end of the transistor T2. Therefore, the capacitor C compensates the nth gate control signal G(n) to the nth control signal Q(n) to increase the driving capability of the nth control signal Q(n), and further, the transistor The T7 transmits the received high frequency clock signal CK to the second end of the transistor T7, that is, the node A, so that the transistor T8 and the transistor T9 whose control terminal receives the voltage level of the second terminal of the transistor T7 are activated. The transistor T8 pulls the second end of the transistor T5 down to the first low voltage level VG1 electrically coupled to the second end of the transistor T8, and the transistor T9 pulls the second end of the transistor T6 down to the second stage of the transistor T9. The first low voltage level VG1 electrically coupled to the terminal is electrically coupled to the second end of the transistor T6 to receive the transistor T10 and the transistor T11 of the pull-down control signal. The crystal T12 remains off to prevent the transistor T10, the transistor T11, and the transistor T12 from being activated at the wrong time, resulting in the nth stage control signal Q(n) and the nth stage during the period in which the gate control signal is required to be output. The gate control signal G(n) is pulled down to the low voltage level, and a malfunction occurs.

Then, when the nth stage control signal Q(n) returns to a low voltage level, that is, a period in which the gate driving signal is not required to be output, and the n+1th gate control signal G(n+1) is a high voltage potential. When the control terminal receives the transistor T4 of the n+1th gate control signal G(n+1) and the transistor T3 is activated, the transistor T4 will receive the nth control signal Q received by the first terminal. (n) pull down to The second low end of the transistor T4 is electrically coupled to the first low voltage level VG1, and the transistor T3 pulls down the nth gate control signal G(n) received by the first end to the second end of the transistor T3. The voltage level of the node A electrically coupled, since the transistor T7 is turned off at this time, the node A is at a low voltage potential, thereby maintaining the nth gate control signal G(n) at a low voltage potential. So that the nth control signal Q(n) and the nth gate control signal G(n) are effectively stabilized at a low voltage level when the gate control signal is not required to be output, so as to prevent the wrong gate line from being driven. When the next high frequency clock signal CK, that is, the CK1 shown in Fig. 1, comes again, the above operation mode is repeated again to drive the correct gate line.

FIG. 3 is another embodiment of the shift register of the present invention, and FIG. 3 has the same operational principle as the components having the same component symbols in FIG. 2, and details are not described herein again. The difference between FIG. 3 and FIG. 2 is that the shift register embodiment of FIG. 3 further includes a transistor T13. The transistor T13 includes a first end, a second end, and a control end. The first end of the transistor T13 is used. The control terminal of the transistor T13 is configured to receive the n-1th gate control signal G(n-1), the transistor T13 The two ends are electrically coupled to the second low voltage level VGL2, that is, the transistor T13 determines whether to use the second end of the transistor T6 according to the n-1th gate control signal G(n-1). The voltage level is pulled down to the second low voltage level VGL2. Therefore, when the n-1th gate control signal G(n-1) is at a high voltage potential, in addition to the transistor T1 being enabled to output the nth control signal Q(n), in the present embodiment, The crystal T13 is also enabled by the n-1th gate control signal G(n-1) to stabilize the voltage level of the second terminal of the transistor T6 to a low voltage potential, that is, the transistor T13 is electrically coupled. The second low voltage level VGL2 is used to turn on the transistor T10, the transistor T11, and the transistor when a period of the gate driving signal is required to be output. The control terminal of the body T12 is stabilized at a low voltage potential to prevent the transistor T10, the transistor T11, and the transistor T12 from being activated during an erroneous period of time, resulting in the nth stage control signal Q(n) and the nth at the wrong time. The level gate control signal G(n) is pulled down to the low voltage level, and a malfunction occurs.

In view of the above, since the present invention does not require the output of the gate control signal, the control signal is stabilized at a lower low voltage level by using two voltage stabilization methods, and the pull-down control circuit is utilized. The pulse signal determines whether the output gate driving signal and the control signal are stabilized at a low potential level, and the pull-down circuit determines whether to stabilize the gate driving signal at a low voltage level according to the gate control signal, so the shift of the present invention The bit register circuit embodiment not only can quickly and correctly stabilize the control signal system at a low voltage level, but also directly shifts the high frequency clock signal or high voltage level to perform other pull-down control of the pull-down control. Compared with the device, the circuit reliability is greatly improved and the process offset error amount is tolerated, and the pressure effect of the pull-down circuit is effectively reduced, thereby effectively improving the use efficiency of the shift register embodiment of the present invention.

However, the above description is only for the preferred embodiment of the present invention, and the equivalent changes or modifications made by the scope of the present invention and the contents of the specification are still in the present invention. Within the scope of the invention patent.

CK‧‧‧ high frequency clock signal

G(n-1)‧‧‧n-1th gate control signal

G(n)‧‧‧n-th gate control signal

Q(n)‧‧‧n level control signal

G(n+1)‧‧‧n+1th gate control signal

VGH‧‧‧high voltage level

VGL1‧‧‧ first low voltage level

VGL2‧‧‧ second low voltage level

C‧‧‧ capacitor

A‧‧‧ node

T1, T2, T3, T4, T5, T6, T7, T8, T9, T10, T11, T12‧‧‧ transistors

10‧‧‧ Pull-up control circuit

20‧‧‧ Pull-up circuit

30‧‧‧ Pulldown circuit

40‧‧‧ Pull-down control circuit

Claims (6)

A shift register circuit includes: a pull-up control circuit for receiving a high voltage level, and determining whether to output an nth level control signal according to an n-1th gate control signal; The pull-up circuit is electrically coupled to the pull-up control circuit for receiving a high-frequency clock signal, and determining whether to output an n-th gate control signal according to the n-th control signal; and pulling the control circuit And electrically coupled to the pull-up control circuit and the pull-up circuit for stabilizing the n-th control signal and the nth-level gate control signal to a low voltage level during non-operation; The pull-up circuit is electrically coupled to the pull-up circuit for receiving the n-th gate control signal, and determining whether to be electrically coupled to the pull-down control circuit according to an n+1-th gate control signal; The pull-down control circuit further includes: a first transistor having a first end, a second end, and a control end, wherein the first end of the first transistor and the control end of the first transistor are configured to receive The high frequency clock signal; a second transistor having a first end, The second end of the second transistor is configured to receive the high frequency clock signal, and the control end of the second transistor is electrically coupled to the second end of the first transistor. The second end of the second transistor is configured to output a pull control signal; a third transistor has a first end, a second end, and a control end, the first end of the third transistor and the first end Second end of the crystal Coupling, the second end of the third transistor is electrically coupled to the low voltage level; a fourth transistor having a first end, a second end, and a control end, the first of the fourth transistors The second end is electrically coupled to the second end of the second transistor, and the second end of the fourth transistor is electrically coupled to the low voltage level; a fifth transistor having a first end and a second end The first end of the fifth transistor is configured to receive the nth stage control signal, and the control end of the fifth transistor is electrically coupled to the second end of the second transistor, Receiving the pull-down control signal, the second end of the fifth transistor is electrically coupled to the control end of the third transistor, the control end of the fourth transistor, and the pull-down circuit; a sixth transistor, The first end, the second end, and the control end, the first end of the sixth transistor is electrically coupled to the second end of the fifth transistor, and the control end of the sixth transistor and the second transistor The second end is electrically coupled to receive the pull-down control signal, and the second end of the sixth transistor is electrically coupled to the low voltage level; a seventh transistor having a first end, a second end, and a control end, wherein the first end of the seventh transistor is configured to receive the nth gate control signal, and the control end of the seventh transistor The second end of the second transistor is electrically coupled to receive the pull-down control signal, and the second end of the seventh transistor is electrically coupled to the low voltage level; an eighth transistor, The first end, the second end, and the control end, the first end of the eighth transistor is configured to receive the high frequency clock signal, and the control end of the eighth transistor is configured to receive the nth level control signal a second end of the eighth transistor and a second end of the fifth transistor And a ninth transistor having a first end, a second end, and a control end, wherein the first end of the ninth transistor is configured to receive the nth level control signal, and the ninth transistor is controlled The end is configured to receive the n+1th gate control signal, and the second end of the ninth transistor is electrically coupled to the low voltage level. The shift register circuit of claim 1, wherein the pull-down control circuit further comprises: a tenth transistor having a first end, a second end, and a control end, the first of the tenth transistor The terminal is electrically coupled to the second end of the second transistor, and the control end of the tenth transistor is configured to receive the n-1th gate control signal, and the second end of the tenth transistor The low voltage level is electrically coupled. The shift register circuit of claim 1, wherein the pull-up control circuit further comprises: an eleventh transistor having a first end, a second end, and a control end, the eleventh transistor The first end is configured to receive the high voltage level, and the control end of the eleventh transistor is configured to receive the n-1th gate control signal, and the second end of the eleventh transistor is used for outputting The nth level control signal. The shift register circuit of claim 1, wherein the pull-up circuit further comprises: a twelfth transistor having a first end, a second end, and a control end, The first end of the twelfth transistor is configured to receive the high frequency clock signal, and the control end of the twelfth transistor is configured to receive the nth level control signal, the second of the twelfth transistor The end is configured to output the nth gate control signal; and a capacitor, the first end of which is electrically coupled to the second end of the twelfth transistor, and the second end and the twelfth transistor The control terminal is electrically coupled. The shift register circuit of claim 1, wherein the pull-down circuit further comprises: a thirteenth transistor having a first end, a second end, and a control end, the thirteenth transistor One end is configured to receive the nth gate control signal, and the control end of the thirteenth transistor is configured to receive the n+1th gate control signal, and the second end of the thirteenth transistor And electrically coupled to the second end of the fifth transistor. The shift register circuit of claim 1, wherein the low voltage level further comprises a first low voltage level and a second low voltage level.