TWI439034B - Zero voltage switching power converter - Google Patents

Description

Zero voltage switching power converter

The present invention relates to a converter, and more particularly to a zero voltage switching power converter.

In the paper "BR Lin and HK Chiang, "Analysis and Implementation of a Soft Switching Interleaved Forward Converter with Current Double Rectifier," IET Electr. Power Appl., Vol. 1, No. 5, pp. 697-704, 2007." A conventional power converter is proposed.

However, the disadvantages of conventional power converters are:

1. The switching stress used is v _in /1-D, where v _in is the input voltage and D is the power switch duty ratio. When D = 0.5, the switching stress is 2v _in , which is not suitable for high input voltage applications.

2. Use four switches to increase hardware cost.

Accordingly, it is an object of the present invention to provide a zero voltage switching power converter that reduces switching stress.

The zero voltage switching power converter comprises: a first voltage dividing capacitor having a first end of a positive pole receiving an input voltage, and a second end; a second voltage dividing capacitor having an electrical connection to the first a first end of the second end of the voltage dividing capacitor, and a second end of the negative terminal receiving the input voltage; a first switch having a first end electrically connected to the first end of the first voltage dividing capacitor, And a second end, wherein the first switch is controlled to switch between a conducting state and a non-conducting state; a second switch having a first end and a second end electrically connected to the second voltage dividing capacitor a second end, and the second switch is controlled to switch between a conducting state and a non-conducting state; a bypass diode having an anode electrically connected to the first end of the second switch and an electrical connection to the first a cathode of a second end of the switch; first and second transformers, each transformer having a primary side winding and a secondary side winding, and each side inductor has a first end and a second end, wherein The first end of the primary side winding of the first transformer is electrically connected a first end of the first switch, a first end of the primary side winding of the second transformer is electrically connected to a second end of the primary side winding of the first transformer, and a second end of the primary side winding of the second transformer is electrically Connected to the first end of the second switch, the second end of the secondary side winding of the second transformer is electrically connected to the second end of the secondary side winding of the first transformer; a resonant inductor electrically connected to the first end a second terminal of the voltage dividing capacitor and a second end of the primary side winding of the first transformer; a first diode having a first end electrically connected to the secondary side winding of the first transformer An anode, and a cathode; a second diode having an anode electrically connected to the first end of the secondary winding of the second transformer, and a cathode; and a third diode having an electrical connection An anode of the second end of the secondary side winding of the first transformer, and a cathode electrically connected to the cathode of the first diode; a fourth diode having a secondary electrically connected to the first transformer An anode of the second end of the side winding, and an electrical connection to the second diode a cathode of the cathode; a first output inductor having a first end electrically connected to the cathode of the first diode; and a second end; a second output inductor having an electrical connection to the second diode a first end of the cathode of the body, and a second end; and an output capacitor electrically connected between the second end of the first output inductor and the second end of the secondary side winding of the first transformer Provide an output voltage.

The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments.

As shown in FIG. 1, a preferred embodiment of the zero voltage switching power converter of the present invention comprises: first and second voltage dividing capacitors C ₁ , C ₂ , first and second switches Q ₁ , Q ₂ , and a bypass a diode D _P , a resonant inductor L _r , first and second transformers T ₁ , T ₂ , first to fourth diodes D ₁ to D ₄ , first and second output inductors L ₁ , L ₂ , And an output capacitor C _O .

The first voltage dividing capacitor C ₁ has a first end of a positive pole receiving an input voltage v _in and a second end.

The second voltage dividing capacitor C ₂ has a first end electrically connected to the second end of the first voltage dividing capacitor C ₁ and a second end receiving the negative voltage of the input voltage v _in .

Having a first switch Q ₁ is electrically connected to the first voltage divider terminal of the first capacitor C _1, a first end and a second end, the first switch Q ₁ and controlled to switch to a conducting state and a nonconducting Between states.

The second switch Q ₂ has a first end, and a second end electrically connected to the second end of the second voltage dividing capacitor C ₂ , and the second switch Q ₂ is controlled to be switched between a conducting state and a non-conducting state. between.

The two switches Q ₁ and Q _{2 are} all N-type power semiconductor transistors and are substantially in conduction, and the two switches Q ₁ , Q ₂ have no overlap during the on period, and the two switches Q ₁ , Q ₂ The first end is a drain, and the second ends of the two switches Q ₁ and Q ₂ are sources.

The bypass diode D _P has an anode electrically connected to the first end of the second switch Q ₂ and a cathode electrically connected to the second end of the first switch Q ₁ .

The first and second transformers T ₁ , T ₂ have a primary side winding L _P1 and a secondary side winding L _P2 , and each of the side windings L _P1 , L _P2 has a first end and a second end, wherein The turns ratio of the two windings L _P1 and L _P2 is N ₁ :N ₂ , and in this embodiment, the first end is a polarity point end, and the second end is a non-polar point end. Here, the magnetizing inductance and the leakage inductance of the two transformers T ₁ and T ₂ are not indicated in FIG. 1 and will be described later.

The first end of the primary side winding L _P1 of the first transformer T ₁ is electrically connected to the first end of the first switch Q ₁ .

The first end of the primary side winding L _P1 of the second transformer T ₂ is electrically connected to the second end of the primary side winding L _P1 of the first transformer T ₁ . The second end of the primary side winding L _P1 of the second transformer T ₂ is electrically connected to the second end of the second switch Q ₂ . Second end of the second transformer T ₂ of the secondary side winding L _P2 is connected to the second terminal of the secondary winding L _P2 of the first transformer T _1.

The resonant inductor L _{r is} electrically connected between the second end of the first voltage dividing capacitor C _{1 and} the second end of the primary side winding L _P1 of the first transformer T ₁ .

The first diode D ₁ has an anode electrically connected to the first end of the secondary side winding L _P2 of the first transformer T ₁ , and a cathode.

The second diode D ₂ has an anode electrically connected to the first end of the secondary side winding L _P2 of the second transformer T ₂ , and a cathode.

The third diode D ₃ has an anode electrically connected to the second end of the secondary side winding L _P2 of the first transformer T ₁ and a cathode electrically connected to the cathode of the first diode D ₁ .

The fourth diode D ₄ has an anode electrically connected to the second end of the secondary side winding L _P2 of the first transformer T ₁ and a cathode electrically connected to the cathode of the second diode D ₂ .

The first output inductor L ₁ has a first end electrically connected to the cathode of the first diode D ₁ and a second end.

The second output inductor L ₂ has a first end electrically connected to the cathode of the second diode D ₂ and a second end.

An output capacitor C _{O is} electrically connected between the second end of the first output inductor L _{1 and} the second end of the secondary side winding L _P2 of the first transformer T ₁ for providing an output voltage v _o to a load .

Referring to FIG. 2, it is an operation timing diagram of the embodiment, wherein the parameters v _g1 and v _g2 respectively represent voltages for controlling whether the first and second switches Q ₁ and Q ₂ are turned on, and the parameters v _Cr1 and v _Cr2 respectively represent the The voltages of the parasitic capacitances C _r1 and C _r2 of the first and second switches Q ₁ and Q ₂ , the parameters i _Lm1 and i _Lm2 respectively represent the magnetizing inductances L _m1 and L _m2 flowing through the two transformers T ₁ and T ₂ . Current, the parameter i _Lr represents the current flowing through the resonant inductor L _r , and the parameters i _D1 ～ i _D4 represent the current flowing through the first to fourth diodes D ₁ to D ₄ , respectively, and the parameters i _L1 and i _L2 respectively represent output current of the first inductor of L ₁ flows, flows through the second inductor L current output, the parameter i represents _{2 Lo} total output current. According to the switching of the two switches Q ₁ and Q ₂ , the present embodiment operates in ten modes, and in the following modes, the magnetizing inductances L _m1 and L _{m2 of} the two transformers T ₁ and T ₂ are drawn in the drawing. And the leakage inductances L _l1 , L _l2 , and the turned-on components are indicated by solid lines, and the non-conducting components are indicated by dashed lines. The following descriptions are respectively for each mode and the duty-switching period D of the two switches Q ₁ and Q _{2 is made} . <0.5.

And the following analysis, the assumptions are:

1. The first and second transformers T ₁ and T ₂ have equal turns ratios and equal magnetization inductance values (L _m1 = L _m2 = L _m ), and the leakage inductance is equal to L _{l 1} = L _{l 2} = L _l .

2. The magnetizing inductance L _{m is} much larger than the resonant inductor L _r and the leakage inductance L _l , that is, L _m >>L _r , L _m >>L _l .

3. The capacitance values of the first and second voltage dividing capacitors C ₁ and C ₂ are much larger than the parasitic capacitances C _r1 and C _{r2 of the} first and second switches Q ₁ and Q ₂ .

4. The inductance values of the first and second output inductors L ₁ and L ₂ are equal, that is, L ₁ = L ₂ .

5. The output capacitor C _{O is} large, and the output voltage v _o can be regarded as a constant.

6. Operate in continuous conduction mode (CCM).

7. The energy stored in the resonant inductor L _r and the leakage inductances L _l1 , L _l2 is greater than the energy of the parasitic capacitances C _{r 1} , C _{r 2} to achieve a zero voltage switching (ZVS) operation.

Mode one (time: t ₀ ~ t ₁ ):

Referring to Figures 2 and 3a, the first switch Q _{1 is} turned on and the second switch Q ₂ is turned off.

The first switch Q _{1 is} in an on state, so that the energy stored in the voltage dividing capacitor C ₁ is transmitted to the load through the transformer T ₁ , and the detailed operation is that the current i _{Lm 1} flowing through the first input inductor L _m1 linearly rises, and _a first switch voltage across the second end Q v _{Cr 1} = 0, and thus the first primary winding of transformer T ₁ L _P1 approximates a first voltage across the voltage dividing capacitor C ₁ v _{P 1} v _{C 1>} 0, and an induced voltage _{v S 1 = nv C 1>} 0 so that the first diode D is turned _{on. 1} T ₁ of the first transformer secondary winding L _P2, a third diode D _{3 is} non-conducting, and the voltage v _{L 1} = v _{S 1} - v _o >0 of the magnetizing inductance L _m1 , the current i _{L 1} linearly rises, and the slope is v _{C 1} / L _m .

The second switch Q _{2 is} in a non-conducting state, so its cross voltage is equivalent to the input voltage v _{Cr 2} = v _in , the second transformer T ₂ is magnetically reset via the bypass diode D _P , and the second transformer T ₂ Primary side winding L _P1 across pressure v _{P 2} - v _{P 1} <0, leaving the second diode D ₂ non-conducting, the fourth diode D ₄ conducting, the voltage of the second output inductor L ₂ v _{L 2} =− V _o , and the second output inductance L the current i _{2 L 2} decreases linearly, and therefore the total output current _{i L o = i L 1 +} i L 2 will ripple cancellation effect.

Mode 2 (time: t ₁ ~ t ₂ ):

Referring to FIG. 2 and FIG. 3b, the first and second switches Q ₁ and Q ₂ are not turned on.

A first dividing capacitor _{C. 1} i _{Q 1} provides a current to charge the first parasitic capacitance C of the switch Q _{1 r 1,} v _{Cr 1} so that the voltage rises, since the bypass diode D _P turned on, and the voltage v _{Cr 1} v _{Cr 2} satisfies v _{Cr 1} + v _{Cr 2} = v _in , so the parasitic capacitance C _{r2 of the} second switch Q ₂ is discharged, causing the voltage v _{Cr 2 to} decrease. Since the parasitic capacitances C _{r 1} and C _{r 2 of the} first and second switches Q ₁ , Q ₂ are very small, v _{Cr 1} rises and v _{Cr 2} drops very fast, so this phase is very short, the first input inductor L _m1 The current i _Lm1 can be regarded as a constant At the same time, i ₁ =ni _L1 , so the parasitic capacitance C _{r1 of} the first switch Q ₁ is rapidly charged by the current i _Q1 .

When v _Cr1 rises to v _C1 , v _Cr2 falls to v _C2 , the voltage of the primary side winding L _P1 of the first transformer T ₁ is v _P1 = 0 , and the voltage of the secondary side winding L _P2 of the second transformer T ₂ is v _P2 = 0 , so v _S1 = 0 and v _S2 = 0 , enter mode three.

Mode three (time: t ₂ ~ t ₃ ):

Referring to FIG. 2 and FIG. 3c, the first and second switches Q ₁ and Q ₂ are not turned on.

The resonant inductor L _r , the first and second leakage inductances L _l1 and L _l2 , the parasitic capacitances C _{r 1} and C _{r2 of the} first and second switches Q ₁ , Q ₂ form a resonant circuit, and the first switch Q ₁ crosses the voltage v _{Cr 1} continues to rise, the second switch Q ₂ continues to fall across the voltage v _Cr2 , the resonant inductor L _r across the negative voltage, the current i _Lr decreases, and the current i _D1 flowing through the first diode D ₁ decreases, flowing through The current i _{D3 of the} third diode D ₃ is incremented, the current i _D2 flowing through the second diode D ₂ is incremented, and the current i _D4 flowing through the fourth diode D ₄ is decreased.

In mode three resonant inductor L _r and the leakage inductance L _L1, L _l2 initial stored energy must be greater than the initial energy storage of the second switch Q _2, a parasitic capacitance C _r2, the second switch Q ₂ can the cross voltage drop v _Cr2 To zero, reach the conditions of ZVS.

When the second switch Q ₂ falls to 0 across the voltage v _Cr2 , the body diode D _{Q2 of the} second switch Q ₂ is turned on, and the mode 3 ends.

Mode four (time: t ₃ ~ t ₄ ):

Referring to FIGS. 2 and 3d, the first and second switches Q ₁ and Q ₂ are not turned on.

When Mode 4 starts, the voltage across the second switch Q ₂ v _Cr2 clamped to zero and v _Cr1 = v _in, and the second switch Q ₂ of the body diode D _Q2 is turned on, the second switch Q ₂ of the voltage across the To zero, before current i _Q2 becomes positive, Q ₂ must be switched to conduct, achieve ZVS operation, and proceed to mode five.

Mode five (time: t ₄ ~ t ₅ ):

Referring to FIG. 2 and FIG. 3E, a first switch Q ₁ is not turned on, the second switch Q ₂ is turned on.

Mode 5 circuit operation is the same as mode 4, so it will not be repeated.

When the current i _{D3 of the} third diode D ₃ rises to i _L1 , the current i _{D2 of the} second diode D ₂ rises to i _L2 , the commutation is completed, and the first and fourth diodes D ₁ and D simultaneously ₄ turns into a cutoff, and mode five ends.

Mode six (time: t ₅ ~ t ₆ ):

Referring to FIG. 2 and FIG. 3f, the first switch Q ₁ is not turned on, the second switch Q ₂ is turned on.

The third diode current i _D3 =i _L1 , the second diode current i _D2 =i _L2 , the voltage of the second input inductor v _P2 v _C2 , whose current i _Lm2 rises linearly and has a slope of v _C2 /L _m , and the voltage of the secondary side winding L _P2 of the second transformer T ₂ is v _S2 =nv _P2 > 0 , and is stored in the second voltage dividing capacitor C at this time ₂ by the energy of the second transformer T ₂ is transmitted to the output load. And the first transformer T ₁ is flux resetted via the bypass diode D _P , and v _P1 =−v _P2 , so the current i _{Lm 1} linearly decreases. In terms of output inductor current, since v _L2 =v _S2 -v _o >0, i _{L 2} rises linearly; v _L1 =-v _o , i _L1 decreases linearly, so the total output current i _Lo =i _L1 +i _L2 will The effect of chopping cancellation.

Mode seven (time: t ₆ ~ t ₇ ):

Referring to FIG. 2 and FIG. 3g, the first and second switches Q ₁ and Q ₂ are not turned on.

The current i _Q2 is positive and charges the parasitic capacitance C _r2 of the second switch Q _{2 to} increase the voltage v _Cr2 . Since the bypass diode D _{P is} turned on, the voltages v _Cr1 and v _Cr2 satisfy v _in =v _Cr1 +v _Cr2 , so the parasitic capacitance C _{r1 of the} first switch Q ₁ is discharged, and the voltage v _{Cr 1 thereof is} lowered. Since the parasitic capacitances C _r1 and C _{r2 of the} first and second switches Q ₁ , Q ₂ are very small, v _Cr2 rises and v _Cr1 drops very fast, so the time of mode seven is very short.

When the second switch Q ₂ rises to v _C2 across the voltage v _Cr2 , at which time v _Cr1 drops to v _C1 , the voltage v _P2 of the primary side winding L _P1 of the second transformer T ₂ =0, and the primary of the first transformer T ₁ The voltage v _P1 =0 of the side winding L _P1 causes the first and fourth diodes D ₁ and D _{2 to} start to conduct, and this stage ends.

Mode eight (time: t ₇ ~ t ₈ ):

Referring to FIG. 2 and FIG. 3h, the first and second switches Q ₁ and Q ₂ are not turned on.

The voltages v _P1 and v _P2 of the primary side windings of the first and second transformers T ₁ , T ₂ are clamped at zero, and i _Lm1 and i _Lm2 remain constant. The resonant inductor L _r , the leakage inductances L _l1 and L _{l2 ,} and the parasitic capacitances C _r1 and C _{r2 of the} first and second switches form a resonant circuit, v _Cr2 continues to rise, and v _Cr1 continues to decrease. The resonant inductor crosses a positive voltage and its current i _Lr rises. The current i _{D1 is} incremented, i _{D3 is} decremented, while i _{D2 is} decremented and i _{D4 is} incremented. And the initial energy storage of the resonant inductor and the leakage inductance must be greater than the initial energy storage of the parasitic capacitance C _r1 of the first switch Q ₁ , so that the first switch across the voltage v _Cr1 drops to zero, reaching the condition of ZVS.

When the first switching voltage v _Cr1 drops to zero, its body diode D _{Q1 is} turned on, and proceeds to mode IX.

Mode nine (time: t ₈ ~ t ₉ ):

Referring to FIG. 2 and FIG. 3i, the first and second switches Q ₁ and Q ₂ are not turned on.

A current flowing through the first switch Q ₁ of the body diode D _Q1, the first switch Q ₁ of voltage across zero, and the voltage across the second switch Q v ₂ of _Cr2 = v _in. Since v _Cr1 =0, before the first switching current i _Q1 becomes a positive value, the first switch Q ₁ must be switched to be turned on to achieve a ZVS operation. Further, the resonant inductor voltage v _Lr = v _C1 L _r / (L _r + 0.5L ₁ ), and the resonant inductor current i _Lr rises linearly.

When the first switch Q ₁ is turned on when switching to reach ZVS operation, the end of the nine modes.

Mode ten (time: t ₉ ~ t ₁₀ ):

Referring to FIG. 2 and FIG. 3i, a first switch Q ₁ turns on, and the second switch Q ₂ is not turned on.

Mode 10 circuit operation is the same as mode 9.

When the first diode current i _D1 rises to i _L1 , the fourth diode current i _D4 rises to i _L2 , the commutation is completed, and the second and third diodes D ₂ and D _{3 are} turned off, mode ten End.

theoretical analysis

It can be seen from the above that L _m >>L _r , L _m >>L ₁ , and the first switch Q _{1 is} turned on and the second switch Q ₂ is turned off, v _P1 v _C1 ; when the first switch Q ₁ is non-conducting and the second switch Q ₂ is conducting, v _{P 1} = - v _{C 2} . According to the volt-second equilibrium theorem,

Dv _C1 +(1-D)(-v _C2 )=0 (1)

Wherein the first switch Q _{1 has} a duty ratio D , and because

v _{C 1} + v _{C 2} = v _in (2)

Can be introduced by formula (1) (2)

v _C1 =(1-D)v _in ,v _C2 =Dv _in (3)

Let n=N ₂ /N ₁ , the voltage conversion ratio is analyzed as follows. When the first switch Q ₁ is turned on and the second switch Q ₂ is non-conductive, the voltage of the first output inductor L ₁ is as shown in the formula (4):

v _L1 =nv _C1 -v _o =n(1-D)v _in -v _o (4)

When the first switch Q ₁ is non-conducting and the second switch Q ₂ is conducting, the voltage of the first output inductor L ₁ is as shown in the formula (5):

v _L1 =-v _o (5)

At steady state, the first output inductor L ₁ satisfies the volt-second equilibrium theorem. therefore

D[n(1-D)v _in -v _o ]+(1-D)(-v _o )=0 (6)

Available voltage conversion ratio

It can be seen from equation (7) that the maximum voltage conversion ratio is when the switch conduction ratio D=0.5.

Experimental simulation

After seen from FIG. 4, when v _in = 400 V, the voltage across the first switch Q v _{Q1, ds} of ₁ has fallen to zero, the drive signal v _g1 was switched on to achieve ZVS performance, while the second switch Q ₂ After the voltage across the voltage v _{Q2, ds} drops to zero, the drive signal v _g2 is switched to conduct to achieve ZVS performance. It can be seen from the figure that the voltage stress is v _in , and the simulation result is consistent with the low voltage stress of the first and second switches Q ₁ and Q ₂ .

Figure 5 shows the waveform measurement of the output inductor currents i _L1 , i _L2 , i _Lo . From the analog waveform, it can be seen that under steady-state operation, the inversion of i _L1 and i _L2 chopping does reduce the chopping Δi _Lo much. (Δi _L1 Δi _L2 2.7A→Δi _Lo 0.4A), a smaller output filter capacitor can be used to reduce the converter size and increase the power density. In addition, I _L1 =I _L2 =10A does share the total output current (20 A), disperses the power loss and thermal stress of the magnetic element, and has high output current and low output current chopping performance.

6 is a current simulation diagram of the diodes D ₁ -D ₄ . It can be seen from the figure that when the first switch Q ₁ is turned on, the first diode D ₁ is turned off, and the third diode D _{3 is} turned on. When the first switch Q ₁ is non-conducting, when the second switch Q ₂ is turned on, the diode D _{1 is} turned on, and the diode D _{3 is} turned off. with When the second switch Q ₂ is turned on, the second diode D _{2 is} turned on, the fourth diode D ₄ is turned off, and when the second switch Q ₂ is non-conductive, the first switch Q ₁ is turned on. When the second diode D _{2 is} turned off, the fourth diode D _{4 is} turned on, and the diode currents i _D2 and i _{D4 are} commutated at this stage. =i _o /2=10A

In summary, the above embodiment has the following advantages:

1. Each switch Q ₁ , Q ₂ has a lower voltage stress, and its switching stress is equivalent to the input voltage v _in , which is suitable for high input voltage applications.

2. Only two switches Q ₁ and Q _{2 are included} , which can reduce the hardware cost.

3. The first and second switches Q ₁ and Q ₂ can achieve zero voltage switching (ZVS) operation, reduce switching losses, and improve power conversion efficiency.

4. Because the parallel output structure has a current sharing function, which can reduce the power loss and thermal stress of the magnetic component, it is suitable for high output current applications.

5. With output current chopping cancellation, it has low output current ripple.

The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.

C ₁ . . . First voltage dividing capacitor

C ₂ . . . Second voltage dividing capacitor

Q ₁ . . . First switch

Q ₂ . . . Second switch

D _p . . . Bypass diode

L _r . . . Resonance inductor

T ₁ . . . First transformer

T ₂ . . . Second transformer

L _P1 . . . Primary side winding

L _P2 . . . Secondary side winding

D ₁ ~ D ₄ . . . First to fourth diodes

L ₁ . . . First output inductor

L ₂ . . . Second output inductor

C _O . . . Output capacitor

v _in . . . Input voltage

v _o . . . . The output voltage

L _m1 ~ L _m2 . . . Magnetizing inductance

L _l1 ~ L _l2 . . . Leakage inductance

C _r1 ~C _r2 . . . Parasitic capacitance

D _Q1 ~ D _Q2 . . . Body diode

1 is a circuit diagram of a preferred embodiment of a zero voltage switching power converter of the present invention;

Figure 2 is a timing diagram of the preferred embodiment;

Figure 3a is a circuit diagram of the preferred embodiment in mode one;

Figure 3b is a circuit diagram of the preferred embodiment in mode two;

Figure 3c is a circuit diagram of the preferred embodiment in mode three;

Figure 3d is a circuit diagram of the preferred embodiment in mode four;

Figure 3e is a circuit diagram of the preferred embodiment in mode five;

Figure 3f is a circuit diagram of the preferred embodiment in mode six;

Figure 3g is a circuit diagram of the preferred embodiment in mode seven;

Figure 3h is a circuit diagram of the preferred embodiment in mode eight;

Figure 3i is a circuit diagram of the preferred embodiment in mode IX;

Figure 3j is a circuit diagram of the preferred embodiment in mode ten;

Figure 4 is a first simulation diagram of the preferred embodiment;

Figure 5 is a second simulation diagram of the preferred embodiment; and

Figure 6 is a third simulation of the preferred embodiment.

C ₁ . . . First voltage dividing capacitor

C ₂ . . . Second voltage dividing capacitor

Q ₁ . . . First switch

Q ₂ . . . Second switch

D _P . . . Bypass diode

L _r . . . Resonance inductor

T ₁ . . . First transformer

T ₂ . . . Second transformer

L _P1 . . . Primary side winding

L _P2 . . . Secondary side winding

D ₁ ~ D ₄ . . . First to fourth diodes

L ₁ . . . First output inductor

L ₂ . . . Second output inductor

C _O . . . Output capacitor

v _in . . . Input voltage

v _o . . . The output voltage

Claims (8)

A zero voltage switching power converter includes: a first voltage dividing capacitor having a first end of a positive pole receiving an input voltage, and a second end; a second voltage dividing capacitor having an electrical connection to the first a first end of the second end of the voltage dividing capacitor, and a second end of the negative terminal receiving the input voltage; a first switch having a first end electrically connected to the first end of the first voltage dividing capacitor, And a second end, wherein the first switch is controlled to switch between a conducting state and a non-conducting state; a second switch having a first end and a second end electrically connected to the second voltage dividing capacitor a second end, and the second switch is controlled to switch between a conducting state and a non-conducting state; a bypass diode having an anode electrically connected to the first end of the second switch and an electrical connection to the first a cathode of a second end of the switch; first and second transformers, each transformer having a primary side winding and a secondary side winding, and each side inductor has a first end and a second end, wherein The first end of the primary side winding of the first transformer is electrically connected At a first end of the first switch, a first end of the primary side winding of the second transformer is electrically coupled to a second end of the primary side winding of the first transformer, and a second end of the primary side winding of the second transformer Electrically connected to the first end of the second switch, the second end of the secondary side winding of the second transformer is electrically connected to the second end of the secondary side winding of the first transformer; a resonant inductor electrically connected to the a second end of the first voltage dividing capacitor and a second end of the primary side winding of the first transformer; a first diode having a first end electrically connected to the secondary side winding of the first transformer An anode, and a cathode; a second diode having an anode electrically connected to the first end of the secondary winding of the second transformer, and a cathode; and a third diode having an electrical connection An anode at a second end of the secondary side winding of the first transformer, and a cathode electrically connected to a cathode of the first diode; a fourth diode having a second electrical connection to the first transformer An anode of the second end of the stage side winding, and an electrical connection to the second pole a cathode of the cathode; a first output inductor having a first end electrically connected to the cathode of the first diode; and a second end; a second output inductor having an electrical connection to the second a first end of the cathode of the pole body, and a second end; and an output capacitor electrically connected between the second end of the first output inductor and the second end of the secondary side winding of the first transformer To provide an output voltage. The zero voltage switching power converter of claim 1, wherein the first and second transformers have equal turns ratios. The zero voltage switching power converter of claim 1, wherein the first end of each secondary side winding is a polarity point end, and the second end of each secondary side winding is a non-polar point end. The zero voltage switching power converter of claim 1, wherein the first end of each primary side winding is a polarity point end, and the second end of each primary side winding is a non-polar point end. The zero-voltage switching power converter of claim 1, wherein the first switch is an N-type power semiconductor transistor, and the first end of the first switch is a drain, the first switch The second end is the source. The zero voltage switching power converter of claim 1, wherein the second switch is an N-type power semiconductor transistor, and the first end of the second switch is a drain, the second switch The second end is the source. The zero-voltage switching power converter of claim 1, wherein the first and second switches are not overlapped during the on period. The zero-voltage switching power converter of claim 1, wherein the first and second output inductors have equal inductance values.