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TWI436587B - Bleeding circuit and method for power reduction of an emi filter - Google Patents

Bleeding circuit and method for power reduction of an emi filter Download PDF

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Publication number
TWI436587B
TWI436587B TW99113533A TW99113533A TWI436587B TW I436587 B TWI436587 B TW I436587B TW 99113533 A TW99113533 A TW 99113533A TW 99113533 A TW99113533 A TW 99113533A TW I436587 B TWI436587 B TW I436587B
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Taiwan
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bleeder
full
circuit
bleed
wave signal
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TW99113533A
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Chinese (zh)
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TW201138302A (en
Inventor
Jung Pei Cheng
Yu Ming Chen
Tzu Chen Lin
Pei Lun Huang
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Richpower Microelectronics
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Publication of TWI436587B publication Critical patent/TWI436587B/en

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Description

減少電磁干擾濾波器之功率消耗的洩放電路及方法Venting circuit and method for reducing power consumption of electromagnetic interference filter

本發明係有關一種電磁干擾(Electro-Magnetic Interference;EMI)濾波器,特別是關於一種減少電磁干擾濾波器之功率消耗的洩放電路及方法。The present invention relates to an Electro-Magnetic Interference (EMI) filter, and more particularly to a bleeder circuit and method for reducing the power consumption of an EMI filter.

近年來,因能源危機及環保概念抬頭,歐盟、北美及日本等區域紛紛對電子設備訂定相關綠色環保法規,除規定電子設備的轉換效率外,亦對空載待機能耗提出嚴格要求。如圖1所示,應用在電源供應設備的電磁干擾濾波器12,為了防止電源插頭拔除後因其電容Cx儲存的電荷導致插頭長時間帶電,因而使用洩放電阻(bleeding resistor)R1並聯電容Cx以洩放其電荷,使電磁干擾濾波器12符合安規。例如CEI/IEC 60950-1 clause 2.1.1.7規定,電容Cx與洩放電阻R1的放電時間常數(time constant)需要小於1秒。通常洩放電阻R1為2MΩ,其功率消耗為4~35mW。只要交流電源AC供電,洩放電阻R1必定一直消耗能量。在系統待機時,洩放電阻R1的功率消耗更佔空載待機能耗相當大的比重。In recent years, due to the energy crisis and the concept of environmental protection, the EU, North America and Japan have set relevant green environmental regulations for electronic equipment. In addition to the conversion efficiency of electronic equipment, they also impose strict requirements on no-load standby energy consumption. As shown in Fig. 1, the electromagnetic interference filter 12 applied to the power supply device uses a bleeding resistor R1 shunt capacitor Cx in order to prevent the plug from being charged for a long time due to the charge stored in the capacitor Cx after the power plug is removed. To discharge its charge, the EMI filter 12 is in compliance with safety regulations. For example, CEI/IEC 60950-1 clause 2.1.1.7 specifies that the discharge time constant of capacitor Cx and bleeder resistor R1 needs to be less than 1 second. Usually, the bleeder resistor R1 is 2MΩ, and its power consumption is 4~35mW. As long as the AC power supply AC is supplied, the bleeder resistor R1 must always consume energy. When the system is in standby, the power consumption of the bleeder resistor R1 accounts for a considerable proportion of the no-load standby energy consumption.

本發明的目的之一,在於提供一種減少電磁干擾濾波器之功率消耗的洩放電路及方法。It is an object of the present invention to provide a bleeder circuit and method for reducing the power consumption of an electromagnetic interference filter.

根據本發明,一種減少電磁干擾濾波器之功率消耗的洩放電路包含整流電路連接該電磁干擾濾波器連接之交流電源,洩放電阻及洩放開關串聯於該整流電路及接地端之間,用來建立或切斷洩放路徑,以及偵測電路根據該整流電路產生的全波信號控制該洩放開關。According to the present invention, a bleeder circuit for reducing power consumption of an electromagnetic interference filter includes a rectifying circuit connected to an ac power supply connected to the EMI filter, and a bleeder resistor and a bleeder switch are connected in series between the rectifying circuit and the ground terminal. To establish or cut off the bleed path, and the detecting circuit controls the bleed switch according to the full wave signal generated by the rectifier circuit.

根據本發明,一種減少電磁干擾濾波器之功率消耗的洩放方法包含對該電磁干擾濾波器連接之交流電源整流以產生全波信號,以及根據該全波信號控制洩放開關以建立或切斷洩放路徑。According to the present invention, a bleeder method for reducing power consumption of an electromagnetic interference filter includes rectifying an alternating current power source connected to the electromagnetic interference filter to generate a full wave signal, and controlling the bleeder switch to establish or cut according to the full wave signal The bleed path.

圖2係根據本發明之實施例,以洩放電路14取代圖1中的洩放電阻R1,其包含洩放電阻R2和洩放開關SW串聯於整流電路16及接地端之間,在洩放開關SW閉路時建立起洩放路徑,在洩放開關SW開路時切斷洩放路徑。當交流電源AC供電時,電容Cx的跨壓Vx經整流電路16中的兩個二極體D1、D2整流成全波信號,偵測電路18將此全波信號經分壓器20分壓後的全波信號Vd和參考電壓Vref於比較器22比較而產生比較信號S1。若全波信號Vd高於參考電壓Vref,則比較信號S1為高準位,反之,則為低準位。偵測控制器24根據比較信號S1控制洩放開關SW,以控制洩放電阻R2何時洩放電容Cx的電荷,因而減少洩放電阻R2造成的損耗,進而降低空載待機能耗。2 is a bleeder circuit 14 in place of the bleeder resistor R1 of FIG. 1 in accordance with an embodiment of the present invention, which includes a bleeder resistor R2 and a bleeder switch SW connected in series between the rectifier circuit 16 and the ground terminal for venting When the switch SW is closed, a bleed path is established, and when the bleed switch SW is open, the bleed path is cut off. When the AC power supply AC is powered, the voltage across the voltage Vx of the capacitor Cx is rectified into a full-wave signal by the two diodes D1 and D2 in the rectifier circuit 16, and the detection circuit 18 divides the full-wave signal by the voltage divider 20. The full wave signal Vd and the reference voltage Vref are compared with the comparator 22 to produce a comparison signal S1. If the full-wave signal Vd is higher than the reference voltage Vref, the comparison signal S1 is at a high level, and vice versa, at a low level. The detection controller 24 controls the bleeder switch SW according to the comparison signal S1 to control when the bleeder resistor R2 bleeds the charge of the capacitor Cx, thereby reducing the loss caused by the bleeder resistor R2, thereby reducing the no-load standby power consumption.

圖3係圖2的電路的波形圖。當交流電源AC供電時,全波信號Vd與參考電壓Vref比較得到的比較信號S1會持續於高低準位之間切換,其於高準位的時間為T1,在此期間洩放開關SW為開路,因此洩放電阻R2等同不存在。在交流電源AC被移除後,若全波信號Vd高於參考電壓Vref,偵測控制器24在比較信號S1處於高準位的時間超過延遲時間T2時,導通洩放開關SW使洩放電阻R2洩放電容Cx的電荷,因而使電容Cx與洩放電阻R2的放電時間常數達到小於1秒之要求。延遲時間T2可以依據安規而設定,以決定洩放時間。要達到上述功能的偵測控制器24,其電路非常簡單,只需要一個上數或下數計時器,此係本技術領域之人士熟知者。較佳者,該計時器係可程式化的。Figure 3 is a waveform diagram of the circuit of Figure 2. When the AC power supply AC is powered, the comparison signal S1 obtained by comparing the full-wave signal Vd with the reference voltage Vref will continue to switch between the high and low levels, and the time at the high level is T1, during which the bleeder switch SW is open. Therefore, the bleeder resistor R2 is equivalently absent. After the AC power source AC is removed, if the full-wave signal Vd is higher than the reference voltage Vref, the detection controller 24 turns on the bleeder switch SW to discharge the bleeder resistor when the comparison signal S1 is at the high level for more than the delay time T2. R2 bleeds the charge of capacitor Cx, thus causing the discharge time constant of capacitor Cx and bleeder resistor R2 to be less than one second. The delay time T2 can be set according to safety regulations to determine the bleed time. The detection controller 24 to achieve the above functions has a very simple circuit and requires only a countdown or countdown timer, which is well known to those skilled in the art. Preferably, the timer is programmable.

以上對於本發明之較佳實施例所作的敘述係為闡明之目的,而無意限定本發明精確地為所揭露的形式,基於以上的教導或從本發明的實施例學習而作修改或變化是可能的,實施例係為解說本發明的原理以及讓熟習該項技術者以各種實施例利用本發明在實際應用上而選擇及敘述,本發明的技術思想由以下的申請專利範圍及其均等來決定。The above description of the preferred embodiments of the present invention is intended to be illustrative, and is not intended to limit the scope of the invention to the disclosed embodiments. It is possible to make modifications or variations based on the above teachings or learning from the embodiments of the present invention. The embodiments are described and illustrated in the practical application of the present invention in various embodiments, and the technical idea of the present invention is determined by the following claims and their equals. .

12...電磁干擾濾波器12. . . Electromagnetic interference filter

14...洩放電路14. . . Bleed circuit

16...整流電路16. . . Rectifier circuit

18...偵測電路18. . . Detection circuit

20...分壓器20. . . Voltage divider

22...比較器twenty two. . . Comparators

24...偵測控制器twenty four. . . Detection controller

圖1係習知的電磁干擾濾波器;Figure 1 is a conventional electromagnetic interference filter;

圖2係根據本發明之實施例;以及Figure 2 is an embodiment in accordance with the present invention;

圖3係圖2的電路的波形圖。Figure 3 is a waveform diagram of the circuit of Figure 2.

14...洩放電路14. . . Bleed circuit

16...整流電路16. . . Rectifier circuit

18...偵測電路18. . . Detection circuit

20...分壓器20. . . Voltage divider

22...比較器twenty two. . . Comparators

24...偵測控制器twenty four. . . Detection controller

Claims (6)

一種減少電磁干擾濾波器之功率消耗的洩放電路,該電磁干擾濾波器具有電容連接於交流電源之兩端之間,該洩放電路包含:整流電路連接於該交流電源之兩端之間,以產生全波信號;洩放電阻及洩放開關串聯於該整流電路及接地端之間;以及偵測電路連接該整流電路及洩放開關,根據該全波信號控制該洩放開關,該偵測電路包含:分壓器連接該整流電路,將該全波信號分壓;比較器連接該分壓器,比較該分壓後的全波信號和參考電壓,據以產生比較信號;以及偵測控制器連接該比較器,根據該比較信號產生控制信號切換該洩放開關。 A bleeder circuit for reducing power consumption of an electromagnetic interference filter, the EMI filter having a capacitor connected between two ends of the AC power source, the bleeder circuit comprising: a rectifier circuit connected between the two ends of the AC power source, To generate a full-wave signal; a bleeder resistor and a bleed switch are connected in series between the rectifier circuit and the ground; and a detection circuit is connected to the rectifier circuit and the bleed switch, and the bleed switch is controlled according to the full-wave signal, the Detector The measuring circuit comprises: a voltage divider connected to the rectifier circuit to divide the full-wave signal; a comparator connected to the voltage divider, comparing the divided full-wave signal and the reference voltage to generate a comparison signal; and detecting The controller is connected to the comparator, and generates a control signal according to the comparison signal to switch the bleed switch. 如請求項1之洩放電路,其中該整流電路包含兩二極體。 The bleeder circuit of claim 1, wherein the rectifier circuit comprises two diodes. 如請求項1之洩放電路,其中該偵測控制器計算該比較信號維持高準位的時間,據以決定該控制信號。 The bleeder circuit of claim 1, wherein the detection controller calculates a time at which the comparison signal maintains a high level, thereby determining the control signal. 如請求項3之洩放電路,其中該偵測控制器包含計時器以決定該控制信號。 The bleeder circuit of claim 3, wherein the detection controller includes a timer to determine the control signal. 一種減少電磁干擾濾波器之功率消耗的洩放方法,該電磁干擾濾波器具有電容連接於交流電源之兩端之間,該洩放方法包含:(A)對該交流電源整流以產生全波信號;以及(B)根據該全波信號控制洩放開關以建立或切斷洩放路徑;其中該步驟B包含: 將該全波信號分壓;比較該分壓後的全波信號和參考電壓以產生比較信號;以及根據該比較信號產生控制信號,俾將洩放電阻接地而建立該洩放路徑。 A bleeder method for reducing power consumption of an electromagnetic interference filter, the EMI filter having a capacitor connected between two ends of an AC power source, the bleed method comprising: (A) rectifying the AC power source to generate a full-wave signal And (B) controlling the bleeder switch to establish or cut a bleed path based on the full wave signal; wherein step B includes: The full-wave signal is divided; the divided full-wave signal and the reference voltage are compared to generate a comparison signal; and a control signal is generated according to the comparison signal, and the bleeder resistor is grounded to establish the bleed path. 如請求項5之洩放方法,更包含計算該比較信號維持高準位的時間以決定該控制信號。The bleed method of claim 5 further includes calculating a time at which the comparison signal maintains a high level to determine the control signal.
TW99113533A 2010-04-28 2010-04-28 Bleeding circuit and method for power reduction of an emi filter TWI436587B (en)

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Publication number Priority date Publication date Assignee Title
TWI481142B (en) * 2012-06-19 2015-04-11 Richtek Technology Corp Bleeding circuit and method for reducing power consumption of an emi filter
TWI628902B (en) * 2017-05-22 2018-07-01 偉詮電子股份有限公司 Control circuit and control method thereof capable of detecting status of receiving power and releasing voltage of capacitor accordingly
CN115498863B (en) * 2022-11-21 2023-05-02 成都智融微电子有限公司 HV bleeder circuit for power management chip

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