TWI435434B - Semiconductor package method for omitting interposer and bottom wafer for use thereof - Google Patents

Description

Semiconductor package method for omitting interposer and bottom wafer for use thereof

The present invention relates to a packaging technique for a semiconductor device, and more particularly to a semiconductor package method in which an interposer is omitted and a substrate for use therefor.

Multi-wafer stacking is one of the most important technologies in the current miniaturization of electronic products, which can achieve system function integration and capacity expansion. Since a plurality of wafers are stacked and packaged in the same package structure, the volume of each package can be greatly reduced, thereby making the electronic product have the advantages of high efficiency and versatility, and can simultaneously meet the demand for miniaturization.

In the current semiconductor industry, it is generally known that a package structure for a multi-wafer stack of different wafer sizes usually relies on an interposer to complete the electrical connection between the upper and lower wafers because the interposer has a reconfigured line. The function is to overcome the problem that the wire is too long or even cannot be electrically connected due to the difference in the size of the wafer due to the inconsistent wafer size. Generally speaking, the conventional interposer selects a dummy chip, a ceramic substrate or an organic substrate, but there is a problem of reliability and it is difficult to control the warpage after stacking, and the reliability problem is a thermal expansion coefficient. CTE mismatch is caused by delamination caused by poor adhesion between different materials.

Referring to FIG. 1 , a conventional semiconductor package method using an interposer mainly includes the following steps: step 11 of “providing a bottom wafer”, step 12 of “setting a bottom wafer to a substrate”, and “setting an intermediary”. Step 14 of "Laminating the Substrate on the Substrate", Step 14 of "Setting the Wafer on the Interposer", "Steps 15 of Forming Electrical Connection Elements to Electrically Connect the Interposer and Substrate", and "Sealing the Back Wafer, Upper Wafer and Step 16 of the Intermediary Board. 2 and 3 are a semiconductor package structure using an interposer according to a conventional method, which mainly includes a bottom wafer 110, a substrate 120 for carrying a wafer, and a wafer smaller than the bottom wafer 110. 130 and an interposer 170 disposed between the bottom wafer 110 and the upper wafer 130. In step 11, the bottom wafer 110 is provided, and the active surface 113 of the bottom wafer 110 is provided with a plurality of electrodes 114 such as pads. In step 12, the back side of the bottom wafer 110 is placed on the substrate 120 using an existing die bonding technique. In step 13, the interposer 170 is disposed on the active surface 113 of the bottom wafer 110, and the interposer 170 has a reconfigured wiring layer 171 (as shown in FIG. 3). In step 14, the back surface of the wafer 130 on the smaller size is adhesively disposed on the interposer 170, and the active surface 131 of the upper wafer 130 is provided with a plurality of pads 132. Therefore, in this multi-wafer stack structure of different wafer sizes, in addition to the thickness of the interposer 170, two adhesive layer thicknesses are formed on the lower surface of the interposer 170. In addition, in step 15, a plurality of electrical connection elements, such as the first bonding wires 141, are electrically connected to the interposer 170 to the substrate 120, and the plurality of second bonding wires 142 are electrically connected. The pads 132 of the upper wafer 130 are connected to the interposer 170, and the plurality of third bonding wires 143 are electrically connected to the interposer 170 and the electrodes 114 of the bottom wafer 110. In addition, in step 16, a glue 150 may be formed on the substrate 120 (as shown in FIG. 3) to seal the bottom wafer 110, the upper wafer 130 and the interposer 170. Due to the different wafer size of the multi-wafer stacking technology, the interposer is an essential component, resulting in an increase in package thickness, as well as delamination and warpage due to the difference in thermal expansion coefficient of the interposer to the wafer and low adhesion to the wafer interface. problem.

In order to solve the above problems, the main object of the present invention is a semiconductor package method for omitting an interposer and a bottom wafer for use thereof, which are mainly applied to a multi-wafer stack structure of different wafer sizes, which can omit the interposer and not affect the electrical properties. The quality of the connection quality, in turn, can thin the overall package thickness and reduce the occurrence of delamination and warpage.

A second object of the present invention is to provide a semiconductor package method for omitting an interposer and a bottom wafer for use thereof, which can achieve the effect of the multi-wafer active surface facing the substrate and eliminating the need for bumps between the wafers, thereby effectively thinning the multi-wafer stack thickness.

The object of the present invention and solving the technical problems thereof are achieved by the following technical solutions. The invention discloses a semiconductor packaging method for omitting an interposer, which mainly comprises the following steps. Firstly, a bottom wafer is provided. The bottom wafer is a two-layer structure comprising a semiconductor layer and an organic layer, and the semiconductor layer is first active. The surface layer is provided with a plurality of electrodes, and the organic layer is embedded with a reconfiguration circuit layer, and a plurality of first terminals and second terminals are disposed on the reconfiguration circuit layer and exposed on the organic layer. Next, the bottom wafer is disposed on a substrate such that the electrodes of the bottom wafer are electrically connected to the substrate. Thereafter, an upper wafer is disposed on the bottom wafer, and a second active surface of the upper wafer is attached to the organic layer and a plurality of pads of the upper wafer are bonded to the first terminals. Finally, a plurality of electrical connecting elements are formed to electrically connect the second terminals to the substrate. The present invention further specifically discloses a bottom wafer used in the aforementioned semiconductor packaging method.

The object of the present invention and solving the technical problems thereof can be further achieved by the following technical measures.

In the foregoing semiconductor packaging method, the organic layer may be a die attach film and have a viscosity.

In the foregoing semiconductor packaging method, the semiconductor layer may be a grain back-grinded die.

In the foregoing semiconductor packaging method, the thickness of the organic layer may be less than one-half of the thickness of the semiconductor layer.

In the above-mentioned semiconductor package method, the organic layer is further provided with a plurality of pressing blocks located on the reconfigurable circuit layer, which may be located between the first terminals and the second terminals, so that the The reconfiguration circuit layer can be completely embedded in the organic layer.

In the aforementioned semiconductor packaging method, the relocation wiring layer is electrically insulatively invisible to the semiconductor layer.

In the foregoing semiconductor packaging method, the upper wafer system may be a bare die, and the second active surface is completely adhered to the organic layer.

In the foregoing semiconductor packaging method, the electrical connection elements may be wire bonds that do not exceed the wire bonding of the upper wafer.

In the foregoing semiconductor packaging method, the method further comprises the steps of: forming a gel on the substrate to seal the bottom wafer, the upper wafer and the electrical connecting elements.

In the above semiconductor package method, the electrode lines may be metal conductor posts protruding from the first active surface for the sealant to fill the gap between the bottom wafer and the substrate.

In the foregoing semiconductor packaging method, the method may further include forming a plurality of external terminals on a lower surface of the substrate.

In the foregoing semiconductor packaging method, the step of providing a bottom wafer may include: providing a wafer; grinding a back surface of the wafer to reach a thickness of the semiconductor layer; forming an organic layer on the wafer Grinding the back side; forming a reconfigured wiring layer and embedding it in the organic layer; and cutting the wafer and the organic layer to produce the bottom wafer.

In the foregoing semiconductor package method, in the step of forming an organic layer, the organic layer may be formed under a metal foil in advance, and the step of forming a reconfigured wiring layer may include: pattern etching a metal foil to form the reconfigured wiring layer; and the reconfigured wiring layer is hot pressed to be trapped in the organic layer.

In the foregoing semiconductor package method, in the step of forming an organic layer, the step of forming a re-distribution circuit layer may further include: partially etching the metal foil before pattern etching the metal foil to Forming the first terminal and the second terminal.

In the foregoing semiconductor package method, the step of forming a re-distribution circuit layer may further include: after pattern etching the metal foil, disposing the first terminal and the second terminal on the re-distribution circuit layer.

It can be seen from the above technical solutions that the semiconductor packaging method for omitting the interposer of the present invention and the bottom wafer used thereof have the following advantages and effects:

1. A bottom wafer having a two-layer structure can be used as one of the technical means. Since the bottom wafer includes a semiconductor layer and an organic layer, the organic layer embedded with the reconfigured wiring layer replaces the conventional interposer and its double The surface adhesive layer is mainly applied to a multi-wafer stack structure of different wafer sizes, and the effect of omitting the interposer without affecting the quality of the electrical connection can be achieved, and the overall package thickness can be thinned. In addition, there is no problem that the conventional interposer does not match the expansion coefficient of the wafer or the adhesion between different materials leads to delamination, and can control the warpage of the multi-wafer stack.

Second, by providing a two-layer structure of the bottom wafer as one of the technical means, the wafer above the smaller wafer size can be a bare die and the active surface is completely adhered to the organic layer of the bottom wafer, and the multi-wafer initiative can be achieved. The surface faces the substrate and the effect of providing bumps between the wafers is effective to thin the thickness of the multi-wafer stack.

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings in which FIG. The components and combinations related to this case, the components shown in the figure are not drawn in proportion to the actual number, shape and size of the actual implementation. Some size ratios are proportional to other related sizes or have been exaggerated or simplified to provide clearer description of. The actual number, shape and size ratio of the implementation is an optional design, and the detailed component layout may be more complicated.

According to an embodiment of the present invention, a semiconductor package method for omitting an interposer is illustrated in a block diagram of FIG. 4, and a semiconductor package structure manufactured by the method is illustrated in a cross-sectional view of FIG. As shown in FIG. 5, the semiconductor package structure mainly includes a bottom wafer 210, a substrate 220, an upper wafer 230, and a plurality of electrical connection elements 240.

The main steps of the method illustrate a schematic cross-sectional view of the elements of Figures 6A through 6E. The semiconductor packaging method for omitting the interposer mainly includes the following steps: step 21 of "providing a bottom wafer", step 22 of "providing a bottom wafer onto the substrate", and "step of setting the upper wafer on the bottom wafer" according to FIG. 23, step 24 of "forming the electrical connection component to electrically connect the upper wafer and the substrate", and step 25 of "sealing the bottom wafer and the upper wafer", the specific operations of each step, please refer to Figures 6A to 6E, illustrating the following Show.

First, in step 21, referring to FIG. 6A, the bottom wafer 210 is provided in a two-layer structure, comprising a semiconductor layer 211 and an organic layer 212. The semiconductor layer 211 and the organic layer 212 are formed by the semiconductor layer 211 and the organic layer 212. a complete die for the pick-and-place machine, in other words, the organic layer 212 is formed at a wafer level, and the semiconductor layer 211 is not formed by wafer dicing into a single die. The organic layer 212 is formed. The base material of the semiconductor layer 211 may be bismuth or III-V, and the material of the organic layer 212 contains carbon, such as polyimide. A desired integrated circuit (not shown) is disposed on one surface of the semiconductor layer 211. The integrated circuit in this embodiment is a memory device, and the surface is the first active surface 213. . The first active surface 213 of the semiconductor layer 211 is provided with a plurality of electrodes 214 as external terminals of the integrated circuit. In this embodiment, the electrodes 214 are bumps, such as solder balls or metal conductor posts, such that the bottom wafer 210 can be flip-chip bonded to the substrate 220 (as shown in FIG. 5). In this embodiment, the semiconductor layer 211 can be a back-grained grain, that is, has no normal grain thickness, and the thickness can be controlled to 2 to 8 mils or less. The thickness of the organic layer 212 may be less than one-half of the thickness of the semiconductor layer 211, about 10 microns.

A plurality of re-distribution circuit layers 215 are embedded in the organic layer 212, and a plurality of first terminals 216 and second terminals 217 are disposed on the re-distribution circuit layer 215 and exposed on the organic layer 212. The reconfigurable circuit layer 215 is made of a conductive material, such as copper, to shorten the formation length of the electrical connecting elements 240. In a more specific configuration, the relocation wiring layer 215 is electrically insulatively invisible to the semiconductor layer 211 and acts as a line reconfiguration of the upper wafer 230 (as shown in FIG. 5). Therefore, the organic layer 212 is included in the bottom wafer 210 to omit the interposer independently disposed in the packaging process. The first terminal 216 and the second terminal 217 are also made of a conductive material, such as a copper post or a nickel gold, as an external end of the reconfigurable circuit layer 215. Moreover, the first terminals 216 and the second terminals 217 further have the function of controlling the embedding depth of the relocation circuit layer 215. More specifically, the organic layer 212 may be a die attach film (DAM) and have a viscosity, may be thermoplastic or semi-cured during the packaging process, so that the reconfigured circuit layer The 215 can be embedded therein, so that an adhesive layer and a solder resist layer covering the reconfigured wiring layer 215 can be further omitted.

Then proceed to step 22. As shown in FIG. 6B, the bottom wafer 210 is disposed on the upper surface 221 of the substrate 220 such that the electrodes 214 of the bottom wafer 210 are electrically connected to the substrate 220. In this embodiment, the bottom wafer 210 is a flip chip, and the electrodes 214 are bumps to be flip-chip bonded to the substrate 220. In this step, the first active surface 213 of the bottom wafer 210 faces the substrate 220. Preferably, the electrodes 214 are protruding from the metal conductor post of the first active surface 213 for the sealant 250 to fill the gap between the bottom wafer 210 and the substrate 220 (as shown in FIG. 5). . In addition, in the embodiment, the substrate 220 is a printed circuit board, and the upper surface 221 can be provided with a plurality of fingers 223 located outside the bottom area of the bottom wafer 210. In addition, a plurality of external pads 224 may be disposed on the lower surface 222 of the substrate 220. The external pads 224 may be electrically connected to the bonding pads of the fingers 223 and the electrodes 214 by the internal circuit structure of the substrate 220. (not shown in the figure).

Then proceed to step 23. As shown in FIG. 6C, the upper wafer 230 is disposed on the bottom wafer 210, and a second active surface 231 of the upper wafer 230 is attached to the organic layer 212 and a plurality of pads 232 of the upper wafer 230 are attached. Bonded to the first terminals 216. In the present embodiment, the upper wafer 230 is a controller that is significantly smaller in size than the bottom wafer 210. Moreover, by using the special structure of the bottom wafer 210, the upper wafer can be set to a general die bonding operation, but the effect of flip chip bonding can be achieved. Preferably, the upper wafer 230 can be a bare die, and the second active surface 231 is completely adhered to the organic layer 212. There is no need to retain the bump gap between the upper wafer 230 and the bottom wafer 210. With the thickness of the adhesive, to achieve the thinning effect of the multi-wafer stack structure of different wafer sizes. Therefore, the effect that the multi-wafer active surface faces the substrate and the bumps are not disposed between the wafers can be achieved, and the thickness of the multi-wafer stack is effectively thinned.

Then proceed to step 24. As shown in FIG. 6D, a plurality of electrical connecting elements 240 are formed to electrically connect the second terminals 217 to the fingers 223 of the substrate 220. The formation of the electrical connection elements 240 can utilize existing wire bonding techniques or internal pin bonding techniques. Preferably, the electrical connecting elements 240 can be wire bonds that do not exceed the back side of the upper wafer 230.

In the semiconductor packaging method of the present invention, a sealing step 25 may be further included. As shown in FIG. 6E, a glue body 250 is formed on the substrate 220 by a molding technique to seal the bottom wafer 210, the upper wafer 230, and the electrical connection elements 240. In addition, as shown in FIG. 5, in the semiconductor package method of the present invention, the method further includes the step of forming a plurality of external terminals 260 on a lower surface 222 of the substrate 220. The external terminals 260 can be solder balls that are bonded to the external pads 224.

As shown in FIG. 5, a semiconductor package structure omitting the interposer includes a bottom wafer 210, the substrate 220, the upper wafer 230, and the electrical connection elements 240. The bottom wafer 210 is The electrodes 214 of the bottom wafer 210 are electrically connected to the substrate 220. The upper wafer 230 is disposed on the bottom wafer 210, and a second active surface 231 of the upper wafer 230 is attached to the organic layer 212 and a plurality of pads 232 of the upper wafer 230 are bonded to the first Terminal 216. The electrical connection elements 240 electrically connect the second terminals 217 to the substrate 220 .

Therefore, the semiconductor package method of the present invention can omit the conventional interposer in a multi-wafer stack structure of different wafer sizes. Since the bottom wafer 210 is composed of the semiconductor layer 211 and the organic layer 212, the organic layer 212 in which the reconfigured wiring layer 215 is embedded replaces the conventional interposer and its double-sided adhesive layer, and is mainly applied to The multi-wafer stack structure of different wafer sizes can achieve the effect of omitting the interposer without affecting the quality of the electrical connection, thereby enabling thinning of the overall package thickness. In addition, there is no problem that the conventional interposer does not match the expansion coefficient of the wafer or the adhesion between different materials leads to delamination, and can control the warpage of the multi-wafer stack.

The method of manufacturing the base wafer 210 will be further described below in conjunction with FIGS. 7A to 7E. In the foregoing step 21 of providing the bottom wafer 210, the following substeps are included. First, as shown in FIG. 7A, a wafer 310 having a sufficient thickness (about ten mils or more) to perform an integrated circuit layout on the first active surface 213 is provided on the first active surface 213. The electrodes 214 can be provided. Next, as shown in FIG. 7B, a back grinding operation is performed to polish one back surface 311 of the wafer 310 to reach the thickness of the semiconductor layer 211. After the step, the wafer 310 is formed with a polished back surface 311A. . Thereafter, as shown in FIG. 7C, an organic layer 212 may be formed on the polished back surface 311A of the wafer 310 by a press-fitting or printing technique. Thereafter, as shown in FIG. 7D, the relocation wiring layer 215 is formed and embedded in the organic layer 212 (the specific embedding step is detailed later). Finally, as shown in FIG. 7E, the wafer 310 and the organic layer 212 are cut along the wafer dicing line by the wafer dicing tool 330 to produce the separated bottom wafer 210. In addition, the timing of the arrangement of the protruding electrodes 214 may be performed before the polishing step or after the trapping step of the relocation wiring layer 215 and before the wafer cutting step. Therefore, the formation of the organic layer 212 is performed at the wafer level and is an internal member of the die, and the individual die is not cut and attached to the back surface of the die.

The specific steps of embedding the reconfigured wiring layer 215 in the organic layer 212 are further described below. In a preferred embodiment, the aforementioned steps of forming the reconfiguration circuit layer 215 may further include the following detailed steps. As shown in FIG. 8A, in the step of forming an organic layer, the organic layer 212 is formed in advance under a metal foil 320, such as a copper foil substrate, and is bonded to the polished back surface of the wafer. 311A. Thereafter, as shown in FIG. 8B, before forming the relocation wiring layer 215, the metal foil 320 is half-etched in advance by a half etching technique to form the first terminal 216 and the second terminal 217. Thereafter, as shown in FIG. 8C, a second patterning etching is performed so that the remaining metal foil 320 is etched into the rearrangement wiring layer 215. Then, as shown in FIG. 8D, the first terminal 216, the second terminal 217 and the re-distribution circuit layer 215 are pressed by a press plate 340 by means of a mold compression, at a suitable temperature and pressure. The configuration circuit layer 215 will be embedded in the organic layer 212.

However, the present invention is not limited to the above-described trapping operation of the reconfiguration wiring layer. In another preferred embodiment, as shown in FIG. 9A, in the step of forming an organic layer, the organic layer 212 is formed in advance under another thin metal foil 320 having a thickness of the metal foil 320. It is smaller than the thickness of the organic layer 212, and the organic layer 212 is formed on the polished back surface 311A of the wafer 310. Thereafter, as shown in FIG. 9B, the metal foil 320 is selectively etched to form the relocation wiring layer 215. As shown in FIG. 9C, after forming the relocation wiring layer 215, the first terminal 216 and the second terminal 217 may be disposed on the relocation wiring layer 215 by electroplating or other terminal forming techniques. Then, as shown in FIG. 9D, the first terminal 216, the second terminal 217, and the rearrangement circuit layer 215 are pressed by the pressure plate 340 by using a mold compression, so that the reconfiguration circuit layer 215 is embedded in In the organic layer 212.

In another preferred embodiment, it is disclosed that the other bottom wafer is substantially identical to the bottom wafer and is represented by the same reference numerals. As shown in FIG. 10, the organic layer 212 is further provided with a plurality of pressing blocks 218 located on the reconfigurable circuit layer 215, which may be located between the first terminals 216 and the second terminals 217. So that the reconfiguration wiring layer 215 can be completely embedded in the organic layer 212.

The above is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention. Any simple modifications, equivalent changes and modifications made without departing from the technical scope of the present invention are still within the technical scope of the present invention.

11. . . Providing a bottom wafer

12. . . Set the bottom wafer to the substrate

13. . . Set the interposer on the bottom wafer

14. . . Set the upper wafer on the interposer

15. . . Forming an electrical connection component to electrically connect the interposer and the substrate

16. . . Sealing the bottom wafer, the upper wafer and the interposer

twenty one. . . Providing a bottom wafer

twenty two. . . Set the bottom wafer to the substrate

twenty three. . . Setting the upper wafer on the bottom wafer

twenty four. . . Forming an electrical connection element to electrically connect the upper wafer and the substrate

25. . . Sealing the bottom wafer and the upper wafer

110. . . Bottom wafer

113. . . Active surface

114. . . electrode

120. . . Substrate

130. . . Upper wafer

131. . . Active surface

132. . . Solder pad

141. . . First wire bond

142. . . Second wire

143. . . Third wire

150. . . Sealant

170. . . Intermediary board

171. . . Reconfigure the line layer

210. . . Bottom wafer

211. . . Semiconductor layer

212. . . Organic layer

213. . . First active surface

214. . . electrode

215. . . Reconfigure the line layer

216. . . First terminal

217. . . Second terminal

218. . . Briquetting block

220. . . Substrate

221. . . Upper surface

222. . . lower surface

223. . . Finger

224. . . External pad

230. . . Upper wafer

231. . . Second active surface

232. . . Solder pad

240. . . Electrical connection element

250. . . Sealant

260. . . External terminal

310. . . Wafer

311. . . back

311A. . . Grinding back

320. . . Metal foil

330. . . Wafer cutting tool

340. . . Press plate

Figure 1: A block diagram of a conventional semiconductor packaging method using an interposer.

Fig. 2 is a perspective view showing the structure of a semiconductor package manufactured in accordance with the flow of Fig. 1 in a see-through seal.

Fig. 3 is a schematic cross-sectional view showing a semiconductor package structure fabricated in accordance with the flow of Fig. 1.

4 is a block diagram showing a process of a semiconductor package in which an interposer is omitted, in accordance with a preferred embodiment of the present invention.

Fig. 5 is a schematic cross-sectional view showing a semiconductor package structure produced in accordance with the flow of Fig. 4 of the present invention.

6A to 6E are schematic cross-sectional views of the elements in the respective steps in the flow according to the fourth embodiment of the present invention.

7A to 7E are cross-sectional views showing the steps of the respective steps in the "providing a bottom wafer" step of the semiconductor package method in accordance with a preferred embodiment of the present invention.

8A to 8D are cross-sectional views showing the steps of the respective steps in the step of "forming a reconfigured wiring layer" in the "providing a bottom wafer" step of the semiconductor packaging method in accordance with a preferred embodiment of the present invention.

9A to 9D are cross-sectional views showing the steps of the respective steps in the step of "forming a reconfigurable wiring layer" in the "providing a bottom wafer" step of the semiconductor packaging method in accordance with another preferred embodiment of the present invention.

Figure 10 is a cross-sectional view showing another embodiment of the substrate in the semiconductor package structure in accordance with another preferred embodiment of the present invention.

210. . . Bottom wafer

211. . . Semiconductor layer

212. . . Organic layer

213. . . First active surface

214. . . electrode

215. . . Reconfigure the line layer

216. . . First terminal

217. . . Second terminal

220. . . Substrate

221. . . Upper surface

222. . . lower surface

223. . . Finger

224. . . External pad

230. . . Upper wafer

231. . . Second active surface

232. . . Solder pad

240. . . Electrical connection element

250. . . Sealant

260. . . External terminal

Claims (27)

A semiconductor packaging method for omitting an interposer includes: providing a bottom wafer, the bottom wafer having a two-layer structure comprising a semiconductor layer and an organic layer, wherein the first active surface of the semiconductor layer is provided with a plurality of electrodes a layer of reconfigured wiring is embedded in the organic layer, and a plurality of first terminals and a plurality of second terminals are disposed on the reconfigured wiring layer and exposed on the organic layer; and the bottom wafer is disposed to a substrate, wherein the electrodes of the bottom wafer are electrically connected to the substrate; an upper wafer is disposed on the bottom wafer, and a second active surface of the upper wafer is attached to the organic layer and the upper wafer is A plurality of pads are bonded to the first terminals; and a plurality of electrical connection elements are formed to electrically connect the second terminals to the substrate. The semiconductor package method of omitting an interposer according to the first aspect of the patent application, wherein the organic layer is a die attach film and has a viscosity. The semiconductor package method of omitting an interposer according to the first aspect of the patent application, wherein the semiconductor layer is a crystal back-grinded die. The semiconductor package method of omitting an interposer according to claim 1 or 3, wherein the thickness of the organic layer is less than one-half of the thickness of the semiconductor layer. Semiconductor seal omitting the interposer according to item 1 of the patent application scope The mounting method, wherein the organic layer is further provided with a plurality of pressing blocks located above the reconfigurable circuit layer, and is disposed between the first terminals and the second terminals, so that the reconfigurable circuit layer can be It is completely embedded in the organic layer. The semiconductor package method of omitting an interposer according to the first aspect of the patent application, wherein the re-distribution circuit layer is electrically insulatively does not touch the semiconductor layer. The semiconductor package method of omitting an interposer according to the first aspect of the patent application, wherein the upper wafer is a bare die, and the second active surface is completely adhered to the organic layer. The semiconductor package method of omitting an interposer according to the first aspect of the patent application, wherein the electrical connection elements are such that the line arc does not exceed the bonding line of the upper wafer. The semiconductor packaging method of omitting the interposer according to claim 1 of the patent application further comprises the steps of: forming a gel on the substrate to seal the bottom wafer, the upper wafer and the electrical connecting elements. The semiconductor package method of omitting an interposer according to claim 9 , wherein the electrodes are metal conductor posts protruding from the first active surface, so that the encapsulant fills a gap between the bottom wafer and the substrate. According to the semiconductor package method of omitting the interposer according to claim 9 of the patent application, the method further comprises the steps of: forming a plurality of external terminals on a lower surface of the substrate. According to the semiconductor package method of omitting the interposer according to the first aspect of the patent application, the step of providing a bottom wafer includes: providing a wafer; grinding a back surface of the wafer to reach a thickness of the semiconductor layer; forming a The organic layer is on the back side of the polished surface of the wafer; a reconfigured wiring layer is formed and embedded in the organic layer; and the wafer and the organic layer are cut to obtain the bottom wafer. The semiconductor package method of omitting an interposer according to claim 12, wherein in the step of forming an organic layer, the organic layer is previously formed under a metal foil, and the step of forming a reconfigured wiring layer The method includes: pattern etching the metal foil to form the reconfigured wiring layer; and hot pressing the reconfigured wiring layer to trap the organic layer. The semiconductor package method of omitting an interposer according to claim 13 , wherein the step of forming a reconfigured wiring layer further comprises: semi-etching the metal foil in advance before pattern etching the metal foil to form the metal foil; Some first terminals and the second terminals. The semiconductor package method of omitting an interposer according to claim 13 , wherein the step of forming a reconfigured wiring layer further comprises: after pattern etching the metal foil, setting the first terminals and the first The two terminals are on the reconfiguration circuit layer. A bottom wafer omitting an interposer in a semiconductor package structure, The bottom wafer is a two-layer structure comprising a semiconductor layer and an organic layer. The first active surface of the semiconductor layer is provided with a plurality of electrodes, and the organic layer is embedded with a reconfigurable circuit layer and is provided with A plurality of first terminals and a plurality of second terminals located above the reconfiguration circuit layer and exposed to the organic layer. The bottom wafer of the interposer in the semiconductor package structure is omitted according to the scope of claim 16 wherein the organic layer is a die attach film and has a viscosity. The bottom wafer of the interposer in the semiconductor package structure is omitted in accordance with claim 16 of the patent application, wherein the semiconductor layer is a crystal back-grinded die. The bottom wafer of the interposer in the semiconductor package structure is omitted in accordance with claim 16 or 18, wherein the thickness of the organic layer is less than one-half the thickness of the semiconductor layer. The bottom wafer of the interposer in the semiconductor package structure is omitted according to claim 16 of the patent application, wherein the organic layer is further provided with a plurality of briquettes located above the reconfiguration circuit layer, which are located at the first terminals and Between the second terminals, the reconfigured circuit layer can be completely embedded in the organic layer. The bottom wafer of the interposer in the semiconductor package structure is omitted in accordance with claim 16 of the patent application, wherein the re-distribution circuit layer is electrically insulatively not in contact with the semiconductor layer. A semiconductor package structure omitting an interposer, comprising the bottom wafer of claim 16, further comprising: a substrate disposed on the substrate to electrically charge the electrodes of the bottom wafer Connected to the substrate; an upper wafer is disposed on the bottom wafer, a second active surface of the upper wafer is attached to the organic layer and a plurality of pads of the upper wafer are bonded to the first And a plurality of electrical connecting elements for electrically connecting the second terminals to the substrate. The semiconductor package structure of the interposer is omitted according to claim 22, wherein the upper wafer is a bare die, and the second active surface is completely adhered to the organic layer. The semiconductor package structure in which the interposer is omitted according to the scope of claim 22, wherein the electrical connection elements are such that the line arc does not exceed the bonding line of the upper wafer. The semiconductor package structure omitting the interposer according to claim 22 of the patent application, further comprising a glue formed on the substrate to seal the bottom wafer, the upper wafer and the electrical connection elements. The semiconductor package structure of the interposer is omitted according to claim 25, wherein the electrodes are metal conductor posts protruding from the first active surface for the encapsulant to fill the gap between the bottom wafer and the substrate. The semiconductor package structure in which the interposer is omitted according to the 25th application of the patent application, further includes a plurality of external terminals disposed on a lower surface of the substrate.