TWI435411B - Semiconductor device and manufacturing method thereof - Google Patents

Description

Semiconductor device and method of manufacturing same

The present invention relates to a semiconductor device and a manufacturing technique thereof, and more particularly to an effective technique for a semiconductor device having a high withstand voltage MISFET such as an LCD (Liquid Crystal Display) driver, and a manufacturing technique thereof.

Japanese Patent Publication No. 2005-116744 (Patent Document 1) discloses a technique of forming a high piezoelectric crystal and a low piezoelectric crystal on the same substrate. In Patent Document 1, the high-resistant piezoelectric crystal system has an offset insulating layer for electric field relaxation. Further, the guard ring formed in the high resistance piezoelectric crystal formation region is connected to the wiring (the lowermost wiring) formed on the interlayer insulating film of the first layer. On the other hand, the source region or the drain region of the high-resistance piezoelectric crystal is a wiring formed on the second interlayer insulating film formed on the interlayer insulating film of the first layer (non-lower layer wiring) )connection. That is, the source region or the drain region of the high-resistance piezoelectric crystal is disposed on the second interlayer insulating film by a plug that penetrates the first interlayer insulating film and the second interlayer insulating film at a time. Wiring connections.

Japanese Patent Publication No. 4-171938 (Patent Document 2) discloses a technique of forming a high withstand voltage n-channel FET and a low withstand voltage n-channel FET on the same substrate. At this time, the low withstand voltage n-channel FET is a lowermost layer wiring formed on the first interlayer insulating film, and is connected to the source region or the drain region. In contrast, in the high withstand voltage n-channel FET, the source region or the drain region is formed such as to be connected to the wiring formed on the second interlayer insulating film, not the most The wiring of the lower layer is connected.

[Patent Document 1] JP-A-2005-116744 (Patent Document 2) JP-A-4-171938

In recent years, LCDs using liquid crystals for display elements have rapidly spread. The LCD is controlled by a driver for driving the LCD. The LCD driver is composed of a semiconductor wafer and is mounted on, for example, a glass substrate. The semiconductor wafer constituting the LCD driver has a structure in which a plurality of transistors and a plurality of layers of wiring are formed on a semiconductor substrate, and bump electrodes are formed on the surface. Moreover, it is attached to the glass substrate via the bump electrode formed on the surface.

Among the plurality of transistors (MISFETs) formed in the LCD driver, there are a low withstand voltage MISFET and a high withstand voltage MISFET. That is, the LCD driver usually has a circuit composed of a low withstand voltage MISFET driven at a voltage of about 5 V, and a circuit having a voltage of about 20 V to 30 V applied to the electrode of the LCD. In order to apply a voltage of about 20 V to 30 V to the electrodes of the LCD, a level shift circuit is connected to a logic circuit driven at a level of 5 V, and a switching element is connected via a level shift circuit. The switching element is a MISFET that is driven by a voltage of 20 V to 30 V and is composed of a so-called high withstand voltage MISFET.

As described above, the LCD driver is provided with a low withstand voltage MISFET and a high withstand voltage MISFET on the same semiconductor substrate. An interlayer insulating film is formed on the low withstand voltage MISFET and the high withstand voltage MISFET formed on the same semiconductor substrate, and wiring is formed on the interlayer insulating film. Wiring and MISFET are connected The plug of the interlayer insulating film is connected. Generally, a wiring connected to a source region or a drain region of a high withstand voltage MISFET is not formed on the first interlayer insulating film, but a second interlayer insulating film is further formed on the first interlayer insulating film. The second interlayer insulating film is formed on the second interlayer insulating film. In short, since the high withstand voltage MISFET uses a relatively high voltage of about 20 V to 30 V, in order to ensure the withstand voltage of the wiring and the high withstand voltage MISFET (gate electrode), the second interlayer insulating film is disposed. The wiring is not arranged on the first interlayer insulating film to ensure the withstand voltage of the high withstand voltage MISFET. Therefore, the high withstand voltage MISFET and the wiring are connected via a plug that penetrates the first interlayer insulating film and a plug that penetrates through the second interlayer insulating film.

In recent years, miniaturization of LCD drivers has been demanded. Therefore, the diameter of the plug (contact plug) for narrowing the connection between the MISFET and the wiring of the LCD driver is performed. For example, the diameter of the plug is greatly reduced from 0.24 μm to 0.14 μm. However, if the diameter of the plug is reduced, the problem that the resistance caused by the plug becomes large is emphasized. In particular, since the high withstand voltage MISFET is connected to the high withstand voltage MISFET and the wiring by the plug which penetrates the first interlayer insulating film and the second interlayer insulating film, the plug is made high by reducing the diameter of the plug. The width ratio becomes larger and the resistance increases. Therefore, in the LCD driver, since the wiring is formed on the first interlayer insulating film, and the wiring width of the wiring formed on the first interlayer insulating film is increased, the connection of the first interlayer insulating film and the second is increased. The number of plugs of the interlayer insulating film is reduced to reduce the resistance of the plug. Wiring is also formed in the first interlayer insulating film, whereby the plug which penetrates the first interlayer insulating film and the plug which penetrates the second interlayer insulating film are not directly connected, and the aspect ratio of the plug can be reduced. Therefore, it is possible to suppress the reduction of the plug diameter. High resistance.

Further, by making the film thickness of the first interlayer insulating film thin, the aspect ratio of the plug formed in the first interlayer insulating film is reduced. As described above, in the wafer scaling of the LCD driver, the film thickness of the first interlayer insulating film is made thin, and wiring is formed on the first interlayer insulating film. Then, the wiring width of the wiring formed on the first interlayer insulating film is increased, and the number of plugs connecting the first interlayer insulating film and the second interlayer insulating film is increased. Here, in order to increase the wiring width of the wiring formed on the first interlayer insulating film, the source wiring connected to the source region of the high withstand voltage MISFET or the drain region of the high withstand voltage MISFET is connected The gate wiring is formed to have a region overlapping the gate electrode of the high withstand voltage MISFET in a plan view.

In this way, it is possible to suppress the increase in resistance of the plug which is reduced in size with the LCD driver, but a new problem occurs. In short, the LCD driver is configured such that the thickness of the first interlayer insulating film is thinned, and the source wiring or the drain wiring and the gate electrode of the high withstand voltage MISFET overlap in a plan view. Therefore, a breakdown voltage between the gate electrode and the source wiring of the high withstand voltage MISFET or between the gate electrode and the drain region of the high withstand voltage MISFET occurs. As a cause of the breakdown of the withstand voltage, the first step is a high-withstand voltage MISFET due to a variation of the polishing step due to a film formation step of the first interlayer insulating film or CMP (Chemical Mechanical Polishing). The first interlayer insulating film on the gate electrode is liable to become very thin. Therefore, it is judged that the source electrode or the drain wiring formed on the first interlayer insulating film is defective in withstand voltage.

The second can be cited as a high withstand voltage MISFET, the film thickness of the gate insulating film is very thick. Then, in the high-withstand voltage MISFET, an electric field relaxation insulating region slightly protruding from the semiconductor substrate is formed in the source region or the drain region, and the end portion of the gate electrode is placed on the electric field relaxation insulating region, so that the reason One of them is that the height of the gate electrode is higher than that of the low withstand voltage MISFET.

Further, as a third reason, the driving voltage of the high withstand voltage MISFET is about 20 V to 30 V, which is higher than that of the low withstand voltage MISFET. As described above, with the configuration of the current LCD driver, it is difficult to increase the resistance of the plug with the size reduction, and it is possible to improve the breakdown voltage between the gate electrode of the high withstand voltage MISFET and the wiring.

It is an object of the present invention to provide a semiconductor device including a high withstand voltage MISFET and a low withstand voltage MISFET, such as an LCD driver, which can suppress the high resistance of a plug due to miniaturization and improve the gate of a high withstand voltage MISFET. A technique for withstanding a breakdown voltage between an electrode and a wiring.

The above and other objects and novel features of the present invention will be apparent from the description and appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS The summary of the representative of the invention disclosed in the present application is as follows.

A semiconductor device according to the present invention is characterized by comprising: (a1) a gate insulating film formed on a semiconductor substrate; (a2) a gate electrode formed on the gate insulating film; and (a3) a MISFET The method is included in a source region and a drain region formed by the integration of the gate electrode. Then, there is provided: (b) an insulating film formed on the MISFET; (c) a first plug, the system And passing through the insulating film and electrically connected to the source region; and (d) a second plug penetrating through the insulating film and electrically connected to the drain region. Further, the method further includes: (e) a source wiring formed on the insulating film and electrically connected to the first plug; and (f) a drain wiring formed on the insulating film, and The second plug is electrically connected. Here, the distance from the interface between the semiconductor substrate and the gate insulating film to the upper surface of the gate electrode is a, and the source wiring and the drain pad are formed from the upper surface of the gate electrode. In the case where the distance from the upper surface of the insulating film of the line is b, a>b. At this time, the gate electrode and the source wiring are disposed so as not to overlap each other in a plan view, and the gate electrode and the drain wiring are disposed so as not to overlap each other in a plan view.

Further, the method of manufacturing a semiconductor device according to the present invention is characterized by comprising the steps of: (a) forming a device isolation region and an electric field relaxation insulating region on a semiconductor substrate; and (b) forming a gate insulating film on the semiconductor substrate. And (c) forming a pair of low-concentration impurity diffusion regions so as to encapsulate the insulating regions for electric field relaxation. Then, there are provided: (d) a step of forming a gate electrode on the gate insulating film; and (e) a step of forming a sidewall on sidewalls on both sides of the gate electrode. Further, (f) forming a pair of high-concentration impurity diffusion regions and forming a pair of low-concentration impurities by the region surrounded by the pair of low-concentration impurity diffusion regions and being outside the insulating region for the electric field relaxation. a source region composed of one of the diffusion regions and one of the pair of high-concentration impurity diffusion regions included therein, and another one of the pair of low-concentration impurity diffusion regions and the first one included therein It is composed of another one of the high-concentration impurity diffusion regions. Steps in the bungee area. Further, (g) a step of forming an insulating film so as to cover the gate electrode; and (h) forming a first plug that penetrates the insulating film and reaches the source region, and is formed to penetrate through the insulating film The step of the second plug of the aforementioned drain region. Further, (i) forming a source wiring connected to the first plug on the insulating film, and forming a drain wiring connected to the second plug on the insulating film. Here, the distance from the interface between the semiconductor substrate and the gate insulating film to the upper portion of the gate electrode is a, from the upper portion of the gate electrode to the source wiring and the drain wiring. When the distance from the upper surface of the insulating film is b, a>b. In this case, the gate electrode and the source wiring are formed so as not to overlap each other in a plan view, and the gate electrode and the drain wiring are formed so as not to overlap each other in a plan view.

In the case of the invention disclosed in the present application, the effects obtained by representative aspects are as follows.

In a semiconductor device including a high-withstand voltage MISFET and a low-withstand voltage MISFET such as an LCD driver, it is possible to suppress a high resistance of a plug due to miniaturization of a semiconductor device, and to improve a gate of a high withstand voltage MISFET. Poor pressure between the electrode and the wiring.

In the following embodiments, for the sake of brevity, it is described as being divided into plural sections or implementation types as necessary, but unless otherwise specified, they are not related to each other, and one party belongs to the other. Some or all of the modifications, details, and supplementary explanations.

In addition, in the following embodiments, when a numerical value or the like of an element (including a number, a numerical value, a quantity, a range, and the like) is mentioned, except for the case where it is specifically indicated, and the case where it is clearly limited to a specific number in principle, It is not limited to the specific number, and may be a specific number or more or less.

Further, in the following embodiments, the constituent elements (including the element steps and the like) are not necessarily necessary unless otherwise specified, and the case where it is determined that it is obviously necessary in principle, and of course, it is not necessarily necessary.

Similarly, in the following embodiments, when the shape, the positional relationship, and the like of the constituent elements and the like are mentioned, in addition to the case where it is specifically indicated, and the case where it is judged to be absolutely negative in principle, it is substantially similar to the shape and the like. Or similar. At this time, the above numerical values and ranges are also as described above.

In the drawings, the same components are denoted by the same reference numerals, and the repeated description thereof will be omitted. Further, in order to make the drawing easy to understand, even if it is a top view, it is attached with a hatch.

(Implementation type 1)

First, a semiconductor wafer for an LCD driver in the present embodiment will be described. Fig. 1 is a plan view showing the structure of a semiconductor wafer CHP (semiconductor device) in the present embodiment. The semiconductor wafer CHP in this embodiment is an LCD driver. In FIG. 1, a semiconductor wafer CHP has a semiconductor substrate 1S formed in, for example, an elongated rectangular shape, and an LCD driver capable of driving, for example, a liquid crystal display device is formed on a main surface thereof. The LCD driver has a function of supplying a voltage to each pixel constituting a cell array of the LCD and controlling the direction of the liquid crystal molecules, and has a gate driving circuit C1, a source driving circuit C2, and a liquid crystal driving circuit C3. Graphics RAM (Random Access Memory) C4 and peripheral circuit C5.

In the vicinity of the outer periphery of the semiconductor wafer CHP, the plurality of bump electrodes BMP are arranged at predetermined intervals along the outer circumference of the semiconductor wafer CHP. The plurality of bump electrodes BMP are disposed on an effective region of an element or wiring on which the semiconductor wafer CHP is disposed. In the complex bump electrode BMP, there are a bump electrode for an integrated circuit which is necessary for the structure of the integrated circuit, or a dummy bump electrode which is unnecessary for the structure of the integrated circuit. The bump electrodes BMP are arranged in a lattice cross shape in the vicinity of one long side and two short sides of the semiconductor wafer CHP. The plurality of bump electrodes BMP arranged in a lattice cross shape are mainly bump electrodes for a gate output signal or a source output signal. The bump electrode BMP arranged in a lattice at the center of the long side of the semiconductor wafer CHP is a bump electrode for the source output signal, and is lattice-crossed at two corners of the long side of the semiconductor wafer CHP and two short sides of the semiconductor wafer CHP. The bump electrode BMP is configured as a bump electrode for the gate output signal. By adopting such a lattice cross arrangement, it is possible to suppress an increase in the size of the semiconductor wafer CHP, and at the same time, it is possible to arrange a bump electrode BMP for a plurality of gate output signals or a bump electrode BMP for a source output signal. That is, the wafer size can be reduced while increasing the number of bump electrodes.

Further, in the vicinity of the other long side of the semiconductor wafer CHP, the bump electrodes BMP are not arranged in a line-like arrangement in a lattice arrangement. The bump electrode BMP arranged in a line-like manner is a bump electrode for a digital input signal or an analog input signal. Further, a dummy bump electrode is formed in the vicinity of the four corners of the semiconductor wafer CHP. In addition, FIG. 1 illustrates an example in which the bump electrodes BMP for the gate output signal or the source output signal are arranged in a lattice, and the bump electrodes BMP for the digital input signal or the analog input signal are arranged in a line shape. However, the bump electrode BMP for the gate output signal or the source output signal may be arranged in a line shape, and the digital input signal or the bump electrode BMP for the analog input signal may be arranged in a lattice.

The outer dimensions of the semiconductor wafer CHP are, for example, 1.0 mm in the short side direction and 12.0 mm in the longitudinal direction, or 1.0 mm in the short side direction and 10.0 mm in the long side direction. Further, for example, the length in the short side direction is 2.0 mm, and the length in the long side direction is 20.0 mm. Thus, the semiconductor wafer CHP used in the LCD driver has a rectangular shape. Specifically, the ratio of the length of the short side to the length of the long side is very large from 1:8 to 1:12. Further, there are also those having a length in the longitudinal direction of 5 mm or more.

Inside the semiconductor wafer CHP of the LCD driver shown in FIG. 1, there are a low breakdown voltage MISFET used for a logic circuit or the like, and a high withstand voltage MISFET used for a liquid crystal drive circuit or the like. For example, in the specification of the present application, a MISFET that operates at a driving voltage of about 5 V to 6 V is called a low withstand voltage MISFET, and a MISFET that operates with a driving voltage of about 20 V to 30 V is called a high withstand voltage MISFET.

2 is a cross-sectional view of a MISFET existing inside the semiconductor wafer CHP shown in FIG. 1. FIG. 2 illustrates a low withstand voltage MISFET and a high withstand voltage MISFET.

First, the structure of the high withstand voltage MISFET will be described. In FIG. 2, in the high withstand voltage MISFET formation region, component separation is formed on the semiconductor substrate 1S. Area 2. That is, a high withstand voltage MISFET is formed in the active region separated by the element isolation region 2. A p-type well 4 is formed in the semiconductor substrate 1S sandwiched by the plurality of element isolation regions 2. This p-type well 4 is a well formed for a high withstand voltage MISFET. Further, in the high withstand voltage MISFET formation region, the electric field relaxation insulating region 3 is formed in a region sandwiched by the plurality of element isolation regions 2. The electric field relaxation insulating region 3 is formed in the same manner as the element isolation region 2, for example, by an STI (Shallow Trench Isolation) method.

In the p-type well 4, a pair of low-concentration impurity diffusion regions (n-type semiconductor regions) 6 for high withstand voltage are formed, and each low-density impurity diffusion region for high withstand voltage is formed by encapsulating the insulating region 3 for electric field relaxation. . A gate insulating film 8 is formed on the surface of the semiconductor substrate 1S located between the pair of high-density low-concentration impurity diffusion regions 6, and a gate electrode 10b is formed on the gate insulating film 8. The gate insulating film 8 is formed of, for example, a hafnium oxide film, and the gate electrode 10b is formed of, for example, a laminated film of a polycrystalline germanium film and a cobalt germanide film. As the gate electrode 10b, a cobalt ruthenium film is formed on the polysilicon film, and the gate electrode 10b can be made low in resistance.

The gate insulating film 8 is formed by resting its end portion on the electric field relaxation insulating region 3. In the high-withstand voltage MISFET formation region, the element isolation region 2 and the electric field relaxation insulating region 3 are easily removed from the surface of the semiconductor substrate 1S due to the high occupancy ratio of the element isolation region 2 and the electric field relaxation insulating region 3. protruding. Therefore, the end portion of the gate insulating film 8 has a shape that rests on the electric field relaxation insulating region 3. Therefore, the gate electrode 10b formed on the gate insulating film 8 is also formed in such a manner that its end portion is raised.

Next, a side wall 12 is formed on the side walls of both sides of the gate electrode 10b, and the side wall 12 is also formed on the electric field relaxation insulating region 3. Then, a high-concentration impurity diffusion region (n-type semiconductor region) 14 for high withstand voltage is formed in the high-concentration low-concentration impurity diffusion region 6 on the outer side of the electric field relaxation insulating region 3. A cobalt vapor film 15 is formed on the surface of the high-concentration impurity diffusion region 14 for high withstand voltage. In this way, one high-pressure impurity diffusion region 14 for high withstand voltage and one high-density impurity diffusion region 14 for high withstand voltage and the cobalt telluride formed inside the low-concentration impurity diffusion region 6 for high withstand voltage are provided. The film 15 forms a source region of the high withstand voltage MISFET. In the same manner, the high-pressure impurity diffusion region 14 for high withstand voltage and the cobalt-deposited region formed in the low-concentration impurity diffusion region 6 for high-withstand voltage are provided by the other one of the low-concentration impurity diffusion regions 6 for the high withstand voltage. The film 15 forms a drain region of the high withstand voltage MISFET.

In the present embodiment, since the electric field relaxation insulating region 3 is formed at the end portion of the gate electrode 10b, the electric field formed at the end portion of the gate electrode 10b can be alleviated. Therefore, the withstand voltage between the gate electrode 10b and the source region or between the gate electrode 10b and the drain region can be ensured. In other words, in the high breakdown voltage MISFET, by forming the electric field relaxation insulating region 3, the withstand voltage can be ensured even when the driving voltage is 20 V to 30 V.

The high withstand voltage MISFET in the present embodiment has the above configuration, and the configuration of the low withstand voltage MISFET according to this embodiment will be described below.

In FIG. 2, in the low withstand voltage MISFET formation region, the element isolation region 2 is formed on the semiconductor substrate 1S. That is, in the active region where the element isolation region 2 is separated, a low withstand voltage MISFET is formed. In the plural component A p-type well 4 is formed in the semiconductor substrate 1S sandwiched between the regions 2. Further, in the p-type well 4, a well for a low withstand voltage MISFET, that is, a p-type well 5 is formed. Further, in the low breakdown voltage MISFET formation region, the electric field relaxation insulating region 3 is not formed.

A gate insulating film 7 is formed on the p-type well 5, and a gate electrode 10a is formed on the gate insulating film 7. The gate insulating film 7 is formed, for example, of a hafnium oxide film, and the gate electrode 10a is formed of, for example, a laminated film of a polycrystalline germanium film and a cobalt germanide film. As the gate electrode 10a, a low-resistance of the gate electrode 10a can be achieved by forming a cobalt germanide film on the polysilicon film. In the low withstand voltage MISFET, since the driving voltage is lower than that of the high withstand voltage MISFET, the film thickness of the gate insulating film 7 of the low withstand voltage MISFET is thinner than the film thickness of the gate insulating film 8 of the high withstand voltage MISFET.

A side wall 12 is formed on the side walls on both sides of the gate electrode 10a, and a pair of low-concentration impurity diffusion regions (n-type semiconductor regions) 11 for low withstand voltage are formed in the p-type well 5 directly below the side wall 12. Further, a high-concentration impurity diffusion region (n-type semiconductor region) 13 for low withstand voltage is formed on the outer side of the pair of low-voltage low-concentration impurity diffusion regions 11. A cobalt telluride film 15 is formed on the surface of the high-concentration impurity diffusion region 13 for low withstand voltage. In this way, the low-concentration impurity diffusion region 11 for low withstand voltage, the high-concentration impurity diffusion region 13 for low withstand voltage formed on the outer side of the low-voltage impurity diffusion region 11 for low withstand voltage, and the low withstand voltage are formed. The source region of the low withstand voltage MISFET is formed by the cobalt vapor film 15 on the surface of the high concentration impurity diffusion region 13. In the same manner, the low-concentration impurity diffusion region 11 for the low withstand voltage and the high-concentration impurity for the low withstand voltage formed on the outer side of the low-voltage impurity diffusion region 11 for low withstand voltage The diffusion region 13 and the cobalt vapor film 15 formed on the surface of the high-concentration impurity diffusion region 13 for low withstand voltage form a drain region of the low withstand voltage MISFET. The low withstand voltage MISFET is constructed as above.

Next, a wiring structure formed on the high withstand voltage MISFET and the low withstand voltage MISFET will be described. In the present embodiment, the wiring structure formed on the high withstand voltage MISFET has one feature. First, a wiring structure on a high withstand voltage MISFET which is characteristic of the present embodiment will be described.

As shown in FIG. 2, a first interlayer insulating film is formed on the high withstand voltage MISFET. Specifically, the first interlayer insulating film is formed of a laminated film of the tantalum nitride film 16 and the hafnium oxide film 17. Then, a first interlayer insulating film composed of the tantalum nitride film 16 and the tantalum oxide film 17 is formed with a plug (first plug) PLG1 that penetrates the interlayer insulating film and reaches the source region of the high withstand voltage MISFET. And a plug (second plug) PLG1 that penetrates the interlayer insulating film and reaches the drain region of the high withstand voltage MISFET. Then, a wiring (source wiring, drain wiring) HL1 is formed on the first interlayer insulating film on which the plug PLG1 is formed. Further, a wiring HL1 is formed on the first interlayer insulating film, and a second interlayer insulating film or a third interlayer insulating film is formed on the first interlayer insulating film including the wiring HL1. A wiring is formed on the interlayer insulating film. That is, a multilayer wiring is formed on the high withstand voltage MISFET, but only the first layer wiring HL1 of the present invention is illustrated in FIG.

One of the features of this embodiment is that a wiring HL1 as a source wiring or a drain wiring is formed on the first interlayer insulating film, and a gate electrode of the wiring HL1 and the high withstand voltage MISFET is formed. 10b is arranged such that the wiring HL1 is not overlapped in a plan view.

In the conventional LCD driver, in the region where the high withstand voltage MISFET is formed, no wiring is formed on the first interlayer insulating film, and wiring is formed for the first time on the second interlayer insulating film. This is carried out from the viewpoint of ensuring the withstand voltage of the gate electrode and the drain wiring of the gate electrode and the source wiring of the high withstand voltage MISFET and the high-withstand voltage MISFET. In this case, the source wiring or the drain region of the high-withstand voltage MISFET is connected by a plug that penetrates the two types of interlayer insulating films of the first interlayer insulating film and the second interlayer insulating film. The drain region with a high withstand voltage MISFET. Therefore, although it is worried that the resistance is high in the plug which penetrates the first interlayer insulating film and the second interlayer insulating film, since the diameter of the plug (for example, 0.24 μm) is ensured in the past, the resistance of the plug is not Highlighted as a problem.

However, due to the miniaturization of the LCD driver, the diameter of the plug is greatly reduced. For example, a plug diameter of 0.24 μm is reduced to a plug diameter of 0.14 μm. In this case, the plug of the first interlayer insulating film and the second interlayer insulating film penetrates once, and the aspect ratio becomes large, and the high resistance of the plug is highlighted as a problem.

Therefore, the plug diameter is reduced together, and the wiring HL1 as the source wiring or the drain wiring is formed on the first interlayer insulating film. As a result, even if the plug diameter is reduced, the wiring HL1 is formed on the first interlayer insulating film, so that the aspect ratio of the plug PLG1 can be reduced, and the high resistance of the plug PLG1 can be suppressed. In short, a plug that penetrates the first interlayer insulating film and the second interlayer insulating film is not formed at one time, and by interposing the wiring HL1 on the first interlayer insulating film, only the first interlayer insulating film can be formed. Plug PLG1. Then, in order to reduce the aspect ratio of the plug PLG1, the first layer is implemented. The interlayer insulating film is thinned. Further widening the wiring width of the wiring HL1 formed on the first interlayer insulating film, and connecting the wiring HL1 formed on the first interlayer insulating film to the second interlayer insulating film by a plurality of rows of plugs The wiring is configured to reduce the resistance of the plug and the wiring. In other words, since the gate electrode 10b of the high withstand voltage MISFET has a large gate length (gate width) of about 2 μm to 3 μm, it overlaps with the gate electrode 10b of the high withstand voltage MISFET in plan view. In this manner, the wiring HL1 is formed on the first interlayer insulating film.

However, when the wiring HL1 is formed on the first interlayer insulating film in such a manner as to overlap the gate electrode 10b of the high withstand voltage MISFET in a plan view, the gate electrode 10b and the constituent source of the high withstand voltage MISFET are formed. A breakdown voltage may occur between the wiring HL1 of the pole wiring or the drain wiring. In addition to thinning the film thickness of the first interlayer insulating film, a high withstand voltage MISFET can be used as the cause of the breakdown voltage. As described above, the gate electrode 10b is placed on the electric field protruding from the semiconductor substrate 1S. The insulating region 3 is relaxed, and the film thickness of the gate insulating film 8 is increased. As a result, it is considered that the distance between the wiring HL1 having the overlap in the plan view and the gate electrode of the high withstand voltage MISFET is close to cause a breakdown voltage. Further, it is judged that the high withstand voltage MISFET has a high driving voltage of 20 V to 30 V.

Therefore, the present embodiment is formed on the first interlayer insulating film to form the wiring HL1 as the source wiring or the drain wiring, and the gate electrode 10b of the wiring HL1 and the high withstand voltage MISFET is in plan view. The wiring HL1 is configured in a non-overlapping manner. Thereby, even if the semiconductor wafer as the LCD driver is miniaturized, the source region of the connection with the high withstand voltage MISFET can be reduced or The aspect ratio of the pole region to the plug PLG1 of the wiring HL1. In short, since the wiring HL1 is formed on the first interlayer insulating film, the plug which penetrates the first interlayer insulating film and the second interlayer insulating film at one time is not formed, and only the first interlayer insulating film can be formed. Plug PLG1. Therefore, even if the diameter of the plug PLG1 is reduced, the aspect ratio of the plug PLG1 can be suppressed from becoming large.

Further, as shown in FIG. 2, the wiring HL1 formed on the first interlayer insulating film is disposed so as not to overlap with the gate electrode 10b of the high withstand voltage MISFET. Thereby, since the wiring HL1 is not formed directly above the gate electrode 10b of the high withstand voltage MISFET, even if the first interlayer insulating film is thinned, the distance between the wiring HL1 and the gate electrode 10b can be pulled apart. . Therefore, the withstand voltage of the gate electrode 10b of the high withstand voltage MISFET and the wiring HL1 which is the source wiring or the gate wiring can be ensured. In other words, according to the present embodiment, it is possible to suppress the high resistance of the plug due to the miniaturization of the semiconductor device, and it is possible to improve the breakdown voltage between the gate electrode and the wiring of the high withstand voltage MISFET. effect.

For example, the high withstand voltage MISFET is formed by the thinning of the first interlayer insulating film or the thickening of the gate insulating film, the presence of the insulating region for electric field relaxation, or the high voltage of the driving voltage, which is likely to be formed between the first layers. A structure in which the breakdown voltage between the wiring (source wiring or the drain wiring) HL1 of the insulating film and the gate electrode 10b is poor. However, the wiring HL1 and the gate electrode 10b which are formed in the first interlayer insulating film are not overlapped in a plan view, and the wiring HL1 can be formed on the first interlayer insulating film, and the wiring HL1 can be pulled apart. The distance from the gate electrode 10b. Therefore, even if the LCD driver is miniaturized, the high resistance of the plug can be suppressed, and the high withstand voltage can be obtained. A significant effect of the breakdown voltage between the gate electrode of the MISFET and the wiring.

Further, by arranging the wiring HL1 and the gate electrode 10b formed in the first interlayer insulating film so as not to overlap in a plan view, the effects shown below can be obtained. In other words, since the first interlayer insulating film in which the wiring HL1 is disposed is formed into a thin film, the interface between the gate insulating film HL1 and the gate insulating film of the high withstand voltage MISFET and the semiconductor substrate 1S is a channel region. When the wiring HL1 and the gate electrode 10b are arranged to overlap each other in a plan view, the wiring HL1 and the channel region of the high withstand voltage MISFET overlap in a plan view. At this time, when a high voltage is applied to the wiring HL1, since the first interlayer insulating film is thinned, the wiring HL1 functions as a gate electrode. In short, the wiring HL1 has a region overlapping the channel region in a plan view, and if the distance between the wiring HL1 and the channel region becomes close, the voltage applied to the wiring HL1 overlaps the wiring HL1 in a plan view. The area will be reversed. In other words, the region overlapping the wiring HL1 in plan view in the entire channel region is in an inverted state. Therefore, even when the high withstand voltage MISFET is turned off, the wiring HL1 and the region overlapping in the plan view in the plan view are reversed, and the distance of the substantially unreversed channel region is narrowed. As a result, the problem of the withstand voltage between the source region and the drain region is reduced.

However, in the present embodiment, the wiring HL1 is disposed so as not to overlap the gate electrode 10b in plan view. Therefore, the wiring HL1 is disposed so as not to overlap with the channel region formed directly under the gate electrode 10b, and does not overlap in plan view. Therefore, it is possible to suppress the wiring HL1 from functioning as a gate electrode. In summary, according to this embodiment, the occurrence of the parasitic MISFET caused by the wiring HL1 can be prevented, and the effect of suppressing the withstand voltage between the source region and the drain region can be obtained. fruit.

Fig. 3 is a plan view of the high withstand voltage MISFET formation region shown in Fig. 2 as viewed from above. The section cut by the line A-A in Fig. 3 corresponds to the high withstand voltage MISFET formation region of Fig. 2. As shown in FIG. 3, on both sides of the gate electrode 10b, a high-concentration impurity diffusion region 14 for high withstand voltage as a source region or a drain region is formed, and a high-concentration impurity diffusion region 14 and a gate for high withstand voltage are formed. An electric field relaxation insulating region 3 is formed between the electrode electrodes 10b. On the high withstand voltage MISFET thus constructed, a first interlayer insulating film (not shown) is interposed to form a wiring. Specifically, the wiring HL1 is formed by interposing a plug (first plug or second plug) PLG1 on the high-concentration impurity diffusion region 14 for high withstand voltage as the source region or the drain region. As can be seen from FIG. 3, the wiring HL1 is disposed so as not to overlap with the gate electrode 10b in a plan view, and the gate electrode 10b is separated from the wiring HL1 by a distance. Therefore, it is understood that the withstand voltage between the gate electrode 10b and the wiring HL1 is ensured.

On the other hand, the gate wiring GL is connected to the gate electrode 10b via the plug (third plug) PLG1. The gate wiring GL is formed of a wiring in the same layer as the wiring HL1 constituting the source wiring or the gate wiring. That is, the gate wiring GL is formed on the first interlayer insulating film. As shown in FIG. 3, the gate wiring GL is disposed in a region overlapping the gate electrode 10b in a plan view. In short, the gate wiring GL and the gate electrode 10b are electrically connected via the plug (third plug) PLG1, and the problem of withstand voltage between the gate electrode 10b and the gate wiring GL does not occur. As described above, in the present embodiment, the purpose is to ensure the withstand voltage of the wiring formed on the first interlayer insulating film and the gate electrode 10b. Then, the problem with the breakdown voltage of the gate electrode 10b is formed on the first layer. In the wiring of the interlayer insulating film, a source wiring electrically connected to a source region of the high withstand voltage MISFET or a drain wiring electrically connected to a drain region of the high withstand voltage MISFET. In short, the feature is that the gate electrode 10b is not overlapped with the wiring HL1 as the source wiring or the drain wiring, and the gate wiring GL and the gate electrically connected to the gate electrode 10b are disposed. The pole electrode 10b may overlap in a plan view.

Here, the present embodiment is characterized in that the wiring HL1 formed in the first interlayer insulating film and the gate electrode 10b of the high withstand voltage MISFET are not overlapped in plan view. At this time, the wiring HL1 formed in the first interlayer insulating film may be referred to as the lowermost wiring. However, in the case where the wiring is formed in the first interlayer insulating film and the wiring is formed in the second interlayer insulating film, the wiring formed in the second interlayer insulating film may also be referred to as the lowermost wiring. Further, even in the case of the second interlayer insulating film, since the wiring is not formed on the first interlayer insulating film, the first interlayer insulating film and the second interlayer insulating film may be combined and referred to as one interlayer. Insulating film. Therefore, in order to specify the wiring HL1 as the object in the present embodiment, some definition is required.

Explain about this definition. This embodiment is problematic in that the first interlayer insulating film is thinned, and the first interlayer insulating film is thinned, and the wiring HL1 and the gate electrode 10b formed in the first interlayer insulating film are formed. The withstand voltage becomes a problem. Therefore, the wiring HL1 formed on the first interlayer insulating film is defined as follows.

As shown in FIG. 2, the distance from the interface between the semiconductor substrate 1S and the gate insulating film 8 to the upper portion of the gate electrode 10b is a, from the upper portion of the gate electrode 10b to the interlayer insulating film on which the wiring HL1 is formed. The upper distance is set to b, then The wiring HL1 of a>b is defined as the wiring as the object in the embodiment. In short, the premise is that the breakdown voltage between the wiring HL1 and the gate electrode 10b is a problem, focusing on the point at which the first interlayer insulating film is thinned, and the gate insulating film 8 of the high withstand voltage MISFET is thick, and The gate electrode 10b is placed at the point of the electric field relaxation insulating region 3. Thereby, it is possible to clearly define the wiring HL1 disposed between the gate electrodes 10b and having a breakdown voltage failure.

Specifically, in the high withstand voltage MISFET, the relationship of a>b is established by numerical examples. First, in the interlayer insulating film, the film thickness of the tantalum nitride film 16 is about 50 nm, and the film thickness of the tantalum oxide film 17 is about 500 nm. Then, the gate insulating film 8 of the high withstand voltage MISFET has a film thickness of about 80 nm, and the gate electrode 10b has a film thickness of about 250 nm. Therefore, the distance a from the interface between the semiconductor substrate 1S and the gate insulating film 8 to the upper portion of the gate electrode 10b is about 330 nm (80 nm + 250 nm). On the other hand, the distance b from the upper portion of the gate electrode 10b to the upper portion of the interlayer insulating film on which the wiring HL1 is formed is about 220 nm (550 nm - 330 nm). Therefore, it can be seen that the relationship of a>b is established. Further, since the electric field relaxation insulating region 3 protrudes from the semiconductor substrate 1S by about 10 nm to 20 nm, it is further understood that the relationship of a>b is satisfied. As described above, in the present embodiment, the withstand voltage between the gate electrode 10b and the wiring HL1 poses a problem. However, the problem of the breakdown voltage is clarified, and the positional relationship between the wiring HL1 and the high withstand voltage MISFET becomes a. >b wiring. Therefore, although not shown in FIG. 2, the wiring formed on the interlayer insulating film of the second layer or more is not the relationship of a>b, and therefore is not the object of this embodiment. That is, the wiring on the interlayer insulating film formed on the second layer or more is due to the gate electrode of the high withstand voltage MISFET The distance of 10b is sufficiently separated, so that the withstand voltage does not pose a problem. Therefore, the wiring (source wiring or drain wiring) formed on the interlayer insulating film of the second layer or more does not pose a problem even if it is disposed so as to overlap the gate electrode 10b in plan view. By arranging the wiring formed on the interlayer insulating film of the second layer or more and overlapping the gate electrode 10b in plan view, the wiring can be efficiently arranged. In particular, in the high withstand voltage MISFET, since the gate electrode of the gate electrode 10b is as long as 2 μm to 3 μm, the wiring formed on the interlayer insulating film of the second layer or more is disposed so as to be in contact with the gate electrode 10b. Overlapping is useful when looking down.

Next, the wiring structure of the low withstand voltage MISFET will be described. As shown in FIG. 2, a first interlayer insulating film is formed on the low withstand voltage MISFET. Specifically, the first interlayer insulating film is formed of a laminated film of the tantalum nitride film 16 and the hafnium oxide film 17. Then, a first interlayer insulating film composed of the tantalum nitride film 16 and the tantalum oxide film 17 is formed, and a plug PLG1 penetrating through the interlayer insulating film and reaching the source region of the low withstand voltage MISFET is formed, and the interlayer insulating film is penetrated therethrough. And reaches the plug PLG1 of the drain region of the low withstand voltage MISFET. Then, a wiring (source wiring, drain wiring) LL1 is formed on the first interlayer insulating film on which the plug PLG1 is formed. Further, although the wiring LL1 is formed on the first interlayer insulating film, a second interlayer insulating film or a third interlayer insulating film is further formed on the first interlayer insulating film including the wiring LL1. A wiring is formed on each of the interlayer insulating films. That is, a multilayer wiring is formed on the low withstand voltage MISFET, but only the wiring LL1 of the first layer is illustrated in FIG.

Here, the low withstand voltage MISFET is different from the high withstand voltage MISFET, the first layer The wiring LL1 is arranged to overlap the gate electrode 10a of the low withstand voltage MISFET in plan view. That is, in the low withstand voltage MISFET, the withstand voltage between the wiring LL1 of the first layer and the gate electrode 10a is different from that of the high withstand voltage MISFET, and does not pose a problem.

The reason why the low breakdown voltage MISFET is first is that the gate insulating film 7 has a thin film thickness and the electric field relaxation insulating region 3 is not formed. Therefore, the gate electrode 10a does not rest on the electric field relaxation insulating region 3. Further, the drive voltage of the low withstand voltage MISFET is about 5 V to 6 V, and the high withstand voltage MISFET having a drive voltage of 20 V to 30 V is easy to ensure the withstand voltage. Therefore, the wiring (source wiring or drain wiring) LL1 formed on the first interlayer insulating film and the gate electrode 10a may overlap in a plan view. Thereby, since the gate electrode of the gate electrode 10a of the low withstand voltage MISFET is about 160 nm long, the space on the gate electrode 10a can be effectively utilized.

Further, as a low-withstand voltage MISFET, the factor of the withstand voltage can be ensured, and the distance from the interface between the semiconductor substrate 1S and the gate insulating film 7 to the upper portion of the gate electrode 10a is c, from the upper portion of the gate electrode 10a. The distance from the upper portion of the interlayer insulating film on which the wiring LL1 is formed is d, and c<d is exemplified. That is, the relationship between the high withstand voltage MISFET (a>b) is not established in the low withstand voltage MISFET, and the distance between the gate electrode 10a and the wiring LL1 can be ensured, resulting in the low withstand voltage MISFET, the gate electrode 10a and the wiring The pressure tolerance of LL1 does not pose a problem.

Specifically, it will be described by numerical examples. For example, in the interlayer insulating film, the film thickness of the tantalum nitride film 16 is about 50 nm, and the film thickness of the tantalum oxide film 17 is about 500 nm. Then, the gate insulating film 7 of the low withstand voltage MISFET has a film thickness of about 13 nm, and the gate is The film thickness of the electrode 10a is about 250 nm. Therefore, the distance c from the interface between the semiconductor substrate 1S and the gate insulating film 7 to the upper portion of the gate electrode 10a is about 263 nm (13 nm + 250 nm). On the other hand, the distance d from the upper portion of the gate electrode 10a to the upper portion of the interlayer insulating film on which the wiring LL1 is formed is about 287 nm (550 nm - 263 nm). Therefore, it can be seen that the relationship of c<d is established. That is, the low withstand voltage MISFET is different from the high withstand voltage MISFET in that the distance d from the upper portion of the gate electrode 10a to the wiring LL1 is larger than the distance c from the lower portion of the gate insulating film 7 to the upper portion of the gate electrode 10a. Since the driving voltage is low, even if the gate electrode 10a and the wiring LL1 have a region overlapping in a plan view, a breakdown voltage does not occur.

As described above, the present embodiment is characterized in that the wiring HL1 as the source wiring or the drain wiring is formed on the first interlayer insulating film in the high breakdown voltage MISFET formation region, and the wiring HL1 and the wiring are high. The gate electrode 10b of the withstand voltage MISFET is arranged such that the gate electrode HL1 does not overlap in a plan view. As a result, it is possible to suppress the high resistance of the plug due to the miniaturization of the LCD driver, and it is possible to obtain a remarkable effect of improving the withstand voltage between the gate electrode of the high withstand voltage MISFET and the wiring.

The LCD driver (semiconductor device) of this embodiment is configured as described above, and a method of manufacturing the same will be described below with reference to the drawings.

First, a semiconductor substrate 1S composed of a single crystal having a p-type impurity such as boron (B) is introduced. At this time, the semiconductor substrate 1S is in a state of a semiconductor wafer having a substantially disk shape. Then, as shown in FIG. 4, the element isolation region 2 separating the low withstand voltage MISFET formation region of the semiconductor substrate 1S and the high withstand voltage MISFET formation region is formed. The component separation area 2 is used to make the component not Set to interfere with each other. The element isolation region 2 can be formed by, for example, a LOCOS (local Oxidation of silicon) method or an STI (shallow trench isolation) method. For example, in the STI method, the element isolation region 2 is formed as follows. That is, on the semiconductor substrate 1S, the element isolation trench is formed using photolithography and etching techniques. Then, a ruthenium oxide film is formed on the semiconductor substrate 1S by means of a buried component isolation trench, and then the ruthenium oxide formed on the semiconductor substrate 1S is removed by chemical mechanical polishing (CMP) membrane. Thereby, the element isolation region 2 in which the hafnium oxide film is buried can be formed only in the element isolation trench.

In the present embodiment, the electric field relaxation insulating region 3 is also formed in the step of forming the element isolation region 2. The electric field relaxation insulating region 3 is formed in the same manner as the element isolation region 2, and is formed, for example, by an STI method or a selective oxidation method (LOCOS method). This electric field relaxation insulating region 3 is formed in a high withstand voltage MISFET formation region. In particular, in the high-withstand voltage MISFET formation region, since the electric field relaxation insulating region 3 is formed, the occupation ratio of the element isolation region 2 and the electric field relaxation insulating region 3 becomes large. Therefore, when the element isolation region 2 and the electric field relaxation insulating region 3 are formed by the STI method, the element isolation region 2 and the electric field relaxation insulating region 3 easily protrude from the surface of the semiconductor substrate 1S in the high withstand voltage MISFET formation region. In short, the element isolation region 2 and the electric field relaxation insulating region 3 are formed so as to protrude from the surface of the semiconductor substrate 1S by, for example, 10 nm to 20 nm. As will be described later, in the high withstand voltage MISFET, since the end portion of the 12 electrode is formed on the electric field relaxation insulating region 3, the end portion of the gate electrode is placed on the protruding electric field relaxation insulating region 3 The way it is formed. In particular, in the LOCOS method (selective oxidation method), since the selective oxide film is formed so as to bulge from the surface of the semiconductor substrate 1S, the amount of the gate electrode is also increased.

Next, as shown in FIG. 5, impurities are introduced into the active region separated by the element isolation region 2 to form a p-type well 4. The p-type well 4 is formed by introducing a p-type impurity such as boron into the semiconductor substrate 1S by ion implantation. The p-type well 4 is a well for a high withstand voltage MISFET, but is formed in a high withstand voltage MISFET formation region and a low withstand voltage MISFET formation region. Then, a semiconductor region (not shown) for channel formation is formed in the surface region of the p-type well 4. The semiconductor region for forming the channel is formed by adjusting the threshold voltage of the formed channel. Further, in the present embodiment, the p-type well 4 having the high withstand voltage MISFET formation region and the low withstand voltage MISFET formation region is formed in the same step, but it may be formed in an individual step. In this case, the impurity concentration introduced into the high withstand voltage MISFET formation region and the impurity concentration introduced into the low withstand voltage MISFET formation region can be formed under optimum conditions.

Next, as shown in FIG. 6, the p-type well 5 is formed in the low withstand voltage MISFET formation region. The p-type well 5 is formed by introducing a p-type impurity such as boron into the semiconductor substrate 1S by ion implantation. This p-type well 5 is a well for a low withstand voltage MISFET. Thereafter, a pair of low-concentration impurity diffusion regions 6 for high withstand voltage are formed in the high withstand voltage MISFET formation region. The low-concentration impurity diffusion region 6 for high withstand voltage is an n-type semiconductor region, and is formed by introducing an n-type impurity such as phosphorus (P) or arsenic (As) into the semiconductor substrate 1S by ion implantation. The low-concentration impurity diffusion region 6 for high withstand voltage is formed so as to encapsulate the insulating region 3 for electric field relaxation.

Next, as shown in FIG. 7, gate insulating is formed on the semiconductor substrate 1S. membrane. At this time, a thin gate insulating film 7 is formed in the low withstand voltage MISFET formation region, and a thick gate insulating film 8 is formed in the high withstand voltage MISFET formation region. For example, the gate insulating film 7 formed in the low breakdown voltage MISFET formation region has a film thickness of about 13 nm, and the gate insulating film 8 formed in the high withstand voltage MISFET formation region has a film thickness of about 80 nm. In order to form a gate insulating film having a film thickness different depending on the region, for example, a thick gate insulating film 8 is formed on the semiconductor substrate 1S, and a high withstand voltage MISFET forming region is masked with a resist film. Then, by etching with the resist film as a mask, the thickness of the gate insulating film 8 of the exposed low breakdown voltage MISFET formation region is reduced, and a thin gate insulating film 7 can be formed. In addition, a thin gate insulating film 7 is initially formed on the entire semiconductor substrate 1S, and a resist film is formed in the low breakdown voltage MISFET formation region. Then, by forming a thick gate insulating film 8 by the exposed high-withstand voltage MISFET formation region, a thin gate insulating film 7 can be formed in the low withstand voltage MISFET formation region, and a thick layer can be formed in the high withstand voltage MISFET formation region. The gate insulating film 8 is provided. The end portion of the gate insulating film 8 formed in the high withstand voltage MISFET formation region is formed to be placed on the electric field relaxation insulating region 3.

The gate insulating films 7, 8 are formed of, for example, a hafnium oxide film, and can be formed using, for example, a thermal oxidation method. However, the gate insulating films 7, 8 are not limited to the hafnium oxide film, and may be variously modified. For example, the gate insulating films 7 and 8 may be a hafnium oxynitride film (SiON). In other words, the structure may be such that the nitrogen is segregated at the interface between the gate insulating films 7, 8 and the semiconductor substrate 1S. Compared with the yttrium oxide film, the yttrium oxynitride film system has a high effect of suppressing the occurrence of interface state in the film or reducing the electron trap. Therefore, the heat carrier resistance of the gate insulating films 7, 8 can be improved, and the insulation resistance can be improved. Further, the ruthenium oxynitride film is less likely to penetrate impurities than the ruthenium oxide film. Therefore, by using the yttrium oxynitride film for the gate insulating films 7, 8, it is possible to suppress fluctuations in the threshold voltage due to diffusion of impurities in the gate electrode toward the semiconductor substrate 1S side. The formation of the yttrium oxynitride film may be performed by heat-treating the semiconductor substrate 1S in an atmosphere containing nitrogen such as NO, NO ₂ or NH ₃ . Further, after forming the gate insulating films 7 and 8 composed of the hafnium oxide film on the surface of the semiconductor substrate 1S, the semiconductor substrate 1S is heat-treated in a nitrogen-containing atmosphere to segregate nitrogen in the gate insulating film 7. The interface between the 8 and the semiconductor substrate 1S can also achieve the same effect.

Further, the gate insulating films 7, 8 may be formed of, for example, a high dielectric film having a dielectric constant higher than that of the hafnium oxide film. In the past, the electrical resistance from the high insulation resistance and the yttrium-yttria interface. Considering good viewpoints such as physical stability, a ruthenium oxide film is used as the gate insulating film 7,8. However, with the miniaturization of the elements, the film thickness of the gate insulating films 7, 8 is also required to be extremely thin. When such an extremely thinned hafnium oxide film is used as the gate insulating film 7, 8, a so-called channel current is generated, which is an electron flowing in the channel of the MISFET, and a barrier formed by the hafnium oxide film is used as a channel. Flow to the gate electrode.

Therefore, by using a material having a dielectric constant higher than that of the ruthenium oxide film, a high dielectric film having a physical film thickness can be used using the same capacitance. If a high dielectric film is used, the physical film thickness can be increased even if the capacitance is the same, so that the leakage current can be reduced.

For example, a high-dielectric film system uses a hafnium oxide film (HfO ₂ film) which is one of tantalum oxides, but a tantalum aluminum oxide film, an HfON film (a hafnium oxynitride film), or an HfSiO film may be used instead of the hafnium oxide film ( A ruthenium film), an HfSiON film (nitrogen oxynitride film), and other lanthanide insulating films of the HfAlO film. Further, a lanthanum-based insulating film into which an oxide such as cerium oxide, cerium oxide, titanium oxide, zirconium oxide, cerium oxide or cerium oxide is introduced may be used as the lanthanide insulating film. The lanthanum-based insulating film is the same as the yttrium oxide film, and since the dielectric constant is higher than that of the yttrium oxide film or the yttrium oxynitride film, the same effect as in the case of using the yttrium oxide film can be obtained.

Next, as shown in FIG. 8, a polysilicon film is formed on the gate insulating films 7, 8. The polysilicon film 9 can be formed using, for example, a CVD method. Then, an n-type impurity such as phosphorus or arsenic is introduced into the polysilicon film 9 by photolithography and ion implantation.

Next, the polysilicon film 9 is processed by etching using the patterned resist film as a mask, the gate electrode 10a is formed in the low withstand voltage MISFET formation region, and the gate electrode 10b is formed in the high withstand voltage MISFET formation region. . The gate electrode 10a has a gate length of, for example, about 160 nm, and the gate electrode 10b has a gate length of about 2 μm to 3 μm. The end portion of the gate electrode 10b formed in the high withstand voltage MISFET formation region is formed by interposing the gate insulating film 8 on the electric field relaxation insulating region 3.

Here, n-type impurities are introduced into the polysilicon film 9 at the gate electrodes 10a and 10b. Therefore, since the value of the work function of the gate electrodes 10a, 10b can be set to the value near the conduction band of 矽 (4.15 eV), the threshold voltage of the low-voltage MISFET and the high withstand voltage MISFET of the n-channel type MISFET can be reduced. .

Next, as shown in FIG. 9, by using the photolithography technique and the ion implantation method, the shallow layer formed in the gate electrode 10a of the low withstand voltage MISFET is integrated. The low-concentration impurity diffusion region 11 for withstand voltage. The low-concentration impurity diffusion region 11 for the shallow low withstand voltage is an n-type semiconductor region.

Then, as shown in FIG. 10, a hafnium oxide film is formed on the semiconductor substrate 1S. The hafnium oxide film can be formed using, for example, a CVD method. Then, a side wall 12 can be formed on the sidewalls of the gate electrodes 10a, 10b by anisotropically etching the hafnium oxide film. The side wall 12 is formed of a single layer film of a hafnium oxide film, but is not limited thereto. For example, the side wall 12 composed of a laminated film of a tantalum nitride film and a hafnium oxide film may be formed.

Next, as shown in FIG. 11, a low-withstand voltage high-concentration impurity diffusion region 13 integrated in the deep layer of the sidewall 12 is formed in the low-withstand voltage MISFET formation region by using the photolithography technique and the ion implantation method. The deep low-pressure high-concentration impurity diffusion region 13 is an n-type semiconductor region. The source region or the drain region of the low withstand voltage MISFET is formed by the deep low-voltage high-concentration impurity diffusion region 13 and the low-level low-voltage low-concentration impurity diffusion region 11 in the shallow layer. In this manner, the source region and the drain region can be formed by forming the source region and the drain region by using the low-concentration impurity diffusion region 11 for the low-level low withstand voltage and the high-concentration impurity diffusion region 13 for the low breakdown voltage. Made of LDD (Lightly Doped Drain) construction.

In the high-withstand voltage MISFET formation region, ion implantation of the n-type impurity forming the high-concentration impurity diffusion region 13 for low withstand voltage is simultaneously performed, and the high-concentration impurity diffusion region 14 for high withstand voltage is also formed. The high-density impurity diffusion region 14 for high withstand voltage is also an n-type semiconductor region, and is formed so as to be outside the insulating region 3 for electric field relaxation and to be enclosed in the low-concentration impurity diffusion region 6 for high withstand voltage. For high withstand voltage MISFETs, high concentration with high withstand voltage The impurity diffusion region 14 and the high-voltage low-concentration impurity diffusion region 6 form a source region or a drain region.

In this manner, after the high-concentration impurity diffusion region 13 for low withstand voltage and the high-concentration impurity diffusion region 14 for high withstand voltage are formed, heat treatment at a temperature of about 1000 ° C is performed. Thereby, the activation of the introduced impurities is performed.

Thereafter, as shown in FIG. 12, a cobalt film is formed on the semiconductor substrate 1S. At this time, a cobalt film is formed in direct contact with the gate electrodes 10a and 10b. Similarly, the cobalt film is also directly in contact with the deep high-concentration impurity diffusion region 13 for low withstand voltage and the high-concentration impurity diffusion region 14 for high withstand voltage.

The cobalt film can be formed, for example, using a sputtering method. Then, after forming a cobalt film, heat treatment is performed to cause the polysilicon film 9 constituting the gate electrodes 10a and 10b to react with the cobalt film to form a cobalt vapor film 15. Thereby, the gate electrodes 10a and 10b have a laminated structure of the polysilicon film 9 and the cobalt vapor film 15. The cobalt vapor film 15 is formed to reduce the resistance of the gate electrodes 10a and 10b. In the same manner, by the heat treatment, the surface of the high-concentration impurity diffusion region 13 for low withstand voltage and the high-concentration impurity diffusion region 14 for high withstand voltage reacts with the cobalt film to form the cobalt vapor film 15 . Therefore, in the high-concentration impurity diffusion region 13 for low withstand voltage and the high-concentration impurity diffusion region 14 for high withstand voltage, it is possible to reduce the resistance.

Then, the unreacted cobalt film is removed from the semiconductor substrate 1S. Further, in the present embodiment, the cobalt halide film 15 is formed, but for example, instead of the cobalt vapor film 15, a nickel vapor film or a titanium vapor film may be formed. In this manner, a low withstand voltage MISFET and a high withstand voltage MISFET can be formed on the semiconductor substrate 1S.

Next, the wiring steps will be explained. First, as shown in FIG. 13, a tantalum nitride film 16 as an interlayer insulating film is formed on the main surface of the semiconductor substrate 1S, and a tantalum oxide film 17 is formed on the tantalum nitride film 16. Thereby, the first interlayer insulating film serves as a laminated film of the tantalum nitride film 16 and the hafnium oxide film 17. The tantalum nitride film 16 can be formed using, for example, a CVD method, and the hafnium oxide film 17 can be formed by a CVD method using, for example, TEOS (tetra ethyl ortho silicate: tetraethyl decane) as a raw material. At this time, the film thickness of the tantalum nitride film 16 is about 50 nm, and the film thickness of the hafnium oxide film 17 is about 1100 nm.

Thereafter, as shown in FIG. 14, the surface of the ruthenium oxide film 17 is planarized by, for example, CMP (Chemical Mechanical Polishing). At this step, the film thickness of the ruthenium oxide film 17 is reduced to about 550 nm, for example. Thus, the film thickness of the yttrium oxide film 17 is thinned.

Next, as shown in FIG. 15, a contact hole CNT1 is formed in the hafnium oxide film 17 using a photolithography technique and an etching technique. The contact hole CNT1 penetrates through the first interlayer insulating film composed of the hafnium oxide film 17 and the tantalum nitride film 16, and reaches the semiconductor substrate 1S. Specifically, the contact hole CNT1 is formed in the high withstand voltage MISFET formation region and the low withstand voltage MISFET formation region. In the high withstand voltage MISFET formation region, a contact hole (first contact hole) CNT1 reaching the source region (cobalt telluride film 15) is formed, and a contact hole reaching the drain region (cobalt telluride film 15) is formed (second Contact hole) CNT1. Further, although not shown in Fig. 15, a contact hole reaching the gate electrode 10b is also formed. Similarly, in the low breakdown voltage MISFET formation region, the contact hole CNT1 reaching the source region (cobalt telluride film 15) is formed, and the contact hole CNT1 reaching the drain region (cobalt telluride film 15) is formed. In addition, although not shown, the gate is also formed. Contact hole of the electrode 10a.

Next, as shown in FIG. 16, a titanium/titanium nitride film 18a is formed on the tantalum oxide film 17 including the bottom surface and the inner wall of the contact hole CNT1. The titanium/titanium nitride film 18a is composed of a laminated film of a titanium film and a titanium nitride film, and can be formed by, for example, sputtering. The titanium/titanium nitride film 18a has a so-called barrier property, which prevents, for example, tungsten which is deposited in a subsequent step from being diffused into the crucible. Thereafter, a tungsten film 18b is formed on the entire surface of the main surface of the semiconductor substrate 1S so as to fill the contact hole CNT1. The tungsten film 18b can be formed using, for example, a CVD method.

Next, as shown in FIG. 17, the titanium/titanium nitride film 18a and the tungsten film 18b which are formed on the hafnium oxide film 17 are removed by, for example, a CMP method, and the titanium/titanium nitride film remains only in the contact hole CNT1. 18a and a tungsten film 18b, whereby the plug PLG1 can be formed. The yttrium oxide film 17 is cut by CMP polishing at this time. Specifically, the film thickness of the yttrium oxide film 17 is about 550 nm before CMP polishing, and the film thickness of the yttrium oxide film 17 after CMP polishing is about 500 nm.

a plug (first plug) PLG1 electrically connected to a source region of the high withstand voltage MISFET or a plug electrically connected to a drain region of the high withstand voltage MISFET in the high withstand voltage MISFET formation region (second Plug) PLG1. Although not shown, a plug (third plug) electrically connected to the gate electrode 10b is also formed. Similarly, in the low withstand voltage MISFET formation region, a plug PLG1 electrically connected to the source region of the low withstand voltage MISFET or a plug PLG1 electrically connected to the drain region of the low withstand voltage MISFET is formed. Further, although not shown, a plug electrically connected to the gate electrode 10a is also formed.

Next, as shown in FIG. 18, a titanium/titanium nitride film 19a, a copper-containing aluminum film 19b, and a titanium/titanium nitride film are sequentially formed on the hafnium oxide film 17 and the plug PLG1. 19c. These films can be formed by using, for example, sputtering. Next, patterning of the films is performed by using a photolithography technique and an etching technique to form wirings HL1 and LL1. In this manner, the wiring HL1 and the wiring LL1 can be formed on the first interlayer insulating film.

Since the wiring HL1 and the wiring LL1 are formed on the first interlayer insulating film, the aspect ratio of the plug PLG1 connected to the wiring HL1 and the wiring LL1 can be reduced. Therefore, even if the diameter of the plug PLG1 is reduced to reduce the miniaturization of the wafer region, the increase in resistance of the plug PLG1 can be suppressed. Further, in the present embodiment, the wiring (source wiring) HL1 connected to the source region of the high withstand voltage MISFET via the plug PLG1 and the high-voltage MISFET via the plug PLG1 are disposed as follows. Wiring of the pole area (bungee wiring) HL1. In short, the wiring HL1 and the gate electrode 10b disposed on the first interlayer insulating film are disposed so as not to overlap in a plan view. Thereby, since the wiring HL1 is not formed directly above the gate electrode 10b of the high withstand voltage MISFET, even if the first interlayer insulating film is thinned, the distance between the wiring HL1 and the gate electrode 10b can be pulled apart. Therefore, the withstand voltage of the gate electrode 10b of the high withstand voltage MISFET and the wiring HL1 which is the source wiring or the gate wiring can be ensured. In other words, according to the present embodiment, it is possible to suppress the high resistance of the plug due to the miniaturization of the semiconductor device, and it is possible to obtain a remarkable effect of improving the withstand voltage between the gate electrode of the high withstand voltage MISFET and the wiring. .

Further, although not shown, a gate wiring electrically connected to the gate electrode 10b is also formed on the first interlayer insulating film. In other words, the gate wiring is also formed in the same layer as the wiring HL1 constituting the source wiring or the drain wiring. Since the gate wiring is electrically connected to the gate electrode 10b, the gate wiring and the gate are The withstand voltage between the electrode electrodes 10b does not pose a problem. Therefore, the gate wiring is disposed to overlap the gate electrode 10b in plan view.

On the other hand, in the low withstand voltage MISFET formation region, the wiring LL1 is formed on the first interlayer insulating film. In the low withstand voltage MISFET, since the withstand voltage between the wiring LL1 and the gate electrode 10a does not pose a problem, the wiring LL1 has a wide wiring width so as to overlap the gate electrode 10a in plan view. Thereby, the space on the gate electrode 10a can be effectively utilized, and the resistance of the wiring LL1 can be reduced.

Next, as shown in FIG. 19, a ruthenium oxide film 20 of a second interlayer insulating film is formed on the first interlayer insulating film on which the wiring HL1 and the wiring LL1 are formed. Then, as in the above steps, the plug PLG2 is formed on the ruthenium oxide film 20. The plug PLG2 is connected to the wiring HL1 and the wiring LL1. Then, on the ruthenium oxide film 20 on which the plug PLG2 is formed, the wiring HL2 and the wiring LL2 are formed. Here, since the wiring HL1 and the wiring HL2 are connected by the plug PLG2 of a plurality of rows, the wiring resistance and the plug resistance can be reduced. Similarly, since the wiring LL1 and the wiring LL2 are connected by the plug PLG2 of a plurality of rows, the wiring resistance and the plug resistance can be reduced.

In the high withstand voltage MISFET formation region, the wiring HL2 formed on the tantalum oxide film 20 of the second interlayer insulating film may be disposed to overlap the gate electrode 10b in plan view. This is because the wiring HL2 and the gate electrode 10b disposed on the second interlayer insulating film are sufficiently separated from the gate electrode 10b by the distance between the wiring HL1 disposed on the first interlayer insulating film, and thus the wiring HL2. The withstand voltage between the gate electrode 10b does not pose a problem. Therefore, as the gate length, the space on the gate electrode 10b of about 2 μm to 3 μm can be effectively utilized, and the space is enlarged. The wiring of the wiring HL2 is wide, whereby the wiring HL2 can be made low in resistance. Further, in the second interlayer insulating film, a plurality of wirings may be disposed in a region overlapping the gate electrode 10b in a plan view.

Further, wiring is formed by the upper layer of the wiring HL2 and the wiring LL2 to form a multilayer wiring. Then, bump electrodes are formed on the uppermost layer of the multilayer wiring. The step of forming the bump electrode will be described.

Fig. 20 shows a ruthenium oxide film 21 formed on a multilayer wiring, and a pad PAD is formed on the ruthenium oxide film 21. Although the lower layer structure of the hafnium oxide film 21 is omitted, a low breakdown voltage MISFET, a high withstand voltage MISFET, and a multilayer wiring as shown in FIG. 19 are formed under the hafnium oxide film 21.

As shown in FIG. 20, for example, a ruthenium oxide film 21 is formed. The hafnium oxide film 21 can be formed using, for example, a CVD method. Then, a titanium/titanium nitride film, an aluminum film, and a titanium/titanium nitride film are laminated on the hafnium oxide film 21. Thereafter, the laminated film is patterned using photolithography and etching techniques. By this patterning, the pad PAD can be formed on the yttrium oxide film 21.

Next, as shown in FIG. 21, a surface protective film 22 is formed on the ruthenium oxide film 21 on which the pad PAD is formed. The surface protective film 22 is formed of, for example, a tantalum nitride film, and can be formed by, for example, a CVD method. Next, an opening portion is formed in the surface protective film 22 by using a photolithography technique and an etching technique. The opening is formed on the pad PAD and exposes the surface of the pad PAD.

Next, as shown in FIG. 22, a UBM (Under Bump Metal) film 23 is formed on the surface protective film 22 including the opening. The UBM film 23 can be formed using, for example, a sputtering method by, for example, a titanium film, a nickel film, a palladium film, or titanium. Single layer film or stack of tungsten alloy film, titanium nitride film or gold film A film is formed. Here, the UBM film 23 has a function of lifting the adhesion between the bump electrode and the pad PAD or the surface protective film 22, or functions as an electrode, and has a barrier function, which suppresses or prevents the formation of the subsequent steps. The metal element of the conductor film moves toward the multilayer wiring side, or conversely, the metal element constituting the multilayer wiring moves toward the conductor film side.

Next, as shown in FIG. 23, after the resist film RES is applied on the UBM film 23, exposure is performed on the resist film RES. Development processing is performed to pattern. The patterning is performed so that the resist film RES does not remain in the bump electrode formation region. Then, as shown in FIG. 24, a gold film is formed as the conductor film 24 by, for example, electroplating. Thereafter, as shown in FIG. 25, the bump electrode BMP composed of the conductor film 24 and the UBM film 23 is formed by removing the patterned resist film RES and the UBM film 23 covering the resist film RES. .

Next, the diced semiconductor wafer CHP can be obtained by dicing the semiconductor substrate in the state of the semiconductor wafer. The semiconductor wafer CHP obtained by chip formation is shown in FIG. Thereafter, the semiconductor wafer CHP obtained by dicing the semiconductor substrate is mounted on the glass substrate.

Next, the state in which the semiconductor wafer CHP of the LCD driver is adhered and mounted on the mounting substrate is shown. Fig. 26 shows a case where a semiconductor wafer CHP is mounted on a glass substrate 30a (COG: Chip On Glass). As shown in FIG. 26, the glass substrate 30b is mounted on the glass substrate 30a, and the display part of an LCD is formed. Then, a semiconductor wafer CHP of an LCD driver is mounted on the glass substrate 30a in the vicinity of the display portion of the LCD. A bump electrode BMP is formed on the semiconductor wafer CHP, and is formed on the bump electrode BMP and the glass. The terminals on the substrate 30a are connected via an anisotropic conductive film 32. Further, the glass substrate 30a and the flexible printed circuit (flexible printed circuit) 31 are also connected by an anisotropic conductive film. In the semiconductor wafer CHP mounted on the glass substrate 30a, the output bump electrode BMP is electrically connected to the display portion of the LCD, and the input bump electrode BMP is connected to the flexible printed circuit board 31.

Fig. 27 is a view showing the overall structure of the LCD. As shown in FIG. 27, the display portion 33 of the LCD is formed on the glass substrate, and an image is displayed on the display portion 33. A semiconductor wafer CHP of an LCD driver is mounted on a glass substrate in the vicinity of the display unit 33. The flexible printed circuit board 31 is mounted in the vicinity of the semiconductor wafer CHP, and the semiconductor wafer CHP of the LCD driver is mounted between the flexible printed circuit board 31 and the display portion 33 of the LCD. In this manner, the semiconductor wafer CHP can be mounted on a glass substrate. By the above steps, the LCD driver can be mounted on a glass substrate to manufacture an LCD.

(implementation type 2)

One of the features of the first embodiment is that, as shown in FIG. 28, a wiring HL1 as a source wiring or a drain wiring is formed on the first interlayer insulating film (yttrium oxide film 17), and the wiring is The line HL1 and the gate electrode 10b of the high withstand voltage MISFET are arranged such that the wiring HL1 does not overlap in a plan view. Fig. 28 shows a distance e between the gate electrode 10b of the high withstand voltage MISFET and the wiring HL1 which does not overlap in plan view. In the second embodiment, a specific numerical example of the distance e will be described.

Figure 28 is a cross-sectional view showing a high withstand voltage MISFET and a low withstand voltage MISFET, It is the same as that of Fig. 2. In addition, FIG. 28 shows a distance e between the gate electrode 10b of the high withstand voltage MISFET and the wiring HL1 which does not overlap in plan view, and the diameter z of the plug PLG1.

As shown in FIG. 28, the gate electrode 10b of the high withstand voltage MISFET is separated from the wiring HL1 by a distance e from the top view, but the distance e must take into account the dimensional error of the pattern formed by the photolithography step or the alignment deviation of the pattern. Decide. This is because, for example, even if a sufficient distance e is set in order to ensure the withstand voltage of the gate electrode 10b and the wiring HL1, it is judged that there may be a dimensional error due to the processing of the gate electrode 10b or the wiring HL1, or The gate electrode 10b is offset from the plug PLG1, or the alignment between the plug PLG1 and the wiring HL1 is shifted, and the gate electrode 10b and the wiring HL1 are processed to overlap each other in plan view. In this case, the withstand voltage between the gate electrode 10b and the wiring HL1 cannot be ensured.

Therefore, it is necessary to set the distance e such that the distance between the gate electrode 10b and the wiring HL1 does not overlap in the plan view can be ensured even if the dimensional error of the pattern in the photolithography step or the alignment deviation of the pattern is generated. .

Fig. 29 is a view specifically showing the dimensional error of the pattern of the photolithography step or the alignment deviation between the patterns. For example, in FIG. 29, it is understood that when the gate electrode 10b is formed by the photolithography step, the size error (deviation) of the gate electrode 10b is at most 40 nm. Further, the alignment deviation (overlap deviation, deviation) of the plug PLG1 with respect to the gate electrode 10b is at most 40 nm. Similarly, the dimension error of the wiring HL1 is at most 40 nm, and the overlap deviation of the wiring HL1 with respect to the plug PLG1 is at most 70 nm. Therefore, the dimensional error and the overlap deviation all go to the direction of the distance e between the narrow gate electrode 10b and the wiring HL1 which does not overlap in a plan view. In the case of action, it will become the error of the narrowest distance e.

In summary, when the distance e is below 190 nm (40 nm+40 nm+40 nm+70 nm), the size error of the pattern according to the photolithography step and the overlap deviation between the patterns are formed as the gate electrode 10b and the wiring. The HL1 has an overlapping area in a plan view. As a result, a state in which the withstand voltage between the gate electrode 10b and the wiring HL1 cannot be ensured is generated. In other words, when the distance e is separated by 190 nm or more, the gate electrode 10b and the wiring HL1 can be prevented from overlapping each other in a plan view, regardless of the size error of the pattern of the photolithography step or the overlap of the pattern. Therefore, by setting the distance e to 190 nm or more, even if the dimensional error of the pattern of the photolithography step or the overlap between the patterns is generated, the gate electrode 10b and the wiring HL1 can be surely prevented from overlapping in plan view. . As a result, the withstand voltage between the gate electrode 10b and the wiring HL1 can be surely improved, and the reliability of the semiconductor device can be improved.

Further, in the above description, the distance e at which the gate electrode 10b and the wiring HL1 do not overlap in a plan view is larger than the value of the pattern error of the pattern in which the photolithography step is simply added or the overlap between the patterns (190). Example of nm). Among them, since it is judged that the dimensional error of all the patterns or the overlap deviation between the patterns is generated in the direction of the narrowing distance e, the accuracy is very small. Therefore, as a method of evaluating the distance e, other methods of determining the second power can be considered. . That is, the dimensional error of the pattern of the photolithography step or the overlap deviation between the patterns is evaluated by the power of the second power. In this case, the distance e becomes √(40×40+40×40+40×40+70×70)=98 nm, and by separating the distance e by 98 nm (about 100 nm) or more, the gate electrode 10b and the wiring HL1 can be sufficiently prevented from being Overlapping when viewed from above.

(Implementation type 3)

One of the features of the first embodiment is that the wiring HL1 formed in the first interlayer insulating film (yttria film 17) and the gate electrode 10b of the high withstand voltage MISFET shown in FIG. 28 are arranged in plan view. Do not overlap. In summary, the foregoing embodiment 1 focuses on the problem caused by thinning the first interlayer insulating film, that is, focusing on the formation of the first interlayer insulating film by thinning the first interlayer insulating film. The withstand voltage of the wiring HL1 of the insulating film and the gate electrode 10b may constitute a problem. At this time, in the first embodiment, the first interlayer insulating film is quantitatively defined to be thinned.

Specifically, as shown in FIG. 28, the distance from the interface between the semiconductor substrate 1S and the gate insulating film 8 to the upper portion of the gate electrode 10b is a, from the upper portion of the gate electrode 10b to the wiring HL1. When the distance between the upper portions of the interlayer insulating film is b, the wiring HL1 of a>b is defined as the wiring to be used in the above-described embodiment 1. In short, the premise is that the breakdown voltage between the wiring HL1 and the gate electrode 10b is a problem, focusing on the point at which the first interlayer insulating film is thinned, and the gate insulating film 8 of the high withstand voltage MISFET is thick, and The gate electrode 10b is placed at the point of the electric field relaxation insulating region 3. Thereby, it is possible to clearly define the wiring HL1 disposed between the gate electrodes 10b and having a breakdown voltage failure.

In the third embodiment, the conditions for abbreviating the above a>b under other conditions will be described. First, as described above, the distance from the interface between the semiconductor substrate 1S and the gate insulating film 8 to the upper portion of the gate electrode 10b is a, from the upper portion of the gate electrode 10b to the upper portion of the interlayer insulating film on which the wiring HL1 is formed. The distance is set to b, and the condition is a>b before the present invention. Here, as other conditions, the diameter z of the plug PLG1 and the interlayer insulating film (yttria film) The relationship of the thickness f (not shown) of the 17+ tantalum nitride film 16) (f = a + b). In other words, the plug PLG1 is formed to penetrate the interlayer insulating film. However, from the viewpoint of making the plugging property of the plug PLG1 good, the aspect ratio must be equal to or less than a specific value. Here, the aspect ratio means the amount of f/z by the thickness f of the interlayer insulating film and the diameter z of the plug PLG1. This aspect ratio becomes large, and the plugging property PLG1 having a small diameter is formed corresponding to, for example, a thick interlayer insulating film, and the landfill characteristics are deteriorated. In summary, from the viewpoint of making the plugging characteristics of the plug PLG1 good, the aspect ratio must be equal to or less than a specific value. Specifically, for example, the condition can be expressed by the condition of f/z<5. In short, when the thickness f of the interlayer insulating film and the diameter z of the plug PLG1 are determined so that the aspect ratio f/z becomes 5 or less, deterioration of the filling characteristics of the plug PLG1 can be suppressed.

Here, the thickness of the interlayer insulating film f = a + b, from this formula will become a = f - b. Substituting this into a>b becomes f>2b. On the other hand, if the relationship f/z < 5 from the aspect ratio is f < 5z. Therefore, 2b<5z can be obtained from two relational expressions of f<5z and f>2b. If 2b < 5z is solved for b, b<2.5z is obtained. From the above, it can be seen that the condition of a>b is replaced by the condition that the thickness f=a+b of the interlayer insulating film and the aspect ratio f/z<5 are replaced by b<2.5z. In the case of the sentence, it is understood that the distance from the upper portion of the gate electrode 10b to the upper portion of the interlayer insulating film on which the wiring HL1 is formed is b, and the diameter of the plug PLG1 is z, and the condition of b<2.5z is The distance b from the upper portion of the gate electrode 10b to the upper portion of the interlayer insulating film on which the wiring HL1 is formed is less than 2.5 times the diameter z of the plug PLG1. In summary, the present invention is characterized in that, in the third embodiment, the distance b from the upper portion of the gate electrode 10b to the upper portion of the interlayer insulating film on which the wiring HL1 is formed is smaller than that of the plug PLG1. When the diameter z is 2.5 times, the gate electrode 10b and the wiring HL1 can be arranged so as not to overlap each other in plan view.

Further, the diameter of the plug PLG1 is set to z, and when the diameter of the plug PLG1 is the same throughout the plug PLG1, it does not pose a problem, but actually the diameter of the surface of the interlayer insulating film (yttria film 17) The largest, as the bottom of the plug PLG1 advances, the diameter becomes smaller and is formed. In this case, the problem is which diameter is the diameter z of the plug PLG1. In the third embodiment, the diameter of the bottom of the plug PLG1 is referred to as z.

(Implementation type 4)

In the above-described first embodiment, the case where the present invention is applied to a high withstand voltage MISFET will be described. However, in the present embodiment 4, the case where the present invention is applied to a resistance element will be described. That is, in the LCD driver, in addition to the low withstand voltage MISFET or the high withstand voltage MISFET, a plurality of resistance elements constituting the circuit are formed. In the resistor element, a high voltage is applied similarly to the high withstand voltage MISFET. Therefore, in the same manner as the high withstand voltage MISFET, a high voltage resistor element is used, and the withstand voltage system poses a problem.

Fig. 30 is a plan view showing a resistive element of the present embodiment 4. In FIG. 30, a gate insulating film 8 is formed on a semiconductor substrate 1S, and a polysilicon film (conductor film) 40 as a resistive element is formed on the gate insulating film 8. The polysilicon film 40 as a resistive element is connected to the wiring 43 by a plug (fourth plug) 42. On the other hand, a wiring 44 which is not connected to the resistance element is also formed.

The present embodiment 4 is characterized in that the wiring 43 and the wiring 44 formed on the polysilicon film 40 as the resistance element are applied differently from the polysilicon film 40. The potential wiring 44 is disposed so as not to overlap the polysilicon film 40 in plan view. In short, since the wiring 43 that is directly electrically connected via the polysilicon film 40 and the plug 42 is turned on, there is no problem of withstand voltage with the polysilicon film 40. Thereby, as shown in FIG. 30, the polysilicon film 40 and the wiring 43 are arranged so as to overlap in a plan view. On the other hand, the wiring 44 that is not directly electrically connected to the polysilicon film 40 and the plug 42 and is applied with a potential different from that of the polysilicon film 40 is caused to have a high potential difference with the polysilicon film 40. In this case, polycrystalline germanium is used. Between the film 40 and the wiring 44, the withstand voltage poses a problem. Therefore, the wiring 44 that is not directly electrically connected via the polysilicon film 40 and the plug 42 is disposed so as not to overlap with the polysilicon film 40 as a resistive element in plan view. According to this configuration, even when a high voltage is applied between the polysilicon film 40 as the resistance element and the wiring 44, the withstand voltage can be secured.

Figure 31 is a cross-sectional view taken along line B-B of Figure 30. In Fig. 31, a resistance element forming region is formed in such a manner as to be adjacent to a high withstand voltage MISFET formation region. Hereinafter, the structure of the resistance element formed in the resistive element formation region will be described. In FIG. 31, on the semiconductor substrate 1S, an element isolation region 2 is formed, and a film having the same film thickness as that of the gate insulating film 8 for a high withstand voltage MISFET is formed on the element isolation region 2 (referred to as gate insulation). Membrane 8). Then, a polysilicon film 40 is formed on the gate insulating film 8, and the polysilicon film 40 is formed using the same film as the polysilicon film constituting the gate electrode 10b of the high withstand voltage MISFET. The polysilicon film 40 functions as a resistance element. On the side wall of the polysilicon film 40, a side wall 41 equivalent to the side wall 12 is formed through the step of forming the side wall 12 of the MISFET. Further, a part of the surface of the polysilicon film 40 is formed to form a cobalt vapor film 15.

Then, an interlayer insulating film is formed in such a manner as to cover the polysilicon film 40. This interlayer insulating film is formed of a tantalum nitride film 16 and a hafnium oxide film 17. In the interlayer insulating film, a plug 42 that penetrates the interlayer insulating film and reaches the cobalt germanide film 15 formed on the surface of the polysilicon film 40 is formed, and a wiring 43 directly electrically connected to the plug 42 is formed on the interlayer insulating film. 31 is a cross-sectional view taken along line B-B of FIG. 30, and therefore, a wiring 43 directly electrically connected to the polysilicon film 40 via the plug 42 is shown. Further, a feature of the present embodiment 4 is shown in FIG. 30, that is, the wiring 44 and the polysilicon film 40 do not overlap in a plan view.

Here, the resistive element is formed using a step of forming a high withstand voltage MISFET. That is, the gate insulating film 8 formed on the element isolation region 2 also uses the same film as the gate insulating film 8 of the high withstand voltage MISFET, and the polysilicon film 40 formed on the gate insulating film 8 is also used and constructed. The polysilicon film of the gate electrode 10b of the high withstand voltage MISFET is the same film. Therefore, the height of the resistance element is the same as the height of the high withstand voltage MISFET.

On the other hand, the thickness of the interlayer insulating film is the same as that of the high withstand voltage MISFET formation region and the resistance element formation region, and the interlayer insulating film is considered from the viewpoint of minimizing the aspect ratio of the plug PLG1 of the high withstand voltage MISFET as much as possible. Thin film.

Thus, in the high withstand voltage MISFET formation region, the distance from the interface between the semiconductor substrate 1S and the gate insulating film 8 to the upper portion of the gate electrode 10b is a, and the wiring HL1 is formed from the upper portion of the gate electrode 10b. When the distance between the upper portions of the interlayer insulating film is b, the condition of a>b is obtained.

Then, a polysilicon film 40 (resistive element) is formed on the gate insulating film 8, and a polysilicon film 40 (resistance element) is used to form a gate of the high withstand voltage MISFET. The polycrystalline germanium film of the electrode 10b is formed of the same film. Therefore, in the resistive element formation region, the distance from the interface between the semiconductor substrate 1S and the gate insulating film 8 to the upper portion of the polysilicon film 40 is also the same as a, from the upper portion of the polysilicon film 40 to the formation of the wiring 43 or the wiring 44 ( The distance from the upper portion of the interlayer insulating film of Fig. 30) is also the same as b. Therefore, in the resistive element formation region, the condition of a>b also holds.

From the above, in the resistive element, the thickness of the interlayer insulating film between the polysilicon film 40 and the wiring 44 (not shown in FIG. 31) is thinned, and the polysilicon film interposing with the interlayer insulating film is the same as the high withstand voltage MISFET. The withstand voltage between 40 and wiring 44 poses a problem. Therefore, as shown in FIG. 30, a wiring 44 having a potential different from that of the polysilicon film 40 is also formed in the wiring 43 and the wiring 44 formed on the polysilicon film 40 as the resistance element in the resistive element, and is arranged to be polysilicon. The film 40 does not overlap when viewed from above. With such a configuration, even if the interlayer insulating film is thinned, the withstand voltage between the polysilicon film 40 and the wiring 44 can be ensured.

Here, as a method of lowering the height of the resistance element, it is conceivable that the polysilicon film 40 constituting the resistance element is not formed on the gate insulating film 8 of a thick layer, but is formed directly on the element isolation region 2, or is low resistant. Formed on the gate insulating film of the thin layer of the MISFET. In this case, since the thickness of the interlayer insulating film interposed between the polysilicon film 40 and the wiring 44 can be thickened due to the lowering of the height of the polysilicon film 40 constituting the resistive element, it is judged that the polysilicon film 40 and the wiring 44 can be improved. Withstand voltage.

However, in the present embodiment 4, a polysilicon film 40 as a resistive element is formed on the same film as the gate insulating film 8 of the high withstand voltage MISFET for the reason described below. The reason is explained with reference to the drawings. Figure 32 and Figure 33 A cross-sectional view showing the steps of forming a general element isolation region. For example, as shown in FIG. 32, the element isolation trench 2a is formed on the semiconductor substrate 1S by using a photolithography technique and an etching technique. Then, as shown in FIG. 33, after the element isolation trench 2a is formed by embedding a hafnium oxide film, the hafnium oxide film formed on the surface of the semiconductor substrate 1S is removed by chemical mechanical polishing (CMP). . Thereby, the yttrium oxide film can be left only in the element isolation trench 2a, so that the element isolation region 2 in which only the yttrium oxide film is buried can be formed in the element isolation trench 2a. 32 and 33 show the steps of forming the normal element isolation region 2.

However, for example, as shown in FIG. 34, when the element isolation trench 2a is formed on the semiconductor substrate 1S, the foreign material 45a adheres to the etching region of the semiconductor substrate 1S. As a result, the foreign matter 45a serves as a mask, and is formed in the lower layer of the foreign matter without being left to be etched. That is, as shown in Fig. 34, an etching residue 45 is formed under the foreign matter 45a. Thereafter, as shown in FIG. 35, when the element isolation region 2 in which the trench isolation portion 2a is separated by the hafnium oxide film is formed, the etching residue 45 is maintained.

Therefore, when the polysilicon film 40 as a resistive element is formed on the element isolation region 2 in which the etching residue 45 is formed, since the etching residue 45 is formed of germanium, the polysilicon film 40 and the semiconductor substrate 1S are caused to pass through the etching residue 45. The short circuit is inconvenient. This inconvenience is remarkable in the case where the polysilicon film 40 is directly formed on the element isolation region 2, but as shown in FIG. 36, when the gate insulating film 7 of the thin layer is formed to form the polysilicon film 40, The polysilicon film 40 is applied with a high voltage, and thus short-circuit defects are also likely to occur.

Thereby, as shown in FIG. 37, after a thick gate insulating film 8 is formed on the element isolation region 2, a polysilicon film 40 is formed on the thick gate insulating film 8. By forming a thick gate insulating film 8 between the polysilicon film 40 as a resistive element and the element isolation region 2, for example, as shown in FIG. 37, even if the etching residue 45 occurs in the element isolation region 2, the polysilicon film 40 can be greatly reduced. The semiconductor substrate 1S is short-circuited via the etching residue 45.

For the above reasons, the polysilicon film 40 constituting the resistive element is formed on the gate insulating film 8 having the same thickness as the gate insulating film 8 of the high withstand voltage MISFET. Therefore, the polysilicon film 40 (resistance element) is formed on the gate insulating film 8, and the polysilicon film 40 (resistance element) is formed in the same film as the polysilicon film constituting the gate electrode 10b of the high withstand voltage MISFET. Therefore, in the resistive element formation region, the distance from the interface between the semiconductor substrate 1S and the gate insulating film 8 to the upper portion of the polysilicon film 40 is also the same as a, from the upper portion of the polysilicon film 40 to the formation of the wiring 43 or the wiring 44 ( The distance from the upper portion of the interlayer insulating film of Fig. 30) is also the same as b. Therefore, in the resistive element formation region, the condition of a>b also holds.

However, in the present embodiment 4, the wiring 44 having a different potential from the polysilicon film 40 is formed in the wiring 43 and the wiring 44 formed on the polysilicon film 40 as the resistance element, and is disposed in the polysilicon film 40. Since it does not overlap in planar view, even if the interlayer insulating film is thinned, the remarkable effect of ensuring the withstand voltage between the polysilicon film 40 and the wiring 44 is exhibited.

(implementation type 5)

In the first embodiment, the description relates to covering a low withstand voltage MISFET and a high withstand voltage after forming a low withstand voltage MISFET and a high withstand voltage MISFET. The MISFET is formed by forming an interlayer insulating film, and then forming a wiring on the interlayer insulating film. In the fifth embodiment, the step of forming the interlayer insulating film will be described in further detail.

38 is a cross-sectional view showing a state in which a low breakdown voltage MISFET, a high withstand voltage MISFET, and a resistance element are formed on the semiconductor substrate 1S. That is, in Fig. 38, in addition to the low withstand voltage MISFET and the high withstand voltage MISFET, a resistance element is also formed. The resistive element is formed by a step of forming a high withstand voltage MISFET. Then, as shown in FIG. 38, the tantalum nitride film 16 is formed so as to cover the low breakdown voltage MISFET, the high withstand voltage MISFET, and the resistance element. The tantalum nitride film 16 can be formed using, for example, a CVD method.

Next, as shown in FIG. 39, a tantalum oxide film 50 is formed on the tantalum nitride film 16 formed on the semiconductor substrate 1S. The ruthenium oxide film 50 can be formed by a high density plasma CVD method using, for example, a high density plasma. High-density plasma refers to the use of high-frequency electric fields. The magnetic field is used to high-densify the gas into a plasma. The high-density plasma CVD method refers to the gas introduced into the processing chamber into a high-density plasma, and the high-density plasma is chemically reacted to be deposited on the semiconductor substrate 1S. Membrane method. Examples of the method of generating the high-density plasma include, for example, an induction coupled plasma (ICP) or an electron cyclotron resonance (ECR) method.

The inductively bonded plasma is one of the high-density plasmas used in the chemical vapor phase growth method, and the plasma introduced into the processing chamber is excited by the induced high-frequency coil to cause the plasma to be generated. On the other hand, electron cyclotron resonance is a phenomenon as shown below. That is, if the electron is subjected to Lorentz force in the magnetic field, then It will perform a whirling motion in a plane perpendicular to the magnetic field. At this time, if an electric field having a uniform surrounding frequency is given in the plane of motion of the electron, the whirling motion resonates with the energy of the electric field, and the electric field energy is absorbed by the electron, and the electron is supplied with a large amount of energy. By using this phenomenon, various gases can be converted into high-density plasma.

The ruthenium oxide film 50 formed by the high-density plasma CVD method as described above has an advantage of good landfill characteristics. Therefore, the yttrium oxide film 50 formed by the high-density plasma CVD method is formed on the tantalum nitride film 16, and even if the memory cell of the SRAM (Static Random Access Memory) progresses finely, The element having a small interval between the gate electrodes can still make the yttrium oxide film have good landfill characteristics between the gate electrodes. In summary, an SRAM is also mounted on a semiconductor device that is an LCD driver. Since the SRAM progresses due to the miniaturization, the distance between the gate electrodes becomes very narrow. Therefore, when a yttrium oxide film is buried between the gate electrodes by a CVD method using a plasma of a normal density, the space between the gate electrodes cannot be sufficiently filled, and the space between the gate electrodes is "porosity". "." When a "pore" occurs between the gate electrodes, the conductor film used for forming the plug in the later-described step enters the "pore" and intervenes in the conductor film inside the "pore", and the adjacent plug is short-circuited. bad. Therefore, in the present embodiment 5, the yttrium oxide film 50 is formed on the tantalum nitride film 16 by a high-density plasma CVD method having a good landfill property. By stacking the yttrium oxide film 50 by the high-density plasma CVD method in this way, it is possible to improve the filling property of the space between the gate electrodes in a thinned element such as an SRAM. As a result, "pore" can be suppressed from occurring, and short-circuit defects of adjacent plugs can be prevented.

Next, as shown in FIG. 40, a hafnium oxide film 51 is formed on the hafnium oxide film 50. The cerium oxide film 51 can be formed, for example, by a plasma CVD method using TEOS (tetraethyl ortho silicate). This material uses a plasma CVD method using TEOS using a plasma which is generally lower in density than the above-described high density plasma CVD method. The conventional plasma CVD method using TEOS has a feature that the film thickness of the yttrium oxide film 51 is good, and the yttrium oxide film 51 is formed to obtain the film thickness of the interlayer insulating film.

Next, as shown in FIG. 41, the surface of the ruthenium oxide film 51 is planarized. The planarization of the surface of the ruthenium oxide film 51 is performed by, for example, polishing the surface of the ruthenium oxide film 51 by chemical mechanical polishing (CMP). In this step, the film thickness of the ruthenium oxide film 51 is reduced due to variations in the amount of polishing caused by CMP, etc., and the upper portion of the high withstand voltage MISFET or the upper portion of the resistance element is exposed.

Therefore, as shown in FIG. 42, a ruthenium oxide film (gap insulating film) 52 is formed on the planarized yttrium oxide film 51. The ruthenium oxide film 52 is formed in the same manner as the ruthenium oxide film 51, and can be formed by a normal plasma CVD method using TEOS as a raw material.

Next, as shown in FIG. 43, contact holes are formed in the interlayer insulating film (the hafnium oxide film 52, the hafnium oxide film 51, the hafnium oxide film 50, and the tantalum nitride film 16) by using a photolithography technique and an etching technique. The contact hole penetrates the interlayer insulating film and reaches the semiconductor substrate 1S.

Then, a titanium/titanium nitride film is formed on the interlayer insulating film including the bottom surface and the inner wall of the contact hole. The titanium/titanium nitride film is composed of a laminated film of a titanium film and a titanium nitride film, and can be formed, for example, by sputtering. Thereafter, a tungsten film is formed on the entire surface of the main surface of the semiconductor substrate 1S so as to fill the contact holes. The tungsten The film can be formed using, for example, a CVD method.

Then, by removing the unnecessary titanium/titanium nitride film and the tungsten film formed on the interlayer insulating film by, for example, a CMP method, the titanium/titanium nitride film and the tungsten film remain only in the contact holes, and the plug PLG1 can be formed. And plug 42.

Next, as shown in FIG. 44, a titanium/titanium nitride film, an aluminum film containing copper, and a titanium/titanium nitride film are sequentially formed on the hafnium oxide film 52 and the plug PLG1. These films can be formed by using, for example, sputtering. Next, patterning of the films is performed by using a photolithography technique and an etching technique to form wirings HL1, LL1, wirings 43, and wirings 53. In this manner, the wiring HL1, the wiring LL1, the wiring 43, and the wiring 53 can be formed on the first interlayer insulating film.

In the fifth embodiment, as in the first embodiment, the wiring HL1 and the gate electrode 10b disposed on the first interlayer insulating film are not overlapped in plan view. Thereby, since the wiring HL1 is not formed directly above the gate electrode 10b of the high withstand voltage MISFET, even if the first interlayer insulating film is thinned, the distance between the wiring HL1 and the gate electrode 10b can be pulled apart. Therefore, the withstand voltage of the gate electrode 10b of the high withstand voltage MISFET and the wiring HL1 which is the source wiring or the gate wiring can be ensured.

On the other hand, in the resistive element formation region, the wiring 43 directly connected to the polysilicon film 40 as the resistance element via the plug 42 is formed so as to overlap the polysilicon film 40 in plan view. However, since the wiring 43 and the wiring 53 formed on the polysilicon film 40 as the resistance element are not directly connected to the polysilicon film 40 with the plug 42, and the wiring 53 having a different potential from the polysilicon film 40 is applied, the arrangement is performed. In order to not overlap with the polysilicon film 40 in a plan view, Therefore, even if the interlayer insulating film is thinned, the withstand voltage between the polysilicon film 40 and the wiring 53 can be ensured.

The invention achieved by the inventors of the present invention is specifically described above, but the present invention is not limited to the embodiments described above, and various modifications may be made without departing from the spirit and scope of the invention.

In the foregoing embodiment, an example in which an n-channel type MISFET is used as a low withstand voltage MISFET and a high withstand voltage MISFET formed in an LCD driver is described, but a p-channel type MISFET is used as a low withstand voltage MISFET and a high withstand voltage MISFET. In the case, the technical idea of this embodiment mode can also be applied.

(industrial availability)

The present invention can be widely utilized in the manufacturing of semiconductor devices.

1S‧‧‧Semiconductor substrate

2‧‧‧Component separation area

2a‧‧‧ Component separation trench

3‧‧‧Insulated area for electric field relaxation

4‧‧‧p well

5‧‧‧p type well

6‧‧‧Low-concentration impurity diffusion area for high withstand voltage

7‧‧‧Gate insulation film

8‧‧‧Gate insulation film

9‧‧‧Polysilicon film

10a‧‧‧gate electrode

10b‧‧‧gate electrode

11‧‧‧Low-concentration impurity diffusion area for low withstand voltage

12‧‧‧ Side wall

13‧‧‧High concentration impurity diffusion area for low withstand voltage

14‧‧‧High concentration impurity diffusion area for high withstand voltage

15‧‧‧Cobalt telluride film

16‧‧‧ nitride film

17‧‧‧Oxide film

18a‧‧‧Titanium/titanium nitride film

18b‧‧‧Tungsten film

19a‧‧‧Titanium/titanium nitride film

19b‧‧‧Aluminum film

19c‧‧‧Titanium/titanium nitride film

20‧‧‧Oxide film

21‧‧‧Oxide film

22‧‧‧Surface protection film

23‧‧‧UBM film

24‧‧‧Conductor film

30a‧‧‧glass substrate

30b‧‧‧glass substrate

31‧‧‧Flexible substrate

32‧‧‧Anisotropic conductive film

33‧‧‧Display Department

40‧‧‧ Polysilicon film

41‧‧‧ Side wall

42‧‧‧ plug

43‧‧‧Wiring

44‧‧‧Wiring

45‧‧‧ etching residue

45a‧‧‧ Foreign objects

50‧‧‧Oxide film

51‧‧‧Oxide film

52‧‧‧Oxide film

53‧‧‧Wiring

BMP‧‧‧ bump electrode

C1‧‧‧ gate drive circuit

C2‧‧‧ source drive circuit

C3‧‧‧LCD driver circuit

C4‧‧‧Graphic RAM

C5‧‧‧ peripheral circuits

CHP‧‧‧Semiconductor wafer

CNT1‧‧‧ contact hole

GL‧‧‧ gate wiring

HL1‧‧‧ wiring

HL2‧‧‧ wiring

LL1‧‧‧ wiring

LL2‧‧‧ wiring

PAD‧‧‧ pads

PLG1‧‧‧ plug

PLG2‧‧‧ plug

RES‧‧‧resist film

Fig. 1 is a plan view showing a semiconductor wafer (LCD driver) of an embodiment of the present invention.

Fig. 2 is a cross-sectional view showing an example of the internal structure of the semiconductor wafer shown in Fig. 1.

Fig. 3 is a plan view showing the high withstand voltage MISFET shown in Fig. 2.

4 is a cross-sectional view showing a manufacturing step of a semiconductor device of an embodiment.

Figure 5 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 4.

Figure 6 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 5.

Figure 7 is a cross section showing the manufacturing steps of the semiconductor device continued from Figure 6; Figure.

Figure 8 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 7.

Figure 9 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 8.

Figure 10 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 9.

Figure 11 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 10.

Figure 12 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 11;

Figure 13 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 12;

Figure 14 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 13.

Figure 15 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 14.

Figure 16 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 15.

Figure 17 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 16;

Figure 18 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 17;

Figure 19 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 18 Figure.

Figure 20 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 19.

Figure 21 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 20.

Figure 22 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 21;

Figure 23 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 22;

Figure 24 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 23;

Figure 25 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 24;

Fig. 26 is a cross-sectional view showing a state in which a semiconductor wafer is mounted on a glass substrate.

Fig. 27 is a view showing the overall structure of the LCD.

Figure 28 is a cross-sectional view showing a semiconductor device of Embodiment 2 and Embodiment 3.

Fig. 29 is a view specifically showing the dimensional error of the pattern of the photolithography step and the alignment deviation between the patterns.

Fig. 30 is a plan view showing the structure of a resistive element of the embodiment 4.

Figure 31 is a cross-sectional view showing a cross section taken along line B-B of Figure 30.

Figure 32 is a cross-sectional view showing the steps of forming a general element isolation region.

Figure 33 is a cross section of the step of forming the element separation region of Figure 32; Figure.

Fig. 34 is a cross-sectional view showing a state in which an etching residue is generated due to foreign matter when the element separation trench is formed.

Figure 35 is a cross-sectional view showing the step of forming the element separation region of Figure 34.

Fig. 36 is a cross-sectional view showing an example in which a thin gate insulating film is formed on an element isolation region in which an etching residue is formed to form a resistive element.

Fig. 37 is a cross-sectional view showing an example in which a gate insulating film is formed by interposing a thick layer of a gate insulating film on an element isolation region in which an etching residue is formed.

38 is a cross-sectional view showing a manufacturing step of the semiconductor device of the embodiment 5.

Figure 39 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 38.

Figure 40 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 39.

Figure 41 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 40.

Figure 42 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 41.

Figure 43 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 42.

Figure 44 is a cross-sectional view showing the manufacturing steps of the semiconductor device continued from Figure 43.

1S‧‧‧Semiconductor substrate

2‧‧‧Component separation area

3‧‧‧Insulated area for electric field relaxation

4,5‧‧‧p type well

6‧‧‧Low-concentration impurity diffusion area for high withstand voltage

7,8‧‧‧gate insulating film

10a, 10b‧‧‧ gate electrode

11‧‧‧Low-concentration impurity diffusion area for low withstand voltage

12‧‧‧ Side wall

13‧‧‧High concentration impurity diffusion area for low withstand voltage

14‧‧‧High concentration impurity diffusion area for high withstand voltage

15‧‧‧Cobalt telluride film

16,17‧‧‧ nitride film

a‧‧‧From the interface between the semiconductor substrate 1S and the gate insulating film 8 to the upper portion of the gate electrode 10b

B‧‧‧ Distance from the upper portion of the gate electrode 10b to the upper portion of the interlayer insulating film on which the wiring HL1 is formed

c‧‧‧From the interface between the semiconductor substrate 1S and the gate insulating film 7 to the upper portion of the gate electrode 10a

D‧‧‧ Distance from the upper portion of the gate electrode 10a to the upper portion of the interlayer insulating film on which the wiring LL1 is formed from

HL1, LL1‧‧‧ wiring

PLG1‧‧‧ plug

Claims (33)

A semiconductor device comprising: (a1) a first gate insulating film formed on a semiconductor substrate; and (a2) a first gate electrode formed on the first gate insulating film; A3) The first MISFET includes a first source region and a first drain region formed by integrating the first gate electrode, and (b1) a second gate insulating film formed on the semiconductor substrate; B2) a second gate electrode formed on the second gate insulating film and having a conductor film in the same layer as the first gate electrode; (b3) a second MISFET included in the second electrode a second source region and a second drain region formed by integrating the gate electrodes, wherein a thickness of the second gate insulating film is thinner than a thickness of the first gate insulating film; and (c) an insulating film; The first MISFET and the second MISFET are formed on the first MISFET and the second MISFET; (d) the first plug is electrically connected to the first source region through the insulating film; and (e) the second plug is connected The insulating film is electrically connected to the first drain region; (f) a third plug that penetrates the insulating film and is electrically connected to the second source region And (g) a fourth plug electrically connected to the second drain region and electrically connected to the second drain region; (h) a first source wiring formed on the insulating film and before a first plug electrical connection; (i) a first drain wiring formed on the insulating film and electrically connected to the second plug; (j) a second source wiring Formed on the insulating film and electrically connected to the third plug; and (k) a second drain wiring formed on the insulating film and electrically connected to the fourth plug; The first source wiring, the first drain wiring, the second source wiring, and the second drain wiring are formed in the same layer; and the semiconductor substrate and the first gate are The distance from the interface of the insulating film to the upper surface of the first gate electrode is a, and the first source wiring and the first drain wiring are formed from the upper surface of the first gate electrode. When the distance between the upper surface of the insulating film of the second source wiring and the second drain wiring is b, a>b; the first gate electrode and the first source wiring system The first gate electrode and the first drain wiring are disposed so as not to overlap in a plan view, and the second gate electrode and the second source are not overlapped in a plan view. The pole wirings are arranged to overlap in a plan view, and the second gate electrode and the second drain wiring are arranged to overlap each other in a plan view. The semiconductor device according to claim 1, wherein the first source wiring, the first drain wiring, the second source wiring, and the first drain wiring constitute a lowermost wiring layer. The semiconductor device of claim 1, wherein An electric field relaxation insulating region is formed in the first source region and the first drain region. The semiconductor device according to claim 3, wherein the end portion of the first gate electrode is placed on the electric field relaxation insulating region. The semiconductor device according to claim 3, wherein the electric field relaxation insulating region protrudes from the semiconductor substrate. The semiconductor device according to claim 3, wherein the electric field relaxation insulating region is formed by filling an insulating material in a trench formed in the semiconductor substrate. The semiconductor device of claim 3, wherein the insulating region for electric field relaxation is formed by a selective oxidation method. The semiconductor device according to claim 1, wherein the insulating film is formed of a laminated film of a tantalum nitride film and a hafnium oxide film. The semiconductor device according to claim 1, wherein the gate wiring electrically connected to the first gate electrode is formed by the first source wiring, the first drain wiring, and the second source wiring And the second wiring of the second drain wiring is formed in the same layer. The semiconductor device according to claim 9, wherein the gate wiring includes a region overlapping the first gate electrode in a plan view. The semiconductor device of claim 1, wherein the driving voltage of the first MISFET is 20 V or more. The semiconductor device of claim 1, wherein the semiconductor device is used in an LCD driver of a liquid crystal display device. The semiconductor device according to claim 1, wherein a distance between the first gate electrode and the first source wiring that does not overlap in a plan view or between the first gate electrode and the first drain wiring is in a plan view The distance that does not overlap is 100 nm or more. The semiconductor device according to claim 1, wherein the semiconductor substrate includes a resistive element forming region different from a region in which the first MISFET and the second MISFET are formed, and the resistive element forming region includes an element isolation region in the semiconductor substrate. The first gate insulating film is formed on the element isolation region, and the conductive film is formed as a resistive element on the first gate insulating film, and the insulating film is formed on the first MISFET and the second MISFET. The conductive film is formed to cover the conductive film, and the fifth plug penetrates the insulating film formed on the first MISFET and the second MISFET, and is electrically connected to the conductive film, and a first wiring is formed on the insulating film. The second wiring is electrically connected to the fifth plug, and a second wiring is formed on the insulating film for receiving a potential different from the conductor film; wherein the first wiring and the second wiring are formed on Same layer; and In a region, the first wiring and the conductor film overlap in a plan view, and the second wiring and the conductor film do not overlap in a plan view. The semiconductor device according to claim 1, wherein a distance from an interface between the semiconductor substrate and the second gate insulating film to an upper surface of the second gate electrode is c, and the second gate electrode is used. a case where the distance from the upper surface to the upper surface of the insulating film on which the first source wiring, the first drain wiring, the second source wiring, and the second drain wiring are formed is d Next, c<d. A method of manufacturing a semiconductor device, comprising the steps of: (a) forming a device isolation region and an electric field relaxation insulating region on a semiconductor substrate; and (b) forming a gate insulating film on the semiconductor substrate; c) a step of forming a pair of low-concentration impurity diffusion regions in a manner of separately encapsulating the insulating regions for electric field relaxation; (d) a step of forming a gate electrode on the gate insulating film; (e) a gate electrode a step of forming a sidewall on the sidewalls on both sides of the electrode; (f) forming a pair of high-concentration impurity diffusion regions in a region surrounded by the pair of low-concentration impurity diffusion regions and outside the insulating region for the electric field relaxation, And forming a source region composed of one of the pair of low-concentration impurity diffusion regions and one of the pair of high-concentration impurity diffusion regions included therein, and forming a diffusion of the first pair of low-concentration impurities a step of forming another one of the regions and a drain region composed of the other one of the pair of high-concentration impurity diffusion regions; (g) forming an insulating film so as to cover the gate electrode Step; (h) forming a first plug that penetrates the insulating film and reaches the source region, and forms a second plug that penetrates the insulating film to reach the drain region; and (i) forms on the insulating film a source wiring connected to the first plug, a step of forming a drain wiring connected to the second plug on the insulating film; and an interface from the semiconductor substrate and the gate insulating film to the foregoing The distance from the upper portion of the gate electrode is a, and the distance from the upper portion of the gate electrode to the upper surface of the insulating film on which the source wiring and the drain wiring are formed is b, a And bb, the gate electrode and the source wiring are formed so as not to overlap each other in a plan view, and the gate electrode and the drain wiring are formed so as not to overlap each other in a plan view. The method of manufacturing a semiconductor device according to claim 16, wherein the source wiring and the drain wiring constitute a lowermost wiring layer. The method of manufacturing a semiconductor device according to claim 16, wherein after the step (g) and before the step (h), the step of planarizing the surface of the insulating film by polishing the surface of the insulating film is performed. . The method of manufacturing a semiconductor device according to claim 16, wherein the step (h) comprises the steps of: (h1) forming a first contact hole reaching the source region and a second contact reaching the drain region in the insulating film; Step of the hole; (h2) a step of forming a conductive film on the insulating film including the inside of the first contact hole and the inside of the second contact hole; and (h3) removing the conductive film formed on the insulating film by polishing the conductive film On the other hand, the conductive film is formed by leaving the conductive film inside the first contact hole and the second contact hole to form the first plug and the second plug. The method of fabricating a semiconductor device according to claim 16, wherein the step (h) also forms a third plug reaching the gate electrode; the step (i) is the same as the source wiring and the drain wiring The layer forms a gate wiring connected to the third plug; and the gate electrode and the gate wiring include regions overlapping in a plan view. The method of manufacturing a semiconductor device according to claim 16, wherein the step (g) forms a tantalum nitride film so as to cover the gate electrode, and a tantalum oxide film is formed on the tantalum nitride film, thereby The above-mentioned insulating film is formed by laminating a tantalum nitride film and the above-described tantalum oxide film. The method of manufacturing a semiconductor device according to claim 16, wherein the step (a) is formed by forming a trench in the semiconductor substrate and filling an insulating material in the trench to form the element isolation region and the electric field relaxation insulating region. . The method of manufacturing a semiconductor device according to claim 16, wherein the step (d) is such that the gate electrode is formed so that an end portion of the gate electrode is formed on the insulating region for electric field relaxation. A method of manufacturing a semiconductor device according to claim 16, wherein The step (g) includes the steps of: (g1) forming a first insulating film in such a manner as to cover the gate electrode; (g2) forming a second insulating film on the first insulating film; (g3) a step of planarizing the surface of the second insulating film; and (g4) a step of forming a gap insulating film on the second insulating film; and a plasma used in forming the first insulating film in the step (g1) Forming a plasma having a higher density than the plasma used in forming the second insulating film in the step (g2); the insulating film comprising: the first insulating film, the second insulating film, and the gap insulating film . A semiconductor device comprising: (a1) a first gate insulating film formed on a semiconductor substrate; and (a2) a first gate electrode formed on the first gate insulating film; A3) The first MISFET includes a first source region and a first drain region formed by integrating the first gate electrode, and (b1) a second gate insulating film formed on the semiconductor substrate; B2) a second gate electrode formed on the second gate insulating film; (b3) a second MISFET including a second source region and a second region formed by integrating the second gate electrode a polar region, wherein a thickness of the second gate insulating film is thinner than a thickness of the first gate insulating film; and (c) an insulating film formed on the first MISFET and the first (2) a first plug electrically penetrating through the insulating film and electrically connected to the first source region; (e) a second plug penetrating through the insulating film and the first drain a third electrical plug that penetrates the insulating film and is electrically connected to the second source region; (g) a fourth plug that penetrates the insulating film and is in contact with the second The drain region is electrically connected; (h) the first source wiring is formed on the insulating film and electrically connected to the first plug; (i) the first drain wiring is formed And the second source wiring is electrically connected to the insulating film, and is electrically connected to the third plug; and (k) a second drain wiring formed on the insulating film and electrically connected to the fourth plug; wherein an electric field relaxation is formed in the first source region and the first drain region An insulating region; an end portion of the first gate electrode is placed on the electric field relaxation insulating region; and the first gate electrode and the first source wiring are disposed Do not overlap in plan view, the first and the gate electrode and the first drain line arranged as not to overlap in a plan view; and The electric field relaxation insulating region protrudes from the semiconductor substrate. A semiconductor device comprising: (a1) a gate insulating film formed on a semiconductor substrate; (a2) a gate electrode formed on the gate insulating film; (a3) a MISFET, wherein a source region and a drain region formed by integrating the gate electrode; (b) an insulating film formed on the MISFET; and (c) a first plug penetrating the insulating film and the source a pole region electrically connected; (d) a second plug penetrating through the insulating film and electrically connected to the drain region; (e) a source wiring formed on the insulating film and having the foregoing a first plug electrically connected; and (f) a drain wiring formed on the insulating film and electrically connected to the second plug; the diameter of the first plug and the second plug The diameter of the plug is set to z, and the distance from the upper surface of the gate electrode to the upper surface of the insulating film on which the source wiring and the drain wiring are formed is b, b<2.5 z; the gate electrode and the source wiring are disposed so as not to overlap in a plan view, and the gate electrode and the foregoing Source wiring lines arranged as not to overlap in plan view. A semiconductor device comprising: (a1) a gate insulating film formed on a semiconductor substrate; (a2) a gate electrode formed on the gate insulating film; (a3) a MISFET including a source region and a drain region formed by integrating the gate electrode; (b) an insulating film; Formed on the MISFET; (c) a first plug that penetrates the insulating film and is electrically connected to the source region; (d) a second plug that penetrates the insulating film and is adjacent to the drain a regional electrical connection; (e) a source wiring formed on the insulating film and electrically connected to the first plug; and (f) a drain wiring formed on the insulating film And electrically connected to the second plug; wherein a distance from the interface between the semiconductor substrate and the gate insulating film to the upper surface of the gate electrode is a, and the upper surface of the gate electrode is to be When the distance from the upper surface of the insulating film on which the source wiring and the drain wiring are formed is b, a>b; the gate electrode and the source wiring are arranged in a plan view. Do not overlap, and the gate electrode and the drain wiring line are arranged so as not to overlap in a plan view; and the aforementioned MIS The driving voltage of the FET is 20V or more. A semiconductor device comprising: (a1) a first gate insulating film formed on a semiconductor substrate; and (a2) a first gate electrode formed on the first gate insulating film; (a3) the first MISFET includes a first source region and a first drain region formed by integrating the first gate electrode, and (b1) a second gate insulating film formed on the semiconductor substrate; (b2) a second gate electrode formed on the second gate insulating film and having a conductor film in the same layer as the first gate electrode; (b3) a second MISFET included in the first a second source region and a second drain region formed by integrating the gate electrodes, wherein a thickness of the second gate insulating film is thinner than a thickness of the first gate insulating film; (c) first a plug electrically connected to the first source region; (d) a second plug electrically connected to the first drain region; (e) a third plug connected to the first 2) a source region electrically connected; (f) a fourth plug electrically connected to the second drain region; (g) a first source wiring electrically connected to the first plug (h) a first drain wiring electrically connected to the second plug; (i) a second source wiring electrically connected to the third plug; and (j) 2 布线 pole wiring, which is connected to the aforementioned fourth plug The first source wiring, the first drain wiring, the second source wiring, and the second drain wiring are formed in the same layer; and the semiconductor substrate and the first semiconductor are The distance from the interface of the gate insulating film to the upper surface of the first gate electrode is a, and the upper surface of the first gate electrode is connected to the first source wiring and the first drain wiring. When the distance between the second source wiring and the lower surface of the second drain wiring is b, a>b; the first gate electrode and the first source wiring are arranged in a plan view. The first gate electrode and the first drain wiring are arranged so as not to overlap each other in a plan view, and the second gate electrode and the second source wiring are arranged to overlap in a plan view. The second gate electrode and the second drain wiring are arranged to overlap each other in a plan view. The semiconductor device according to claim 28, wherein the first MISFET, the second MISFET, the first plug, the second plug, the third plug, and the fourth plug are formed in an insulating film. The semiconductor device according to claim 28, wherein a distance from an interface between the semiconductor substrate and the second gate insulating film to an upper surface of the second gate electrode is c, and the second gate electrode is used. When the distance from the upper surface to the lower surface of the first source wiring, the first drain wiring, the second source wiring, and the second drain wiring is d, c<d. The semiconductor device according to claim 28, wherein the electric field relaxation insulating region is formed in the first source region and the first drain region. The semiconductor device according to claim 31, wherein the end portion of the first gate electrode is placed on the insulating region for electric field relaxation. The semiconductor device according to claim 31, wherein the electric field relaxation insulating region protrudes from the semiconductor substrate.