TWI433285B - Method of forming metal bumps - Google Patents
Method of forming metal bumps Download PDFInfo
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- TWI433285B TWI433285B TW100144805A TW100144805A TWI433285B TW I433285 B TWI433285 B TW I433285B TW 100144805 A TW100144805 A TW 100144805A TW 100144805 A TW100144805 A TW 100144805A TW I433285 B TWI433285 B TW I433285B
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- Taiwan
- Prior art keywords
- layer
- forming
- conductive layer
- alkali
- opening
- Prior art date
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- 238000000034 method Methods 0.000 title claims description 35
- 229910052751 metal Inorganic materials 0.000 title claims description 23
- 239000002184 metal Substances 0.000 title claims description 23
- 239000010410 layer Substances 0.000 claims description 168
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 33
- 239000003513 alkali Substances 0.000 claims description 33
- 229910052802 copper Inorganic materials 0.000 claims description 33
- 239000010949 copper Substances 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 9
- 239000011241 protective layer Substances 0.000 claims description 6
- 238000005553 drilling Methods 0.000 claims description 4
- 239000007788 liquid Substances 0.000 claims 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 10
- 229910000679 solder Inorganic materials 0.000 description 8
- 229910052763 palladium Inorganic materials 0.000 description 5
- 238000007747 plating Methods 0.000 description 5
- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 4
- 239000011148 porous material Substances 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- 238000009713 electroplating Methods 0.000 description 3
- LCPVQAHEFVXVKT-UHFFFAOYSA-N 2-(2,4-difluorophenoxy)pyridin-3-amine Chemical compound NC1=CC=CN=C1OC1=CC=C(F)C=C1F LCPVQAHEFVXVKT-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 238000007654 immersion Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- CHQMHPLRPQMAMX-UHFFFAOYSA-L sodium persulfate Substances [Na+].[Na+].[O-]S(=O)(=O)OOS([O-])(=O)=O CHQMHPLRPQMAMX-UHFFFAOYSA-L 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
- 239000003755 preservative agent Substances 0.000 description 1
- 230000002335 preservative effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
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- Manufacturing Of Printed Wiring (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
本發明係有關於一種形成金屬凸塊之方法，特別是一種於電路板的接墊上形成金屬凸塊之方法。The present invention relates to a method of forming metal bumps, and more particularly to a method of forming metal bumps on pads of a circuit board.
電路板的微細凸塊間距(fine bump pitch)技術一直是業界開發的主要重點。然而，過去以墊上焊錫(solder plated on pad,SPOP)法在電路板或基板上形成金屬凸塊的作法已面臨到技術瓶頸。這是因為防焊開孔(SRO)以及曝光對位精度無法下縮的結果。The board's fine bump pitch technology has been a major focus of industry development. However, in the past, a method of forming metal bumps on a circuit board or a substrate by a solder plated on pad (SPOP) method has faced a technical bottleneck. This is because the solder mask opening (SRO) and the accuracy of the exposure alignment cannot be reduced.
目前的SPOP法是先在防焊層中形成SRO開孔，蓋上乾膜後，再於SRO開孔的原處形成第二次開孔，受限於曝光對位精度的容許誤差，第二次開孔的孔徑必須較SRO開孔大些，例如，30微米(μm)，造成最後形成的凸塊或銅柱因此具有不利的上蓋帽緣結構。The current SPOP method is to first form a SRO opening in the solder mask, and after forming a dry film, a second opening is formed in the original portion of the SRO opening, which is limited by the tolerance of the exposure alignment accuracy, and second. The aperture of the secondary opening must be larger than the opening of the SRO, for example, 30 micrometers (μm), resulting in a finally formed bump or copper pillar thus having an unfavorable upper cap edge structure.
在相關的先前技藝中，如台灣專利公開號TW200803660，雖然教示將一離形膜及離形膜上表面之晶種層移除，藉以形成無上蓋且口徑一致的焊錫凸塊。然而，上述作法之缺點是離形膜撕除時會有殘膜或離形膜去除不全的問題發生，故實際上難以實施。In a related prior art, such as Taiwan Patent Publication No. TW200803660, it is taught that a seed layer of a release film and an upper surface of a release film is removed, thereby forming a solder bump having no upper cover and uniform aperture. However, the above-mentioned method has a drawback in that the problem that the residual film or the release film is incompletely removed when the release film is peeled off is practically difficult to carry out.
於是，本發明提出一種改良之形成金屬凸塊之方法，以解決先前技藝之不足與缺點。Accordingly, the present invention provides an improved method of forming metal bumps to address the deficiencies and shortcomings of the prior art.
根據本發明之一實施例，本發明提出一種形成金屬凸塊之方法，首先提供一基板，其上至少具有一線路層，包含有至少一接墊，其中該線路層被一絕緣層所覆蓋；於該絕緣層上形成一第一導電層；於該第一導電層上形成一抗鹼膜；於該抗鹼膜上形成一第二導電層；於該第二導電層、該抗鹼膜、該第一導電層及該絕緣層中形成至少一開孔，顯露出該接墊；於該第二導電層上以及該開孔之側壁、底部均勻形成一晶種層；選擇性的去除該第二導電層上之該晶種層以及該第二導電層，僅留下位於該開孔側壁之晶種層；於該晶種層上形成一第三導電層，填滿該開孔；以及去除該抗鹼膜及該第一導電層，顯露出第三導電層之上部。According to an embodiment of the present invention, a method for forming a metal bump is provided. First, a substrate is provided having at least one circuit layer including at least one pad, wherein the circuit layer is covered by an insulating layer; Forming a first conductive layer on the insulating layer; forming an anti-alkali film on the first conductive layer; forming a second conductive layer on the anti-alkali film; and forming the second conductive layer, the anti-alkali film, Forming at least one opening in the first conductive layer and the insulating layer to expose the pad; uniformly forming a seed layer on the second conductive layer and sidewalls and bottom of the opening; selectively removing the first layer The seed layer on the two conductive layers and the second conductive layer leaving only a seed layer on the sidewall of the opening; forming a third conductive layer on the seed layer to fill the opening; and removing The alkali-resistant film and the first conductive layer expose an upper portion of the third conductive layer.
根據本發明之另一實施例，本發明提出一種形成金屬凸塊之方法，先提供一基板，其上至少具有一線路層，包含有至少一接墊，其中該線路層被一絕緣層所覆蓋；於該絕緣層上形成一抗鹼膜；於該抗鹼膜上形成一濺鍍銅層；於該濺鍍銅層、該抗鹼膜及該絕緣層中形成至少一開孔，顯露出該接墊；於該濺鍍銅層上以及該開孔之側壁、底部均勻形成一晶種層；選擇性的去除該濺鍍銅層上之該晶種層以及該濺鍍銅層，僅留下位於該開孔側壁之晶種層；於該晶種層上形成一導電層，填滿該開孔；以及去除該抗鹼膜，顯露出導電層之上部。According to another embodiment of the present invention, the present invention provides a method of forming a metal bump, which first provides a substrate having at least one wiring layer including at least one pad, wherein the circuit layer is covered by an insulating layer Forming an alkali-resistant film on the insulating layer; forming a sputtered copper layer on the anti-alkali film; forming at least one opening in the sputtered copper layer, the anti-alkali film, and the insulating layer to reveal the a seed layer; a seed layer is uniformly formed on the sputtered copper layer and the sidewalls and the bottom of the opening; selectively removing the seed layer on the sputtered copper layer and the sputtered copper layer, leaving only a seed layer on the sidewall of the opening; forming a conductive layer on the seed layer to fill the opening; and removing the alkali-resistant film to expose the upper portion of the conductive layer.
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims. However, the following preferred embodiments and drawings are for illustrative purposes only and are not intended to limit the invention.
首先，請參閱第1A圖至第1L圖，其為依據本發明一實施例所繪示的電路板剖面示意圖。如第1A圖所示，本發明形成金屬凸塊之方法係先提供一電路板或基板10，其上至少具有一線路層12，包含有至少一接墊122以及一細線路124，其中線路層12被一絕緣層14所覆蓋。前述之絕緣層14可以是防焊層或者ABF樹脂層。如第1B圖所示，於絕緣層14上形成一第一導電層16，例如，化銅層。如第1C圖所示，於第一導電層16上形成一抗鹼膜18，其能耐高溫，在化學鍍銅槽中，能抵抗使用於化學鍍銅或電鍍過程中的鹼液。First, please refer to FIG. 1A to FIG. 1L, which are schematic cross-sectional views of a circuit board according to an embodiment of the invention. As shown in FIG. 1A, the method for forming a metal bump of the present invention first provides a circuit board or substrate 10 having at least one circuit layer 12 including at least one pad 122 and a thin line 124, wherein the circuit layer 12 is covered by an insulating layer 14. The foregoing insulating layer 14 may be a solder resist layer or an ABF resin layer. As shown in FIG. 1B, a first conductive layer 16, for example, a copper layer, is formed on the insulating layer 14. As shown in FIG. 1C, an alkali-resistant film 18 is formed on the first conductive layer 16, which is resistant to high temperatures and is resistant to alkali liquor used in electroless copper plating or electroplating in the electroless copper plating bath.
如第1D圖所示，於抗鹼膜18上形成一第二導電層20，例如，以濺鍍銅層較佳。接著，如第1E圖所示，以雷射鑽孔法，於第二導電層20、抗鹼膜18、第一導電層16及絕緣層14中形成至少一開孔32，顯露出部分的接墊122之一上表面。如第1F圖所示，於第二導電層20上以及開孔32之側壁、底部均勻形成一晶種層36，例如，含鈀金屬層。根據本發明之實施例，晶種層36可以是一種不連續之含鈀金屬層，其可具有孔隙，容許蝕刻液通過。如第1G圖所示，以濕式化學微蝕法，例如，過硫酸鈉/硫酸溶液，去除第二導電層20，根據本發明之實施例，由於該濕式化學微蝕法僅會經由晶種層36的孔隙，選擇性的蝕刻第二導電層20，故可以將第二導電層20上之晶種層36一併去除，僅留下位於開孔32側壁之晶種層36。如第1H圖所示，可接著在晶種層36上形成一化銅層42。如第1I圖所示，再以電鍍法形成一第三導電層50，例如電鍍銅層，填滿開孔32。As shown in Fig. 1D, a second conductive layer 20 is formed on the alkali-resistant film 18, and for example, a copper plating layer is preferably used. Next, as shown in FIG. 1E, at least one opening 32 is formed in the second conductive layer 20, the alkali-resistant film 18, the first conductive layer 16, and the insulating layer 14 by a laser drilling method to reveal a part of the connection. One of the upper surfaces of the pad 122. As shown in FIG. 1F, a seed layer 36, for example, a palladium-containing metal layer, is uniformly formed on the second conductive layer 20 and on the sidewalls and bottom of the opening 32. In accordance with an embodiment of the present invention, seed layer 36 can be a discontinuous palladium-containing metal layer that can have pores that permit passage of etchant. As shown in FIG. 1G, the second conductive layer 20 is removed by a wet chemical microetching method, for example, a sodium persulfate/sulfuric acid solution, according to an embodiment of the present invention, since the wet chemical microetching method only passes through the crystal The pores of the seed layer 36 selectively etch the second conductive layer 20, so that the seed layer 36 on the second conductive layer 20 can be removed together, leaving only the seed layer 36 on the sidewall of the opening 32. As shown in FIG. 1H, a copper layer 42 can be formed on the seed layer 36. As shown in FIG. 1I, a third conductive layer 50, such as an electroplated copper layer, is formed by electroplating to fill the openings 32.
繼之，如第1J圖所示，去除抗鹼膜18顯露出第一導電層16。如第1K圖所示，蝕刻去除第一導電層16，顯露出第三導電層50之上部52。另外，如第1L圖所示，可以在顯露出來的第三導電層50之上部52的表面上形成一保護層60。前述之保護層60係選自以下組合之一者：有機保焊劑(organic solderability preservative,OSP)、化鎳鈀浸金(electroless nickel electroless palladium immersion gold,ENEPIG)，以及化錫。Next, as shown in FIG. 1J, the removal of the alkali-resistant film 18 reveals the first conductive layer 16. As shown in FIG. 1K, the first conductive layer 16 is etched away to expose the upper portion 52 of the third conductive layer 50. Further, as shown in FIG. 1L, a protective layer 60 may be formed on the surface of the upper portion 52 of the exposed third conductive layer 50. The protective layer 60 described above is selected from one of the following combinations: an organic solderability preservative (OSP), an electroless nickel electroless palladium immersion gold (ENEPIG), and a tin.
請參閱第2A圖至第2J圖，其為依據本發明另一實施例所繪示的電路板剖面示意圖。如第2A圖所示，本發明形成金屬凸塊之方法，係先提供一電路板或基板10，其上至少具有一線路層12，包含有至少一接墊122以及一細線路124，其中線路層12被一絕緣層14所覆蓋。前述之絕緣層14可以是防焊層或者ABF樹脂層。如第2B圖所示，於絕緣層14上直接形成一抗鹼膜18，其能耐高溫，在化學鍍銅槽中，能抵抗使用於化學鍍銅或電鍍過程中的鹼液。根據本發明之實施例，抗鹼膜18係直接形成在於絕緣層14上，並與絕緣層14直接接觸。Please refer to FIG. 2A to FIG. 2J , which are schematic cross-sectional views of a circuit board according to another embodiment of the invention. As shown in FIG. 2A, the method for forming a metal bump of the present invention first provides a circuit board or substrate 10 having at least one circuit layer 12 including at least one pad 122 and a thin line 124, wherein the circuit Layer 12 is covered by an insulating layer 14. The foregoing insulating layer 14 may be a solder resist layer or an ABF resin layer. As shown in FIG. 2B, an alkali-resistant film 18 is formed directly on the insulating layer 14, which is resistant to high temperatures and is resistant to lye used in electroless copper plating or electroplating in an electroless copper plating bath. According to an embodiment of the present invention, the alkali-resistant film 18 is directly formed on the insulating layer 14 and is in direct contact with the insulating layer 14.
如第2C圖所示，於抗鹼膜18上形成一濺鍍銅層20。如第2D圖所示，於濺鍍銅層20、抗鹼膜18及絕緣層14中以雷射鑽孔法形成至少一開孔32，顯露出接墊122。如第2E圖所示，於濺鍍銅層20上以及開孔32之側壁、底部均勻形成一晶種層36，例如，含鈀金屬層。根據本發明之實施例，晶種層36可以是一種不連續之含鈀金屬層，其可具有孔隙，容許蝕刻液通過。As shown in Fig. 2C, a sputtered copper layer 20 is formed on the alkali resistant film 18. As shown in FIG. 2D, at least one opening 32 is formed in the sputtered copper layer 20, the alkali-resistant film 18, and the insulating layer 14 by a laser drilling method to expose the pads 122. As shown in FIG. 2E, a seed layer 36, for example, a palladium-containing metal layer, is uniformly formed on the sputtered copper layer 20 and on the sidewalls and bottom of the opening 32. In accordance with an embodiment of the present invention, seed layer 36 can be a discontinuous palladium-containing metal layer that can have pores that permit passage of etchant.
接著，如第2F圖所示，以濕式化學微蝕法，例如，過硫酸鈉/硫酸溶液，去除濺鍍銅層20，根據本發明之實施例，由於該濕式化學微蝕法僅會經由晶種層36的孔隙，選擇性的蝕刻濺鍍銅層20，故可以將濺鍍銅層20上之晶種層36一併去除，僅留下位於開孔32側壁之晶種層36。如第2G圖所示，可接著在晶種層36上形成一化銅層42。如第2H圖所示，於化銅層42上繼續形成一導電層150，填滿開孔32。導電層150可以是化銅層、銀膏、錫膏或銅膏。如第2I圖所示，去除抗鹼膜18，顯露出導電層150之上部152。另外，如第2J圖所示，可以在顯露出來的導電層150之上部152的表面上形成一保護層60。前述之保護層60係選自以下組合之一者：有機保焊劑、化鎳鈀浸金，以及化錫。Next, as shown in FIG. 2F, the sputtered copper layer 20 is removed by a wet chemical microetching method, for example, a sodium persulfate/sulfuric acid solution, according to an embodiment of the present invention, since the wet chemical microetching method only The copper layer 20 is selectively etched through the pores of the seed layer 36, so that the seed layer 36 on the sputtered copper layer 20 can be removed together, leaving only the seed layer 36 on the sidewalls of the opening 32. As shown in FIG. 2G, a copper layer 42 can then be formed on the seed layer 36. As shown in FIG. 2H, a conductive layer 150 is formed on the copper layer 42 to fill the opening 32. The conductive layer 150 may be a copper layer, a silver paste, a solder paste or a copper paste. As shown in Fig. 2I, the alkali-resistant film 18 is removed to expose the upper portion 152 of the conductive layer 150. Further, as shown in FIG. 2J, a protective layer 60 may be formed on the surface of the upper portion 152 of the exposed conductive layer 150. The aforementioned protective layer 60 is selected from one of the following combinations: an organic solder resist, a nickel-palladium immersion gold, and a tin.
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.
10．．．基板10. . . Substrate
12．．．線路層12. . . Circuit layer
122．．．接墊122. . . Pad
124．．．細線路124. . . Fine line
14．．．絕緣層14. . . Insulation
16．．．第一導電層16. . . First conductive layer
18．．．抗鹼膜18. . . Anti-alkali film
20．．．第二導電層、濺鍍銅層20. . . Second conductive layer, sputtered copper layer
32．．．開孔32. . . Opening
36．．．晶種層36. . . Seed layer
42．．．化銅層42. . . Copper layer
50．．．第三導電層50. . . Third conductive layer
150．．．導電層150. . . Conductive layer
52、152．．．上部52, 152. . . Upper
152．．．上部152. . . Upper
60．．．保護層60. . . The protective layer
第1A圖至第1L圖為依據本發明一實施例所繪示的電路板剖面示意圖。1A through 1L are schematic cross-sectional views of a circuit board according to an embodiment of the invention.
第2A圖至第2J圖為依據本發明另一實施例所繪示的電路板剖面示意圖。2A to 2J are schematic cross-sectional views of a circuit board according to another embodiment of the present invention.
10．．．基板10. . . Substrate
12．．．線路層12. . . Circuit layer
122．．．接墊122. . . Pad
124．．．細線路124. . . Fine line
14．．．絕緣層14. . . Insulation
16．．．第一導電層16. . . First conductive layer
18．．．抗鹼膜18. . . Anti-alkali film
20．．．第二導電層20. . . Second conductive layer
32．．．開孔32. . . Opening
36．．．晶種層36. . . Seed layer
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100144805A TWI433285B (en) | 2011-12-06 | 2011-12-06 | Method of forming metal bumps |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW100144805A TWI433285B (en) | 2011-12-06 | 2011-12-06 | Method of forming metal bumps |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TW201324713A TW201324713A (en) | 2013-06-16 |
| TWI433285B true TWI433285B (en) | 2014-04-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW100144805A TWI433285B (en) | 2011-12-06 | 2011-12-06 | Method of forming metal bumps |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI433285B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10477678B1 (en) | 2019-01-09 | 2019-11-12 | Unimicron Technology Corp. | Substrate structure and manufacturing method thereof |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9620580B2 (en) | 2013-10-25 | 2017-04-11 | Mediatek Inc. | Semiconductor structure |
| TWI831200B (en) * | 2022-05-11 | 2024-02-01 | 欣興電子股份有限公司 | Method for manufacturing circuit board and stacked structure |
-
2011
- 2011-12-06 TW TW100144805A patent/TWI433285B/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10477678B1 (en) | 2019-01-09 | 2019-11-12 | Unimicron Technology Corp. | Substrate structure and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201324713A (en) | 2013-06-16 |
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| MM4A | Annulment or lapse of patent due to non-payment of fees |